SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 D Easily Interfaced to Microprocessors D On-Chip Data Latches D Monotonic Over the Entire A/D Conversion D D D OUT1 OUT2 GND DB7 DB6 DB5 DB4 DB3 Range Segmented High-Order Bits Ensure Low-Glitch Output Interchangeable With Analog Devices AD7524, PMI PM-7524, and Micro Power Systems MP7524 Fast Control Signaling for Digital Signal-Processor Applications Including Interface With TMS320 CMOS Technology 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 RFB REF VDD WR CS DB0 DB1 DB2 FN PACKAGE (TOP VIEW) KEY PERFORMANCE SPECIFICATIONS Resolution Linearity error Power dissipation at VDD = 5V Setting time Propagation delay time 1 OUT2 OUT1 NC RFB REF D D, N, OR PW PACKAGE (TOP VIEW) 8 Bits 1/2LSB Max 5mW Max 100ns Max 80ns Max GND DB7 NC DB6 DB5 description 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 VDD WR NC CS DB0 DB4 DB3 NC DB2 DB1 The TLC7524C, TLC7524E, and TLC7524I are CMOS, 8-bit, digital-to-analog converters (DACs) designed for easy interface to most popular microprocessors. 4 NC−No internal connection The devices are 8-bit, multiplying DACs with input latches and load cycles similar to the write cycles of a random access memory. Segmenting the high-order bits minimizes glitches during changes in the most significant bits, which produce the highest glitch impulse. The devices provide accuracy to 1/2LSB without the need for thin-film resistors or laser trimming, while dissipating less than 5mW typically. Featuring operation from a 5V to 15V single supply, these devices interface easily to most microprocessor buses or output ports. The 2- or 4-quadrant multiplying makes these devices an ideal choice for many microprocessor-controlled gain-setting and signal-control applications. The TLC7524C is characterized for operation from 0°C to 70°C. The TLC7524I is characterized for operation from −25°C to +85°C. The TLC7524E is characterized for operation from − 40°C to +85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright 1998−2007, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 functional block diagram REF R 15 2R R 2R R 2R 2R 2R 16 S-1 S-2 S-3 S-8 R 1 2 CS WR 12 3 Data Latches 13 4 DB7 (MSB) 5 DB6 6 DB5 RFB OUT1 OUT2 GND 11 DB0 (LSB) Data Inputs Terminal numbers shown are for the D or N package. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to 16.5V Digital input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to VDD + 0.3V Reference voltage, Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25V Peak digital input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µA Operating free-air temperature range, TA: TLC7524C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C TLC7524I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25°C to +85°C TLC7524E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to +85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C Case temperature for 10 seconds, TC: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C Lead temperature 1,6mm (1/16 inch) from case for 10 seconds: D, N, or PW package . . . . . . . . . . . +260°C package/ordering information For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 recommended operating conditions Supply voltage, VDD VDD = 5V MIN NOM MAX VDD = 15V MIN NOM MAX 4.75 14.5 5 5.25 ± 10 Reference voltage, Vref High-level input voltage, VIH 15 2.4 V 0.8 40 CS hold time, th(CS) V V 13.5 Low-level input voltage, VIL CS setup time, tsu(CS) 15.5 ± 10 UNIT 1.5 V 40 ns 0 0 ns Data bus input setup time, tsu(D) 25 25 ns Data bus input hold time, th(D) 10 10 ns Pulse duration, WR low, tw(WR) 40 40 TLC7524C Operating free-air temperature, TA ns 0 +70 0 +70 TLC7524I −25 +85 −25 +85 TLC7524E −40 +85 −40 +85 °C C electrical characteristics over recommended operating free-air temperature range, Vref = ±10V, OUT1 and OUT2 at GND (unless otherwise noted) PARAMETER IIH IIL IIkg TEST CONDITIONS High-level input current Low-level input current Output leakage current MIN VDD = 5V TYP MAX VI = VDD VI = 0 10 10 µA µA −10 −10 OUT1 WR, CS at 0V, ± 400 ± 200 OUT2 DB0−DB7 at VDD, Vref = ± 10V WR, CS at 0V, ± 400 ± 200 Quiescent DB0−DB7 at VIHmin or VILmax 1 2 mA Standby DB0−DB7 at 0V or VDD 500 500 µA 0.04 %FSR/% Supply current kSVS Supply voltage sensitivity, ∆gain/∆VDD ∆VDD = ± 10% Ci Input capacitance, DB0−DB7, WR, CS VI = 0 nA 0.01 OUT2 DB0−DB7 at 0V, WR, CS at 0V OUT1 OUT2 DB0−DB7 at VDD, 0.16 0.005 5 OUT1 Output capacitance UNIT DB0−DB7 at 0V, Vref = ± 10V IDD Co VDD = 15V TYP MAX MIN WR, CS at 0V Reference input impedance (REF to GND) 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 30 30 120 120 120 120 30 30 20 5 20 pF pF kΩ 3 SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 operating characteristics over recommended operating free-air temperature range, Vref = ±10V, OUT1 and OUT2 at GND (unless otherwise noted) PARAMETER TEST CONDITIONS VDD = 5V MIN TYP MAX VDD = 15V TYP MIN MAX UNIT ± 0.5 ± 0.5 LSB Linearity error Gain error See Note 1 ± 2.5 ± 2.5 LSB Settling time (to 1/2 LSB) See Note 2 100 100 ns Propagation delay from digital input to 90% of final analog output current See Note 2 80 80 ns Feedthrough at OUT1 or OUT2 Vref = ±10V (100kHz sinewave) WR and CS at 0V, DB0−DB7 at 0V 0.5 0.5 %FSR Temperature coefficient of gain TA = +25°C to MAX ± 0.004 ± 0.001 NOTES: 1. Gain error is measured using the internal feedback resistor. Nominal full-scale range (FSR) = Vref − 1LSB. 2. OUT1 load = 100Ω, Cext = 13pF, WR at 0V, CS at 0V, DB0 − DB7 at 0V to VDD or VDD to 0V. operating sequence tsu(CS) th(CS) CS tw(WR) WR ÎÎÎ ÎÎÎ tsu(D) DB0−DB7 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 th(D) %FSR/°C SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 PRINCIPLES OF OPERATION voltage-mode operation It is possible to operate the current-multiplying DAC in these devices in a voltage mode. In the voltage mode, a fixed voltage is placed on the current output terminal. The analog output voltage is then available at the reference voltage terminal. Figure 1 is an example of a current-multiplying DAC, which is operated in voltage mode. R R R REF (Analog Output Voltage) 2R 2R 2R 0 2R 1 R OUT1 (Fixed Input Voltage) OUT2 Figure 1. Voltage Mode Operation The relationship between the fixed-input voltage and the analog-output voltage is given by the following equation: VO = VI (D/256) where VO = analog output voltage VI = fixed input voltage D = digital input code converted to decimal In voltage-mode operation, these devices meet the following specification: PARAMETER Linearity error at REF TEST CONDITIONS VDD = 5V, OUT1 = 2.5V, POST OFFICE BOX 655303 OUT2 at GND, • DALLAS, TEXAS 75265 MIN TA = +25°C MAX UNIT 1 LSB 5 SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 PRINCIPLES OF OPERATION The TLC7524C, TLC7524E, and TLC7524I are 8-bit multiplying DACs consisting of an inverted R-2R ladder, analog switches, and data input latches. Binary-weighted currents are switched between the OUT1 and OUT2 bus lines, thus maintaining a constant current in each ladder leg independent of the switch state. The high-order bits are decoded. These decoded bits, through a modification in the R-2R ladder, control three equally-weighted current sources. Most applications only require the addition of an external operational amplifier and a voltage reference. The equivalent circuit for all digital inputs low is seen in Figure 2. With all digital inputs low, the entire reference current, Iref, is switched to OUT2. The current source I/256 represents the constant current flowing through the termination resistor of the R-2R ladder, while the current source IIkg represents leakage currents to the substrate. The capacitances appearing at OUT1 and OUT2 are dependent upon the digital input code. With all digital inputs high, the off-state switch capacitance (30pF maximum) appears at OUT2 and the on-state switch capacitance (120pF maximum) appears at OUT1. With all digital inputs low, the situation is reversed as shown in Figure 2. Analysis of the circuit for all digital inputs high is similar to Figure 2; however, in this case, Iref would be switched to OUT1. The DAC on these devices interfaces to a microprocessor through the data bus and the CS and WR control signals. When CS and WR are both low, analog output on these devices responds to the data activity on the DB0−DB7 data bus inputs. In this mode, the input latches are transparent and input data directly affects the analog output. When either the CS signal or WR signal goes high, the data on the DB0−DB7 inputs are latched until the CS and WR signals go low again. When CS is high, the data inputs are disabled regardless of the state of the WR signal. These devices are capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for 2-quadrant or 4-quadrant multiplication are shown in Figure 3 and Figure 4. Table 1 and Table 2 summarize input coding for unipolar and bipolar operation respectively. RFB R OUT1 30 pF IIkg Iref REF OUT2 I/256 120 pF IIkg Figure 2. TLC7524 Equivalent Circuit With All Digital Inputs Low 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 PRINCIPLES OF OPERATION VDD Vref RA = 2 kΩ (see Note A) RB C (see Note B) RFB DB0−DB7 OUT1 − OUT2 + Output CS WR GND NOTES: A. RA and RB used only if gain adjustment is required. B. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation. Figure 3. Unipolar Operation (2-Quadrant Multiplication) Vref VDD 20 kΩ RA = 2 kΩ (see Note A) RB CS WR − C (see Note B) RFB DB0−DB7 20 kΩ Output OUT1 − OUT2 + + 10 kΩ 5 kΩ GND NOTES: A. RA and RB used only if gain adjustment is required. B. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation. Figure 4. Bipolar Operation (4-Quadrant Operation) Table 1. Unipolar Binary Code DIGITAL INPUT (see Note 3) MSB ANALOG OUTPUT LSB 11111111 10000001 10000000 01111111 00000001 00000000 Table 2. Bipolar (Offset Binary) Code DIGITAL INPUT (see Note 4) MSB ANALOG OUTPUT LSB −Vref (255/256) −Vref (129/256) 11111111 10000001 Vref (127/128) Vref (1/128) −Vref (128/256) = − Vref/2 −Vref (127/256) 10000000 0 01111111 −Vref (1/256) 0 00000001 −Vref (1/128) −Vref (127/128) 00000000 −Vref NOTE 3: LSB = 1/256 (Vref) NOTE 4: LSB = 1/128 (Vref) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 PRINCIPLES OF OPERATION microprocessor interfaces D0−D7 Data Bus Z−80A DB0−DB7 WR TLC7524 WR OUT1 OUT2 CS IORQ Decode Logic Address Bus A0−A15 Figure 5. TLC7524: Z-80A Interface Data Bus D0−D7 6800 DB0−DB7 φ2 WR TLC7524 OUT1 OUT2 CS VMA A0−A15 Decode Logic Address Bus Figure 6. TLC7524: 6800 Interface 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 PRINCIPLES OF OPERATION microprocessor interfaces (continued) A8−A15 Address Bus 8051 Decode Logic 8-Bit Latch CS WR ALE TLC7524 DB0−DB7 OUT1 OUT2 WR AD0−AD7 Adress/Data Bus Figure 7. TLC7524: 8051 Interface POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 Revision History DATE REV 6/07 D PAGE SECTION DESCRIPTION Front Page — Deleted Available Options table. 2 — Inserted Package/Ordering information. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. PACKAGE OPTION ADDENDUM www.ti.com 5-Oct-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLC7524CD ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7524CDG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7524CDR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7524CDRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7524CFN ACTIVE PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLC7524CFNG3 ACTIVE PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLC7524CFNR ACTIVE PLCC FN 20 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLC7524CFNRG3 ACTIVE PLCC FN 20 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLC7524CN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC7524CNE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC7524CNS ACTIVE SO NS 16 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7524CNSG4 ACTIVE SO NS 16 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7524CNSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7524CNSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7524CPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7524CPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7524CPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7524CPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7524ED ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7524EDG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7524EDR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7524EDRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7524EN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC7524ENE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC7524ID ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 5-Oct-2007 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLC7524IDG4 ACTIVE SOIC D 16 TLC7524IDR ACTIVE SOIC D TLC7524IDRG4 ACTIVE SOIC TLC7524IFN ACTIVE TLC7524IFNG3 40 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM ACTIVE PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLC7524IFNR ACTIVE PLCC FN 20 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLC7524IFNRG3 ACTIVE PLCC FN 20 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLC7524IN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC7524INE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC7524IPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7524IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7524IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7524IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 5-Oct-2007 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLC7524CDR Package Package Pins Type Drawing SOIC SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TLC7524CNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 TLC7524CPWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 TLC7524EDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TLC7524IDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TLC7524IPWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC7524CDR SOIC D 16 2500 346.0 346.0 33.0 TLC7524CNSR SO NS 16 2000 346.0 346.0 33.0 TLC7524CPWR TSSOP PW 16 2000 346.0 346.0 29.0 TLC7524EDR SOIC D 16 2500 346.0 346.0 33.0 TLC7524IDR SOIC D 16 2500 346.0 346.0 33.0 TLC7524IPWR TSSOP PW 16 2000 346.0 346.0 29.0 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56) 44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10) 52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37) 68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91) 84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45) 4040005 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. 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