SCDS148 − OCTOBER 2003
D Output Voltage Translation Tracks VCC
D Supports Mixed-Mode Signal Operation On
D
D
D
D
D
D
D VCC Operating Range From 2.3 V to 3.6 V
D Data I/Os Support 0 to 5-V Signaling Levels
All Data I/O Ports
− 5-V Input Down To 3.3-V Output Level
Shift With 3.3-V VCC
− 5-V/3.3-V Input Down To 2.5-V Output
Level Shift With 2.5-V VCC
5-V Tolerant I/Os With Device Powered-Up
or Powered-Down
Bidirectional Data Flow, With Near-Zero
Propagation Delay
Low ON-State Resistance (ron)
Characteristics (ron = 5 Ω Typical)
Low Input/Output Capacitance Minimizes
Loading (Cio(OFF) = 5 pF Typical)
Data and Control Inputs Provide
Undershoot Clamp Diodes
Low Power Consumption
(ICC = 20 µA Max)
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
D Control Inputs Can be Driven by TTL or
D
D
D
D
D
5-V/3.3-V CMOS Outputs
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 1000-V Charged-Device Model (C101)
Supports Digital Applications: Level
Translation, USB Interface, Memory
Interleaving, Bus Isolation
Ideal for Low-Power Portable Equipment
D, DBQ, DGV, OR PW PACKAGE
(TOP VIEW)
1OE
S1
1B4
1B3
1B2
1B1
1A
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
2OE
S0
2B4
2B3
2B2
2B1
2A
description/ordering information
The SN74CB3T3253 is a high-speed TTL-compatible FET multiplexer/demultiplexer with low ON-state
resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation
on all data I/O ports by providing voltage translation that tracks VCC. The SN74CB3T3253 supports systems
using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels
(see Figure 1).
The SN74CB3T3253 is organized as two 1-of-4 multiplexer/demultiplexers with separate output-enable (1OE,
2OE) inputs. The select (S0, S1) inputs control the data path of each multiplexer/demultiplexer. When OE is low,
the associated multiplexer/demultiplexer is ON, and the A port is connected to the B port, allowing bidirectional
data flow between ports. When OE is high, the associated multiplexer/demultiplexer is OFF, and a
high-impedance state exists between the A and B ports.
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
!"#$%&'#! ( )*$$+!' &( #" ,*-.)&'#! /&'+
$#/*)'( )#!"#$% '# (,+)")&'#!( ,+$ '0+ '+$%( #" +1&( !('$*%+!'(
('&!/&$/ 2&$$&!'3 $#/*)'#! ,$#)+((!4 /#+( !#' !+)+((&$.3 !).*/+
'+('!4 #" &.. ,&$&%+'+$(
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1
SCDS148 − OCTOBER 2003
description/ordering information (continued)
VCC
5.5 V
VCC
IN
≈VCC − 1 V
≈VCC
OUT
≈VCC − 1 V
CB3T
0V
0V
Input Voltages
Output Voltages
NOTE A: If the input high voltage (VIH) level is greater than or equal to VCC − 1 V, and less than or equal to 5.5 V, then the output high voltage
(VOH) level will be equal to approximately the VCC voltage level.
Figure 1. Typical DC Voltage-Translation Characteristics
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
SOIC − D
SSOP (QSOP) − DBQ
−40°C to 85°C
TSSOP − PW
Tube
SN74CB3T3253D
Tape and reel
SN74CB3T3253DR
Tape and reel
SN74CB3T3253DBQR
Tube
SN74CB3T3253PW
Tape and reel
SN74CB3T3253PWR
TOP-SIDE
MARKING
CB3T3253
KS253
KS253
TVSOP − DGV
Tape and reel
SN74CB3T3253DGVR
KS253
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each multiplexer/demultiplexer)
INPUTS
2
INPUT/OUTPUT
A
FUNCTION
L
B1
A port = B1 port
H
B2
A port = B2 port
L
B3
A port = B3 port
H
H
B4
A port = B4 port
X
X
Z
Disconnect
OE
S1
L
L
L
L
L
H
L
H
S0
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SCDS148 − OCTOBER 2003
logic diagram (positive logic)
7
1A
6
SW
5
SW
1B1
1B2
4
SW
1B3
3
1B4
SW
9
10
2A
2B1
SW
11
SW
2B2
12
2B3
SW
13
SW
2B4
14
S0
2
S1
1
1OE
2OE
15
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3
SCDS148 − OCTOBER 2003
simplified schematic, each FET switch (SW)
† Gate Voltage (VG) is approximately
equal to VCC + VT when the switch is ON
and VI > VCC + VT.
A
B
VG†
Control
Circuit
EN‡
‡ EN is the internal enable signal applied to the switch.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)§
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
ON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mA
Continuous current through VCC or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 5): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
§ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. VI and VO are used to denote specific conditions for VI/O.
4. II and IO are used to denote specific conditions for II/O.
5. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 6)
VCC
Supply voltage
VIH
High-level control input voltage
VIL
Low-level control input voltage
VI/O
TA
Data input/output voltage
MIN
MAX
2.3
3.6
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
1.7
5.5
2
5.5
0
0.7
VCC = 2.7 V to 3.6 V
0
0.8
0
5.5
V
−40
85
°C
Operating free-air temperature
UNIT
V
V
V
NOTE 6: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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SCDS148 − OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VCC = 3 V,
II = −18 mA
VOH
See Figures 3 and 4
IIN
Control inputs
IOZ‡
VCC = 3.6 V,
VO = 0 to 5.5 V,
VI = 0,
Switch OFF,
VIN = VCC or GND
Ioff
VCC = 0,
VO = 0 to 5.5 V,
VI = 0,
ICC
∆ICC§
Control inputs
Cin
Control inputs
A port
Cio(OFF)
B port
A port
Cio(ON)
B port
ron¶
TYP†
VCC = 3.6 V,
VIN = 3.6 V to 5.5 V or GND
VCC = 3.6 V,
Switch ON,
VIN = VCC or GND
II
MIN
VCC = 3.6 V,
II/O = 0,
Switch ON or OFF,
VIN = VCC or GND
VCC = 3 V to 3.6 V,
One input at VCC − 0.6 V,
Other inputs at VCC or GND
UNIT
−1.2
V
±10
µA
±20
VI = VCC − 0.7 V to 5.5 V
VI = 0.7 V to VCC − 0.7 V
−40
µA
±5
VI = 0 to 0.7 V
±10
µA
10
µA
VI = VCC or GND
20
VI = 5.5 V
20
A
µA
300
VCC = 3.3 V,
VIN = VCC or GND
3
VCC = 3.3 V,
VI/O = 5.5 V, 3.3 V, or GND,
Switch OFF,
VIN = VCC or GND
VCC = 3.3 V,
Switch ON,
VIN = VCC or GND
MAX
µA
pF
12
pF
5
VI/O = 5.5 V or 3.3 V
VI/O = GND
10
VI/O = 5.5 V or 3.3 V
VI/O = GND
4
22
pF
22
VCC = 2.3 V,
TYP at VCC = 2.5 V,
VI = 0
IO = 24 mA
5
8
IO = 16 mA
5
8
VCC = 3 V,
VI = 0
IO = 64 mA
IO = 32 mA
5
7
5
7
Ω
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
† All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
§ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
¶ Measured by the voltage drop between A and B terminals at the indicated current through the switch. ON-state resistance is determined by the
lower of the voltages of the two (A or B) terminals.
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SCDS148 − OCTOBER 2003
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 2)
PARAMETER
tpd†
tpd(s)
ten
tdis
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
S
A
1
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
0.15
UNIT
MAX
0.25
ns
ns
10.5
1
8
S
B
1
10
1
8
OE
A or B
1
8.5
1
8
S
B
1
7.5
1
8.5
OE
A or B
1
6.5
1
8
ns
ns
† The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).
6
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SCDS148 − OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
VCC
Input Generator
VIN
50 Ω
50 Ω
VG1
TEST CIRCUIT
DUT
Input Generator
VI
S1
RL
VO
50 Ω
VG2
CL
(see Note A)
RL
TEST
VCC
S1
RL
VI
CL
tpd(s)
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
3.6 V or GND
5.5 V or GND
30 pF
50 pF
tPLZ/tPZL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2 × VCC
2 × VCC
500 Ω
500 Ω
GND
GND
30 pF
50 pF
0.15 V
0.3 V
tPHZ/tPZH
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
3.6 V
5.5 V
30 pF
50 pF
0.15 V
0.3 V
Output
Control
(VIN)
V∆
VCC
VCC/2
VCC
VCC/2
0V
tPLH
VOH
Output
VCC/2
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLZ
VCC
VCC/2
tPZH
tPHL
VCC/2
VOL
VCC/2
0V
tPZL
VCC/2
Open
GND
50 Ω
Output
Control
(VIN)
2 × VCC
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (tpd(s))
VOL + V∆
VOL
tPHZ
VCC/2
VOH − V∆
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: B. CL includes probe and jig capacitance.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
E. The outputs are measured one at a time with one transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state
resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
I. All parameters and waveforms are not applicable to all devices.
Figure 2. Test Circuit and Voltage Waveforms
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SCDS148 − OCTOBER 2003
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
4.0
VCC = 2.3 V
IO = 1 µA
TA = 25°C
3.0
V − Output Voltage − V
O
V − Output Voltage − V
O
4.0
2.0
1.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
3.0
VCC = 3 V
IO = 1 µA
TA = 25°C
2.0
1.0
0.0
0.0
1.0
VI − Input Voltage − V
2.0
POST OFFICE BOX 655303
4.0
VI − Input Voltage − V
Figure 3. Data Output Voltage vs Data Input Voltage
8
3.0
• DALLAS, TEXAS 75265
5.0
6.0
SCDS148 − OCTOBER 2003
TYPICAL CHARACTERISTICS (continued)
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
V
− Output Voltage High − V
OH
3.5
4.0
VCC = 2.3 V to 3.6 V
VI = 5.5 V
TA = 85°C
100 µA
8 mA
16 mA
24 mA
3.0
2.5
2.0
1.5
2.3
2.5
2.7
2.9
3.1
3.3
3.5
VCC = 2.3 V to 3.6 V
VI = 5.5 V
TA = 25°C
3.5
100 µA
8 mA
16 mA
24 mA
3.0
2.5
2.0
1.5
3.7
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
VCC − Supply Voltage − V
VCC − Supply Voltage − V
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
4.0
V
− Output Voltage High − V
OH
V
− Output Voltage High − V
OH
4.0
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
3.5
VCC = 2.3 V to 3.6 V
VI = 5.5 V
TA = −40°C
100 µA
8 mA
16 mA
24 mA
3.0
2.5
2.0
1.5
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
VCC − Supply Voltage − V
Figure 4. VOH Values
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9
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
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MSOI004E JANUARY 1995 − REVISED MAY 2002
DBQ (R−PDSO−G**)
PLASTIC SMALL−OUTLINE PACKAGE
0.012 (0,30)
0.008 (0,20)
0.025 (0,64)
0.005 (0,13)
13
24
0.244 (6,20)
0.228 (5,80)
0.157 (3,99)
0.150 (3,81)
0.008 (0,20) NOM
Gauge Plane
1
12
0.010 (0,25)
A
0°−8°
0.035 (0,89)
0.016 (0,40)
0.069 (1,75) MAX
Seating Plane
0.010 (0,25)
0.004 (0,10)
0.004 (0,10)
PINS **
16
20
24
28
A MAX
0.197
(5,00)
0.344
(8,74)
0.344
(8,74)
0.394
(10,01)
A MIN
0.189
(4,80)
0.337
(8,56)
0.337
(8,56)
0.386
(9,80)
M0−137
VARIATION
AB
AD
AE
AF
DIM
D
4073301/F 02/2002
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO−137.
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1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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