TI SN74CB3T16210DGGR

www.ti.com
SN74CB3T16210
20-BIT FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH WITH 5-V-TOLERANT LEVEL SHIFTER
FEATURES
•
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•
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Member of the Texas Instruments Widebus™
Family
Output Voltage Translation Tracks VCC
Supports Mixed-Mode Signal Operation on All
Data I/O Ports
– 5-V Input Down to 3.3-V Output Level Shift
With 3.3-V VCC
– 5-V/3.3-V Input Down to 2.5-V Output Level
Shift With 2.5-V VCC
5-V-Tolerant I/Os With Device Powered Up or
Powered Down
Bidirectional Data Flow With Near-Zero
Propagation Delay
Low ON-State Resistance (ron) Characteristics
(ron = 5 Ω Typ)
Low Input/Output Capacitance Minimizes
Loading (Cio(OFF) = 5 pF Typ)
Data and Control Inputs Provide Undershoot
Clamp Diodes
Low Power Consumption
(ICC = 40 µA Max)
VCC Operating Range From 2.3 V to 3.6 V
Data I/Os Support 0- to 5-V Signaling Levels
(0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
Supports Digital Applications: Level
Translation, PCI Interface, USB Interface,
Memory Interleaving, and Bus Isolation
Ideal for Low-Power Portable Equipment
SCDS156A – OCTOBER 2003 – REVISED MARCH 2005
DGG OR DGV PACKAGE
(TOP VIEW)
NC
1A1
1A2
1A3
1A4
1A5
1A6
GND
1A7
1A8
1A9
1A10
2A1
2A2
VCC
2A3
GND
2A4
2A5
2A6
2A7
2A8
2A9
2A10
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1OE
2OE
1B1
1B2
1B3
1B4
1B5
GND
1B6
1B7
1B8
1B9
1B10
2B1
2B2
2B3
GND
2B4
2B5
2B6
2B7
2B8
2B9
2B10
NC - No internal connection
DESCRIPTION/ORDERING INFORMATION
The SN74CB3T16210 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron),
allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O
ports by providing voltage translation that tracks VCC. The SN74CB3T16210 supports systems using 5-V TTL,
3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2005, Texas Instruments Incorporated
SN74CB3T16210
20-BIT FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS156A – OCTOBER 2003 – REVISED MARCH 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The SN74CB3T16210 is organized as two 10-bit bus switches with separate ouput-enable (1OE, 2OE) inputs. It
can be used as two 10-bit bus switches or as one 20-bit bus switch. When OE is low, the associated 10-bit bus
switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE
is high, the associated 10-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging
current will not backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
PACKAGE (1)
TA
–40°C to 85°C
(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
TSSOP – DGG
Tape and reel
SN74CB3T16210DGGR
CB3T16210
TVSOP – DGV
Tape and reel
SN74CB3T16210DGVR
KR210
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
(EACH 10-BIT BUS SWITCH)
INPUT
OE
INPUT/OUTPUT
A
FUNCTION
L
B
A port = B port
H
Z
Disconnect
VCC
5.5 V
VCC
IN
VCC - 1 V
OUT
VCC
VCC - 1 V
CB3T
0V
0V
Input Voltages
Output Voltages
If the input high voltage (VIH) level is greater than or equal to VCC - 1 V, and less than or equal to 5.5 V, the output high voltage (VOH) level will
be equal to approximately the VCC voltage level.
Figure 1. Typical DC Voltage Translation Characteristics
2
SN74CB3T16210
20-BIT FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS156A – OCTOBER 2003 – REVISED MARCH 2005
TERMINAL ASSIGNMENTS (1)
GQL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
A
1A2
B
1A5
1A1
NC
1OE
2OE
1B1
1A4
1A3
1B2
1B3
C
1B4
NC
GND
1A6
1B5
1B6
B
NC
D
1A8
NC
1A7
NC
1B7
1B8
C
E
1A10
1A9
1B9
1B10
D
F
2A1
2A2
2B2
2B1
E
G
VCC
GND
2A3
GND
2B4
2B3
F
H
NC
NC
2A4
2B5
NC
NC
G
J
2A5
2A6
2A7
2B7
2B6
2B5
H
K
2A8
2A9
2A10
2B10
2B9
2B8
1
2
3
4
5
6
A
J
K
(1)
NC - No internal connection
LOGIC DIAGRAM (POSITIVE LOGIC)
2
1A1
46
1B1
SW
12
1A10
36
1B10
SW
48
1OE
13
2A1
35
25
24
2A10
2OE
2B1
SW
SW
2B10
47
3
SN74CB3T16210
20-BIT FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS156A – OCTOBER 2003 – REVISED MARCH 2005
SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW)
A
B
VG(1)
Control
Circuit
EN(2)
(1) Gate voltage (VG) is equal to approximately VCC + VT when the switch is ON
and VI > VCC + VT.
(2) EN is the internal enable signal applied to the switch.
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
7
V
VIN
Control input voltage range (2) (3)
–0.5
7
V
VI/O
Switch I/O voltage range (2) (3) (4)
–0.5
7
V
IIK
Control input clamp current
VIN < 0
–50
mA
II/OK
I/O port clamp current
VI/O < 0
–50
mA
IIO
ON-state switch current (5)
±128
mA
Continuous current through VCC or GND
±100
mA
θJA
Package thermal impedance (6)
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
(5)
(6)
4
DGG package
70
DGV package
58
–65
150
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground unless otherwise specified.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
VI and VO are used to denote specific conditions for VI/O.
II and IO are used to denote specific conditions for II/O.
The package thermal impedance is calculated in accordance with JESD 51-7.
www.ti.com
SN74CB3T16210
20-BIT FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH WITH 5-V-TOLERANT LEVEL SHIFTER
SCDS156A – OCTOBER 2003 – REVISED MARCH 2005
Recommended Operating Conditions
VCC
Supply voltage
VIH
High-level control input voltage
VIL
Low-level control input voltage
VI/O
Data input/output voltage
TA
Operating free-air temperature
(1)
(1)
MIN
MAX
UNIT
2.3
3.6
VCC = 2.3 V to 2.7 V
1.7
5.5
V
VCC = 2.7 V to 3.6 V
2
5.5
VCC = 2.3 V to 2.7 V
0
0.7
VCC = 2.7 V to 3.6 V
0
0.8
0
5.5
V
–40
85
°C
V
V
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics (1)
PARAMETER
VIK
TEST CONDITIONS
MIN
TYP (2)
VCC = 3 V, II = –18 mA
VOH
MAX
UNIT
–1.2
V
±10
µA
See Figure 3 and Figure 4
Control
inputs
IIN
VCC = 3.6 V, VIN = 3.6 V to 5.5 V or GND
VCC = 3.6 V,
Switch ON,
VIN = VCC or GND
II
VI = VCC – 0.7 V to 5.5 V
±20
VI = 0.7 V to VCC – 0.7 V
–40
VCC = 3.6 V, VO = 0 to 5.5 V, VI = 0, Switch OFF, VIN = VCC or GND
Ioff
VCC = 0, VO = 0 to 5.5 V, VI = 0,
ICC
VCC = 3.6 V, II/O = 0,
Switch ON or OFF, VIN = VCC or GND
Control
inputs
VCC = 3.3 V, VIN = VCC or GND
VCC = 3.3 V, VI/O = 5.5 V, 3.3 V, or GND, Switch OFF, VIN = VCC or GND
VCC = 2.3 V, TYP at VCC = 2.5 V, VI = 0
ron (5)
VCC = 3 V, VI = 0
µA
40
Cin
VCC = 3.3 V, Switch ON, VIN = VCC or GND
10
VI = 5.5 V
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND
Cio(ON)
µA
40
Control
inputs
Cio(OFF)
±10
VI = VCC or GND
∆ICC (4)
VI/O = 5.5 V or 3.3 V
µA
±5
VI = 0 to 0.7 V
IOZ (3)
(1)
(2)
(3)
(4)
(5)
TA = –40°C TO 85°C
300
µA
µA
4
pF
5
pF
5
pF
VI/O = GND
13
IO = 24 mA
5
9.5
IO = 16 mA
5
9.5
IO = 64 mA
5
8.5
IO = 32 mA
5
8.5
Ω
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
Measured by the voltage drop between A and B terminals at the indicated current through the switch. ON-state resistance is determined
by the lower of the voltages of the two (A or B) terminals.
5
SN74CB3T16210
20-BIT FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS156A – OCTOBER 2003 – REVISED MARCH 2005
Switching Characteristics
for VCC = 2.5 V ± 0.2 V (see Figure 2)
(1)
6
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
tpd (1)
A or B
B or A
0.25
ns
ten
OE
A or B
1
12
1
10
ns
tdis
OE
A or B
1
7.5
1
8.5
ns
PARAMETER
MIN
MAX
MIN
0.15
UNIT
MAX
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
SN74CB3T16210
20-BIT FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS156A – OCTOBER 2003 – REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION
VCC
Input Generator
VIN
50 Ω
50 Ω
VG1
TEST CIRCUIT
DUT
2 × VCC
Input Generator
S1
RL
VO
VI
50 Ω
50 Ω
VG2
CL
(see Note A)
RL
TEST
VCC
S1
RL
VI
CL
tpd(s)
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
3.6 V or GND
5.5 V or GND
30 pF
50 pF
tPLZ/tPZL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2 × VCC
2 × VCC
500 Ω
500 Ω
GND
GND
30 pF
50 pF
0.15 V
0.3 V
tPHZ/tPZH
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
3.6 V
5.5 V
30 pF
50 pF
0.15 V
0.3 V
Output
Control
(VIN)
V∆
VCC
VCC/2
VCC
VCC/2
VCC/2
0V
tPLH
VOH
Output
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (tpd(s))
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLZ
VCC
VCC/2
VOL + V∆
VOL
tPZH
tPHL
VCC/2
0V
tPZL
Output
Control
(VIN)
Open
GND
Output
Waveform 2
S1 at Open
(see Note B)
tPHZ
VOH
VCC/2
VOH - V∆
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance
of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Test Circuit and Voltage Waveforms
7
SN74CB3T16210
20-BIT FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS156A – OCTOBER 2003 – REVISED MARCH 2005
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE vs INPUT VOLTAGE
OUTPUT VOLTAGE vs INPUT VOLTAGE
4
VCC = 2.3 V
IO = 1 µA
TA = 25°C
3
VO - Output Voltage - V
VO - Output Voltage - V
4
2
1
0
0
1
2
3
4
VI - Input Voltage - V
5
6
VCC = 3 V
IO = 1 µA
TA = 25°C
3
2
1
0
0
1
2
Figure 3. Data Output Voltage vs Data Input Voltage
8
3
VI - Input Voltage - V
4
5
6
SN74CB3T16210
20-BIT FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS156A – OCTOBER 2003 – REVISED MARCH 2005
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE
OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE
VCC = 2.3 V ~ 3.6 V
VI = 5.5 V
TA = 85°C
100 µA
VOH - Output Voltage High - V
3.5
4
8 mA
3
2.5
16 mA
24 mA
2
1.5
2.3
2.5
2.7
2.9
3.1
3.3
3.5
VCC = 2.3 V ~ 3.6 V
VI = 5.5 V
TA = 25°C
3.5
2.5
16 mA
24 mA
2
1.5
2.3
3.7
100 µA
8 mA
3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
VCC - Supply Voltage - V
VCC - Supply Voltage - V
OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE
4
VOH - Output Voltage High - V
VOH - Output Voltage High - V
4
3.5
VCC = 2.3 V ~ 3.6 V
VI = 5.5 V
TA = -40°C
100 µA
8 mA
3
16 mA
2.5
24 mA
2
1.5
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
VCC - Supply Voltage - V
Figure 4. VOH Values
9
PACKAGE OPTION ADDENDUM
www.ti.com
19-May-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74CB3T16210DGGRE4
ACTIVE
TSSOP
DGG
48
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
74CB3T16210DGVRE4
ACTIVE
TVSOP
DGV
48
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74CB3T16210DGG
PREVIEW
TSSOP
DGG
48
40
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74CB3T16210DGGR
ACTIVE
TSSOP
DGG
48
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74CB3T16210DGVR
ACTIVE
TVSOP
DGV
48
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74CB3T16210DL
PREVIEW
SSOP
DL
48
25
TBD
Call TI
Call TI
SN74CB3T16210DLR
PREVIEW
SSOP
DL
48
1000
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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