SN54BCT125A, SN74BCT125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS032F – SEPTEMBER 1988 – REVISED MARCH 2003 D D D Operating Voltage Range of 4.5 V to 5.5 V State-of-the-Art BiCMOS Design Significantly Reduces ICCZ 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers SN54BCT125A . . . J OR W PACKAGE SN74BCT125A . . . D, N, OR NS PACKAGE (TOP VIEW) 1 14 2 13 3 12 4 11 5 10 6 9 7 8 1A 1OE NC VCC 4OE VCC 4OE 4A 4Y 3OE 3A 3Y 1Y NC 2OE NC 2A 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3OE 2Y GND NC 3Y 3A 1OE 1A 1Y 2OE 2A 2Y GND SN54BCT125A . . . FK PACKAGE (TOP VIEW) NC – No internal connection description/ordering information The ’BCT125A bus buffers feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION PDIP – N 0°C to 70°C –55°C to 125°C ORDERABLE PART NUMBER PACKAGE† TA TOP-SIDE MARKING Tube SN74BCT125AN Tube SN74BCT125AD Tape and reel SN74BCT125ADR SOP – NS Tape and reel SN74BCT125ANSR BCT125A CDIP – J Tube SNJ54BCT125AJ SNJ54BCT125AJ CFP – W Tube SNJ54BCT125AW SNJ54BCT125AW LCCC – FK Tube SNJ54BCT125AFK SOIC – D SN74BCT125AN BCT125A SNJ54BCT125AFK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each buffer) INPUTS OE A OUTPUT Y L H H L L L H X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54BCT125A, SN74BCT125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS032F – SEPTEMBER 1988 – REVISED MARCH 2003 logic diagram (positive logic) 1OE 1A 2OE 2A 3OE 3A 4OE 4A 1 2 3 1Y 4 5 6 2Y 10 9 8 3Y 13 12 11 4Y Pin numbers shown are for the D, J, N, NS, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA Current into any output in the low state, IO: SN54BCT125A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74BCT125A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54BCT125A, SN74BCT125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS032F – SEPTEMBER 1988 – REVISED MARCH 2003 recommended operating conditions (see Note 3) SN54BCT125A SN74BCT125A MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IIK Low-level input voltage 0.8 0.8 V Input clamp current –18 –18 mA IOH IOL High-level output current –12 –15 mA Low-level output current 48 64 mA High-level input voltage 2 2 V V TA Operating free-air temperature –55 125 0 70 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V II = –18 mA IOH = –3 mA IOH = –12 mA IOH = –15 mA SN54BCT125A TYP† MAX MIN SN74BCT125A TYP† MAX MIN –1.2 2.4 3.3 2 3.2 –1.2 2.4 V 3.3 V 2 0.38 UNIT 3.1 VOL VCC = 4 4.5 5V IOL = 48 mA IOL = 64 mA 0.55 II IIH VCC = 0, VCC = 5.5 V, VI = 7 V VI = 2.7 V 0.1 0.1 mA 35 25 µA IIL IOZH VCC = 5.5 V, VCC = 5.5 V, VI = 0.5 V VO = 2.7 V –20 –20 µA 50 50 µA IOZL IOS‡ VCC = 5.5 V, VCC = 5.5 V, VO = 0.5 V VO = 0 –50 –50 µA –225 mA ICCH ICCL VCC = 5.5 V, VCC = 5.5 V, Outputs open 19 31 19 31 mA Outputs open 46 49 46 49 mA ICCZ Ci VCC = 5.5 V, VCC = 5 V, Outputs open 6 14 6 14 mA VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V 4 0.42 –100 –225 –100 Co VCC = 5 V, 9 † All typical values are at VCC = 5 V. ‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0.55 V 4 pF 9 pF 3 SN54BCT125A, SN74BCT125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS032F – SEPTEMBER 1988 – REVISED MARCH 2003 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) VCC = 5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = 25°C TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MAX§ ’BCT125A tPLH tPHL A Y tPZH tPZL OE Y tPHZ tPLZ OE Y SN54BCT125A SN74BCT125A MIN TYP MAX MIN MAX MIN MAX 1.6 3.5 5.2 1.6 6 1.6 5.7 2.7 5 6.9 2.7 8 2.7 7.7 3.4 6.7 9 3.4 11.1 3.4 10.3 5 8.2 10.4 5 12.8 5 11.7 3 5.8 7.4 3 9.4 3 8.9 2.8 5.5 7.3 2.8 9.9 2.8 8.6 § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 4 UNIT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns ns SN54BCT125A, SN74BCT125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS032F – SEPTEMBER 1988 – REVISED MARCH 2003 PARAMETER MEASUREMENT INFORMATION 7 V (tPZL, tPLZ, O.C.) S1 Open (all others) From Output Under Test Test Point CL (see Note A) R1 From Output Under Test R1 Test Point CL (see Note A) R2 LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS RL = R1 = R2 LOAD CIRCUIT FOR 3-STATE AND OPEN-COLLECTOR OUTPUTS High-Level Pulse (see Note B) 3V Timing Input (see Note B) 3V 1.5 V 1.5 V 0V 1.5 V tw 0V Data Input (see Note B) 3V th tsu Low-Level Pulse 3V 1.5 V 1.5 V 0V 1.5 V 1.5 V VOLTAGE WAVEFORMS PULSE DURATION 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 3V Input (see Note B) 1.5 V 1.5 V 0V tPLH In-Phase Output (see Note D) VOH 1.5 V 1.5 V VOL VOH 1.5 V 1.5 V 0V tPLZ 1.5 V Waveform 1 (see Notes C and D) 3.5 V VOL tPHZ tPLH 1.5 V 1.5 V tPZL tPHL tPHL Out-of-Phase Output (see Note D) Output Control (low-level enable) 0.3 V tPZH Waveform 2 (see Notes C and D) VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (see Note D) VOH 1.5 V 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, tr = tf ≤ 2.5 ns, duty cycle = 50%. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. E. When measuring propagation delay times of 3-state outputs, switch S1 is open. F. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 5962-9093701M2A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC 5962-9093701MCA ACTIVE CDIP J 14 1 TBD Call TI Level-NC-NC-NC 5962-9093701MDA ACTIVE CFP W 14 1 TBD Call TI Level-NC-NC-NC SN54BCT125AJ ACTIVE CDIP J 14 1 TBD Call TI Level-NC-NC-NC SN74BCT125AD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74BCT125ADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74BCT125ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74BCT125ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74BCT125AN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74BCT125ANE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74BCT125ANSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74BCT125ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SNJ54BCT125AFK ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC SNJ54BCT125AJ ACTIVE CDIP J 14 1 TBD Call TI Level-NC-NC-NC SNJ54BCT125AW ACTIVE CFP W 14 1 TBD Call TI Level-NC-NC-NC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. 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