TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 • • • • 12-Bit ADC With 4-Multiplexed Inputs Wide Supply Voltage Range 2.6 V to 5.5 V Low Power Consumption Typical at VDD = 3 V – 0.1 µA in OFF Mode – 4 µA in DONE Mode – 80 µA in ACTIVE Mode Without A/D Conversions – 300 µA in ACTIVE Mode With A/D Conversions Onboard 4-MUX 56-Segment LCD Driver • Onboard Ratiometric Current Source Programmable From 0.15 mA × (SVDD/V) to 2.4 mA × (SVDD/V) Two Independent Crystal Controlled Timers (32.768 kHz) Internal MOS Oscillator Serves as System Clock Programmable Microcontroller Simple and Easy Programming With SMPL Macro Language • • • • description The TSS400 Standard ( TSS400-S1) sensor signal processor is an ultra-low power, intelligent, 12-bit A / D converter ( ADC) that has been preprogrammed with the Sensor Macro Programming Language ( SMPL) interpreter. This language allows fast, easy, and economical customization of the TSS400-S1 to a wide range of sensor signal processing applications. The application specific programs that customize the operation of the TSS400-S1 are stored in external EEPROMs along with any additional data required by the application. The main components of the TSS400-S1 are a four-input multiplexed 12-bit ADC, a programmable constant current source, an LCD driver capable of driving 56 segments using a 4-MUX drive scheme, two crystal controlled independent timers, an on-board RAM, six output-only pins ( R1 to R6 ), a 4-bit programmable I / O port ( K1, K2, K4, K8 ), and I2C serial EEPROM communications. Operation of the TSS400-S1 is very adaptive because it is controlled by a SMPL language program. These programs can be stored in an external EEPROM (standalone mode) or stored in a host computer ( slave mode ). The SMPL language is a powerful, easy to learn, and easy to use macro language. Some of the SMPL language features are single-command EEPROM read and EEPROM write operations, three levels of subroutines, a single-command A / D conversion instruction that specifies the number of conversions and the type of conversion (either compensated or noncompensated) to be made, and two reduced power consumption modes ( DONE and OFF ). SVDD K1 VDD INITN KC VSS COM4 COM3 S1 S2 S3 FN PACKAGE (TOP VIEW) 0°C to 70°C TSS400CFN-S1 – 40°C to 125°C TSS400AFN-S1 SMPL is a trademark of Texas Instruments Incorporated. 6 5 4 7 3 2 1 44 43 42 41 40 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 29 17 18 19 20 21 22 23 24 25 26 27 28 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 R0 R1 I/O R2 R3 R4 R5 R6 R7 COM2 COM1 AVAILABLE OPTIONS PACKAGE TA 44-PIN PLCC (FN) Ri A4 K2 A3 A2 K4 A1 K8 AGND TOSCOUT TOSCIN Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 Terminal Functions SIGNAL NAME PIN NUMBER I/O I DESCRIPTION A1, A2, A3, A4 13, 11, 10, 8 Analog input for the ADC AGND 15 COM1, COM2, COM3, COM4 28, 27, 43, 44 I/O 20 I/O INITN 3 I K1, K2, K4, K8 5, 9, 12, 14 KC R0† 2 18 O EEPROM clock. Controls the EEPROM clock. R1, R2, R3, R4, R5, R6 R7† 19, 21, 22, 23, 24, 25 O Digital outputs 26 O Controls EEPROM power switch Ri 7 S1 — S14 42 — 29 SVDD 6 TOSCIN 17 I Oscillator input. Input connection for crystal oscillator ( 32.768 kHz ). TOSCOUT 16 O Oscillator output. Output connection for crystal oscillator ( 32.768 kHz ). VDD VSS 4 Power supply 1 Ground Analog ground O I/O LCD commons Communication input / output Initialization. INITN is normally tied to VDD and held high. If INITN is held low for more than 10 µs, the TSS400-S1 will begin a warm start. 4-bit programmable input / output port Test. This pin must be tied to VSS during normal operation. Current source ( programming resistor connection ) O LCD segments Switchable VDD † Not directly accessible by the user’s program. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 functional block diagram INITN TOSCIN KC System Control TOSCOUT Oscillator Clock Timers VDD VSS System Bus Sensor Supply Data Memory (RAM) ALU Working Registers SVDD Ri A1 Analog -toDigital Converter FLAC REGB A2 A3 A4 AGND Storage Registers STO0 STO1 S1 STO2 S2 . . . S13 STO3 STO4 STO5 Output PLA LCD Driver S14 COM1 Counters COM2 COM3 FLAG Registers COM4 Status Bits ROM Interpreter External EEPROM/ Host Processor Interface Timer Buffers PC RO R7 I/O System Bus R Output Latch R1 R2 R3 R4 R5 R6 K-Port Latch/Buffer K1 K2 K4 K8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 description (continued) The TSS400-S1 is designed to meet a wide variety of sensor systems applications including those that require short time-to-market and rapid and / or frequent programming updates. Since the TSS400-S1 does not require mask programming, it can be purchased in any quantity. Some typical applications include: • • • • measurements of temperature, pressure, acceleration, gas content, magnetic field, relative humidity, speed, direction, and volume measurements requiring calculation, control, and / or warning functions measurements where temperature compensation is required for accuracy measurements where software calibration and linearization is desirable These sensor systems can be found in many types of applications including home appliances, industrial control subsystems, HVAC systems and instrumentation, portable instrumentation, consumer products, automotive products, or anywhere precise ( 12-bit ), ultra-low power ( 12 µA – 15 µA, TYP ), intelligent A / D conversion is essential. The TSS400-S1 is available in two temperature ranges. The TSS400CFN-S1 is characterized for operation from 0°C to 70°C. The TSS400AFN-S1 is characterized for operation from – 40°C to 125°C. initialization and power up Initialization is started by hardware in two ways: • • Power up: The voltage VDD is switched on ( cold start ). The CPU starts to work at PC 000 after the internal oscillator has started operation. This may take from 1 to 6 seconds. INITN pin: If the INITN pin is held low (switched to ground) for more than 10 µs ( when this occurs during program execution it is called a warm start ). The CPU starts operation at PC 000 when the INITN pin is released to VDD potential. Table 1 lists the TSS400-S1 register contents after a power up or an INITN pin initialization. Table 1. Register Contents REGISTER POWER UP ( COLD START ) INITN PIN ( WARM START ) 000 000 Status bits POS, NEG, and ZERO RAM contents † undefined unchanged reset to 0 unchanged Digit Latches ( DLn ) reset to 0 reset to 0 K-Line’s Latches Contents undefined unchanged 0 unchanged switched off switched off undefined unchanged level 0 level 0 Program Counter ( PC ) Timers ADC Voltage SVDD LCD Segment Latches Subroutine Stack † Despite the RAM remaining unchanged during a warm start, the memory addressed when INITN is activated may be destroyed by a write cycle. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 initialization and power up (continued) If the TSS400-S1 system is battery powered and contains calibration factors or other important data in RAM, it is advisable to distinguish between cold start and warm start. The reason is the possibility of initializations caused by electromagnetic inductance ( EMI). If such an erroneous initialization is not tested for legality, EMI influence could destroy the RAM contents by clearing the RAM with the initialization software routine. The TSS400-S1 compares two reserved RAM nibbles to see if they contain A516 after each initialization: • • If the RAM nibbles contain the expected information ( A516 ), initialization continues at PC 000. The RAM contents are not changed. This means that a spurious signal caused the initialization ( warm start ). If the RAM nibbles differ from A516, the RAM is cleared and the program continues at PC 000. This means that the TSS400-S1 supply voltage was switched on ( cold start ). The short timer and the long timer are not stopped by a warm start. This means that they remain active and must be stopped by a STPTIMx instruction, if necessary. operating conditions The TSS400-S1 has four different modes of operation: OFF, DONE, ACTIVE without A / D conversion, and ACTIVE with A / D conversion. The OFF mode conserves the most power. In this mode, only the RAM and the outputs ( I / O, R outputs, and K lines ) are maintained. The TSS400-S1 enters OFF mode with a software command and is awakened via the K lines or by initialization. Table 2 lists the conditions needed for the K lines to awaken the processor. Table 2. K-Line Wake-Up Conditions DL15 K8 0 0 1 0 1 K4 .AND. 0 1 .OR. 1 .AND. 0 .OR. K2 .AND. 0 1 .OR. 0 .AND. 1 .OR. K1 CONDITION .AND. 0 condition before wake up 1 .OR. 1 condition to wake up processor 0 .AND. 0 condition before wake up 1 .OR. 1 condition to wake up processor The DONE mode is also a low-power mode. In the DONE mode, the RAM, the outputs, and the display are maintained and the timekeeping circuits remain active. The device enters DONE mode with a software command and is awakened via the K lines, initialization, or with a wake up by internal timers. When the TSS400-S1 is executing instructions, it is in the ACTIVE mode. This mode can be broken into two separate states; with A / D conversion and without A / D conversion. All portions of the TSS400-S1 are fully operational in the ACTIVE with A / D conversion mode, only the A / D conversion circuitry is powered down in the ACTIVE without A / D conversion mode. See Figure 1 for a state diagram of the TSS400-S1 operational modes. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 Power up or INIT DONE Mode Timer Active Outputs/RAM/ LCD Stable 4-µA Power Consumption Typical Command: DONE INIT or EXT. HW Wake up, Timer Interrupt ACTIVE Mode Without ADC Active 80-µA Power Consumption Typical Command: OFF INIT or EXT. HW Wake up ACTIVE Mode With ADC Active 300-µA Power Consumption Typical Figure 1. State Diagram for TSS400-S1 Operational Modes 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 OFF Mode Outputs/RAM Stable 0.1-µA Power Consumption Typical TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 analog-to-digital converter (ADC) (see Figure 2) The TSS400-S1 offers a 12-bit ratiometric successive approximation ADC. Sensors are interfaced to this converter via the 4-multiplexed ( 4-MUX) analog inputs ( A1 – A4 ). The analog conversion operation is executed with the MEASR instruction. The SMPL interpreter automatically switches the internal digit latches DL9, DL10, and DL11 such that the ADC is connected to the analog input line specified by the MEASR operand. Table 3 lists the instructions required to access all four analog inputs. Table 3. Instructions Required to Access Analog Inputs INSTRUCTION OPERAND DL9 DL10 DL11 MEASR 0 0 1 0 Connect A1 to the ADC ACTION MEASR 1 0 0 0 Connect A2 to the ADC MEASR 2 0 1 1 Connect A3 to the ADC MEASR 3 0 0 1 Connect A4 to the ADC CHKBATT X 1 X X Check current supply voltage against value in FLAC ADJBATT X 1 X X Set minimum supply voltage point The interpreter automatically switches on the switched-sensor supply voltage ( SVDD ) just prior to making the A/ D conversion and switches it off immediately after the conversion is complete. The MEASR instruction is followed by a BYTE instruction. The operand of the BYTE instruction specifies the number of conversions to be made and whether the conversions are to be compensated or noncompensated. A noncompensated measurement is a single A / D conversion. A compensated measurement is defined as a measurement where two conversions are made, one conversion with the ADC comparator connected normally and the other conversion with the comparator inputs reversed. The two results are added together so any comparator offsets cancel. The interpreter automatically takes care of all required switching to perform the specified type of conversion. Absolute measurements are possible if SVDD is held constant. This requires a stable VDD during the conversion and constant loading of SVDD. The ADC measures the ratio of the input voltage at the analog input ( VDD ) to the switched-sensor supply voltage ( SVDD ) and not absolute voltages. This ensures that the measurement of the sensors is independent of the supply voltage. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 VDD S Set SVDD Reset SVDD Clear R CLR See Note A SVDD SVDD Ri EN A1 A2 DL13 1 DL11 2 EN DL10 See Note A DL9 See Note A Analog Multiplexer A3 S R A4 G1 1 MUX 1 + – SVDD Vref Digital-Analog Converter FLAC Register 12 RAM AGND AGND TSS400 NOTE A: These signals are automatically controlled by the interpreter during A / D conversion. Figure 2. ADC Functional Block Diagram measurement range and conversion formulas The analog input range is the same for all four analog outputs, A1 to A4. The nominal properties of the ADC range and the equations associated with them are listed below: VI (A B N) SV DD + ) where VI = unknown analog input voltage A = converter count for VI = 0 = 0.1012113203 for the TSS400-S1 B = delta in µV/SVDD for a 1-bit difference in conversion result = 0.000096090233 for the TSS400-S1 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 N = A / D conversion result for a single measurement SVDD = Switched sensor supply voltage For the TSS400-S1, the analog input voltage is: VI (0.1012113203 0.000096090233 N) SV DD + ) For multiple measurements, the VI equation becomes: B N ) VI (A SV DD M + ) + ( 0.1012113203 SV DD ) ) ( 0.000096090233 N SVDD ) M where M = the number of measurements taken Since a conversion result of 0 is used to indicate an under-range input and FFF16 is used to indicate an over-range input, the allowable range for N ( in a single measurement ) is: 116 ≤ N ≤ FFF16 or in decimal format: 1 ≤ N ≤ 4094 The minimum measurable analog input voltage to SVDD ratio is: VI V Imin when N 1 SV DD + + + ( 0.1012113203 ) 0.00009609023 ) + SV DD SV DD 0.101309 The maximum measurable analog input voltage to SVDD ratio is: VI V Imax when N 4094 SV DD + + + (0.1012113203 ) 0.000096090233 + 4094) SV DD SV DD 0.494605 So the allowable analog input voltage range for VI is: 0.101307 × SVDD ≤ VI ≤ 0.494605 × SVDD If the input voltage is below the lower limit, VImin, the value 00016 is returned. If the input voltage is above the upper limit, VImax, the value FFF16 is returned. The NEG status bit is set in both cases. The ZERO status bit is set if 00016 is returned. battery check Since the TSS400-S1 is ideal for battery applications, an internal supply voltage check is available. This operation is executed by the instructions ADJBATT and CHKBATT. ADJBATT measures the internal reference voltage and puts the results in the FLAC register. By setting the supply voltage at a minimum acceptable level and executing the ADJBATT instruction, a representative value will be placed in the FLAC register. Saving this number in a storage register or EEPROM location will enable it to be recalled for use by the CHKBATT instruction when the current supply voltage needs to be checked against the preset acceptable minimum. To perform these operations, an internal stable reference is connected to the input of the ADC and a measurement is made. Due to the ratiometric nature of the conversion, the measured value is an indication of the TSS400-S1 supply voltage. The ADJBATT instruction performs this operation and stores the result in the FLAC register. The CHKBATT instruction performs the same operation, but compares the resulting measurement to the number in the FLAC register and sets the positive ( POS) and negative ( NEG) status bits according to the result. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 programmable current source A switchable ratiometric ( to SVDD ) current source is available for supplying a fixed amount of current to the analog sensors. When turned on, the current source sends a constant current out of the addressed analog input ( An). The voltage generated by the external sensor is measured with the same An input. The voltage used for A/ D conversions and the reference voltage ( Vref ) used to set the current of the current source are both proportional to SVDD and have a fixed ratio to each other. This ensures optimum tracking. The current source is activated by digit latch DL13. When DL13 is set to 1 and SVDD is on, the current source is on. When DL13 is set to 0, the current source is off. Figure 3 shows a diagram of the programmable current source. The current I is programmed by an external resistor Rext, which is connected between SVDD and Ri. This current is given by the following equation: I An + VRRext ext Vrext is approximately 0.24 × SVDD The programmable current range that the current source can supply to the ADC input is: 0.15 mA to 2.4 mA × ( SVDD /V) VI + IAn with R I VI + VRext RI + Sensor Resistance RI R ext SVDD Rext VRext Ri VDD – + An An Selected ENABLE (I on An) Sensor AGND AGND Figure 3. Programmable Current Source Diagram 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 timers There are two independent crystal-controlled timers available on the TSS400-S1. The required crystal is a 32.768 kHz crystal. This allows very accurate time measurements and clock functions to be performed. These timers function at 1 Hz and 16 Hz and can be used as a wake-up signal from the DONE mode of operation in addition to the other timing functions. The crystal is also used to control the LCD driver circuitry. counters Two decimal counters, Counter 1 and Counter 2, are available for use on the TSS400-S1. The individual counters range from 0 to 99 or they can be cascaded together for a range of 0 to 9999. Counter 1 is the least significant part of the combined counter. After the counters are incremented or decremented, the ZERO status bit is set when the counter reaches zero or reset if counter is not zero. EEPROM addressing The TSS400-S1 interpreter reads each SMPL instruction from the external EEPROM using the I2C serial communications, interprets the opcode, and performs the required operation. A TSS400-S1 complete system requires two devices ( plus sensors ) for a minimum configuration ( the TSS400-S1 and an EEPROM ). The TSS400-S1 interpreter uses the 11-bit wide program counter (PC) to address up to 2K-bytes of EEPROM ( the maximum length for a user’s program ). Table 4 lists the hardware addresses of the four EEPROMs as defined by the logic levels of pins A1 and A2. Table 4. EEPROM Hardware Addresses EEPROM PINS A2 A1 ADDRESS SPACE 0 0 0 1 0 — 511 ( 016 — 1FF16 ) 512 — 1023 ( 20016 — 3FF16 ) 1 0 10242 — 1535 ( 40016 — 5FF16 ) 1 1 15362 — 2047 ( 60016 — 7FF16 ) Figure 4 shows the TSS400-S1, two EEPROMs, a 32.768-kHz crystal, and a 7-digit LCD connected in a typical system configuration. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 (PNP + 3 resistors) 0V A0 A1 0V 0V A2 VSS 0V VCC EEPROM ( see Note A ) SCL SDA 26 R7 COM1 – COM4 18 R0 20 SEL1 – SEL14 I/O SVDD Ri A1 A2 A3 0V 5V A0 A1 0V A2 VSS 0V A4 GND VCC EEPROM ( see Note A ) SCL 27,29,43,44 7-Digit 4-MUX LCD 29 – 44 6 7 13 11 10 A/D Converter 8 15 VSS SDA R1 R2 R3 VDD 1024 x 8 bits are shown Up to 2048 x 8 bits are possible (1 to 4 EEPROMs) 3 2 4 0V 5V 1 0V 17 32.768-kHz Crystal 16 R4 R5 INITN KC VDD VSS R6 K1 K2 K4 TOSCIN TOSCOUT K8 19 21 22 23 24 R Outputs 25 5 9 12 K Lines 14 NOTE A: The EEPROM shown is a Xicor X24( L )C04. Other manufacturers of I2C EEPROMs include Thompson CFS and Phillips / Signetics. Figure 4. Typical System Configuration RAM usage The TSS400-S1 RAM is organized into several registers. Some of these registers are used for system purposes and some are available to the user. These available registers and their usages are described in the following sections. FLAC register The FLAC register is the main working register of the TSS400-S1. It consists of 8 nibbles for the number, 1 nibble for the sign, and two flags that are used internally by arithmetic routines. The sign bit is set to zero for positive numbers and one for negative numbers. The following diagram shows the format of the FLAC register: 10E7 MSD 10E6 10E5 10E4 10E3 10E2 10E1 The FLAC register is used for: • • • • • • 12 receiving the results of an A / D conversion storing the results of all arithmetic and logic operations holding the first operand for arithmetic and logic operations containing the result of a hexadecimal to decimal conversion holding the information for transfer to the EEPROM holding the information to be displayed on the LCD POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10E0 LSD Sign and Flags Sign TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 REGB register The REGB register is the second working register. It consists of 8 nibbles for the number and 1 nibble for the sign. The format of the REGB register is the same as the FLAC register. The REGB register is used for: • • • holding the second operand for arithmetic and logic operations holding the constants read from the EEPROM holding the contents after transfers from the counters storage registers The TSS400-S1 has six general-purpose storage registers. These storage registers have the same format as the FLAC register, each with 8 nibbles for the number and 1 nibble for the sign. These storage registers are addressable by using the names STO0 to STO5. Use of the STO0 register is restricted since it is also used by the device during multiplication, division, and hexadecimal-to-decimal conversions. After multiplication and hexadecimal-to-decimal conversion operations, the contents of STO0 are set to 0 and after a division STO0 contains the remainder of the operation. This remainder can be used in conversions ( e.g., minutes to hours ). flag registers Two general-purpose flag register groups, each with 16 flags, have been set aside. They are named Group 1 and Group 2. The selection of the groups is made with the SMPL instructions SELGRP1 and SELGRP2. The group selected is in use until the other group is selected. Each of the 16 flags in each group may be set, reset, and tested. The contents of the flags can then be used to control the program flow, define the action of jumps, indicate errors in hardware function, and any other user defined purpose. The use of some of the flags is restricted since their operation has been predefined. Table 5 lists the assigned use of each flag. Table 5. Flag Assignment GROUP 1 FLAGS FLAG DEFINITION 0 Arbitrary 1 2 FLAG GROUP 2 FLAGS DEFINITION FLAG DEFINITION 8 Arbitrary 0 Arbitrary Seg. H1 information 9 Arbitrary 1 Seg. H2 information 10 Long Timer 2 3 Seg. H3 information 11 Short Timer 4 Seg. H4 information 12 5 Seg. H5 information 6 7 FLAG DEFINITION 8 Arbitrary Arbitrary 9 Arbitrary Arbitrary 10 Arbitrary 3 Arbitrary 11 Arbitrary K1 Buffer 4 Arbitrary 12 Arbitrary 13 K2 Buffer 5 Arbitrary 13 Arbitrary Seg. H6 information 14 K4 Buffer 6 Arbitrary 14 Arbitrary Seg. H7 information 15 K8 Buffer 7 Arbitrary 15 Arbitrary R outputs and digit latches Outputs R1 through R6 are available as general-purpose outputs. They can be used for scanning keyboards or switches, for controlling relays, lamps, LCDs, etc., or for digital communications using buffers, multiplexers, etc. as required by the designer. The R0 and R7 outputs cannot be addressed by the software. They are used by the interpreter when the EEPROM reads or writes are performed. R0 performs as the clock connection and R7 switches the supply voltage to the EEPROM as required to conserve system power. The TSS400-S1 contains 14 one-bit digit latches ( DL0 through DL13 ) that ( except for DL0 and DL7 ) can be set and reset independently with software. These digit latches can be separated into two distinct groups, those with external outputs ( DL0 through DL7 ) and those without external outputs ( DL8 through DL13 ). The digit latches without external outputs ( DL8 through DL13 ) each control a unique hardware function. Table 6 gives the digit-latch names and the hardware functions they control. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 Table 6. Digit Latch Names and Hardware Functions DIGIT LATCH HARDWARE FUNCTION DL0 Not user addressable (R0), clock for EEPROM DL1 — DL6 6 R outputs (R1–R6) for general use DL7 Not user addressable (R7), power switch for EEPROM DL8 DL9 — DL11† DL12 DL13 0 Sets K port to input 1 Sets K port to output Addressed Analog Input Connected to the ADC DL9 DL10 DL11 0 0 0 A1 0 1 0 A2 0 0 1 A3 0 1 1 A4 1 X X Battery check functions 0 1-Hz timer input into the ALU for timer instructions 1 16-Hz timer input into the ALU for timer instructions 0 Constant current source of the ADC off 1 Constant current source of the ADC on, if SVDD is on † It is not normally necessary to change these digit latches with software since the interpreter controls them automatically. K Port The K port is a 4-bit programmable I / O port with individual lines labeled K1, K2, K4, and K8. The direction of data flow through the K lines is controlled by digit latch DL8. Data to be output through the K lines is first stored in the 4-bit K-lines latch. The K-port output structure is open source. For data input, the K lines are read via Schmitt triggers into the ALU. If the TSS400-S1 has been placed in either the OFF or DONE mode, it is possible to use the K lines to generate a wake-up signal. status logic The status logic consists of 3 bits that are modified after the execution of specific instructions. The status bits are checked by conditional jumps that are executed or not executed depending on the state of the tested status bit. Please note that not every instruction rewrites the status bits. If an instruction does not affect the status bits, the status of the last instruction to rewrite the status bits is preserved. The following diagram shows the 3 bits making up the status logic. POS NEG ZERO POS bit The POS bit is set after an arithmetic instruction if the result of the operation has a positive sign. If the result is negative, the POS bit is reset. Other instructions will set the POS bit if no error occurred making it possible to use the POS bit status as an error indicator. If the A / D measurement is within range, the POS bit is set. NEG bit The NEG bit is set after an arithmetic instruction if the result of the operation has a negative sign. If the result is positive, the NEG bit is reset. Other instructions will set the NEG bit if an error occurred making it possible to use the NEG bit status as an error indicator. If the A / D measurement is out of range, the NEG bit is set. ZERO bit The ZERO bit is set to one if the result of the last instruction is zero or if a comparison results in equality. If the result is not zero or the comparison is not equal, the ZERO bit is cleared. If the A / D measurement is under range, ZERO bit is set. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 LCD driver The TSS400-S1 contains LCD-driver circuitry that is designed to get the best results for a wide range of applications. From a software point of view, the LCD 4-MUX 56-segment driver looks very simple: No timing problems exist with multiplexing for getting a quiet, stable display. The LCD-driver hardware outputs display information automatically without any software burden during the ACTIVE and DONE modes of operation. Software has only to decide which segment information is to be displayed and in which digit to display it. NOTE: LCDs are available for prototype development. Contact the nearest TI sales office for more information. digit addressing The following diagram shows the TSS400-S1 display configuration and accompanying FLAC nibbles. FLAC NIBBLE 10E7 10E6 10E5 10E4 10E3 10E2 10E1 10E0 SELECTS — S1/S2 S3/S4 S5/S6 S7/S8 S9/S10 S11/S12 S13/S14 DIGIT n — 1 2 3 4 5 6 7 COM1 (Even Select ) A COM2 (Odd Select ) F COM2 (Even Select ) C COM1 (Odd Select ) G COM4 (Even Select ) COM4 (Odd Select ) B E D H COM3 (Odd Select ) COM3 (Even Select ) The FLAC’s MSD ( 10E7) cannot be displayed because of the 7-digit configuration of the display driver. If it is necessary to display the MSD, a shift right ( SHIFTR) with decimal correction of the FLAC contents will have to be done. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 segment addressing The OPLA terms definition is based on the following hardware configuration. COMMON SELECT LINES 1 2 3 4 ODD SELECT S1 S3 S5 S7 S9 S11 S13 C F H E EVEN SELECT S2 S4 S6 S8 S10 S12 S14 A B D G Caution: The shown common / select definition can not be modified and any display chosen to be used with the TSS400-S1 must conform to it. The chosen common / select configuration is designed to be fail safe. This means that no valid numbers or characters are displayed when a segment or common signal failure occurs. Instead meaningless segment combinations are displayed that cannot be mistaken as valid data. The TSS400-S1 LCD driver contains a gate-level output PLA ( OPLA) that is of a 64 × 7 bit configuration. The 7 bits represent the segment information A through G for 64 predefined combinations ( the H segment is independent from the OPLA and is given with the display instructions ). Each of the predefined characters can be used with the display command. Table 7 gives the segments displayed and the character for each. Table 7. Segment Display and Character CHARACTER NUMBER 16 SEGMENTS CHARACTER 0 ABCDEF 0 or O 1 BC 1 or | 2 ABDEG 2 3 ABCDG 3 4 BCFG 5 ACDFG 6 ACDEFG 7 ABC 8 ABCDEFG 4 5 or S 6 7 8 or B 9 ABCDFG 9 10 ABCEFG A or R 11 CDEFG 12 ADEF 13 BCDEG d 14 ADEFG E 15 AEFG 16 None 17 BCD J 18 DEF L 19 ABEFG P 20 BCDEF U 21 DEG c 22 CEFG h 23 DE l 24 CEG n 25 CDEG o 26 EG r 27 DEFG t 28 CDE v POST OFFICE BOX 655303 DISPLAYED SEGMENTS b C or [ F Blank • DALLAS, TEXAS 75265 TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 Table 7. Segment Display and Character (Continued) CHARACTER NUMBER SEGMENTS CHARACTER 29 BCDFG Y 30 BCEFG H 31 BCG –1 32 None Blank 33 A 34 F 35 AF 36 B 37 AB 38 BF 39 ABF 40 G 41 AG 42 FG 43 AFG 44 BG 45 ABG 46 BFG 47 ABFG 48 E 49 AE 50 EF 51 AEF 52 BE 53 ABE 54 BEF 55 ABEF 56 EG 57 AEG 58 EFG 59 AEFG 60 C 61 D 62 ABCD ] 63 ABCDE J POST OFFICE BOX 655303 DISPLAYED SEGMENTS Minus Sign Degree F • DALLAS, TEXAS 75265 17 TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 sensor macro programming language (SMPL) The TSS400-S1 features a processor that is programmed with an easy-to-use macro language, SMPL. The internal ROM is pre-programmed with optimized calibration, display, A / D conversion routines, the SMPL macro interpreter, and EEPROM communications protocol. The TSS400-S1 SMPL language is an optimized 75-instruction language that is much easier to use than assembly language. Each SMPL instruction is equivalent, on average, to six or seven assembly language instructions. This greatly reduces the amount of memory space required to store a given program and eases programming tasks. SMPL interpreter instruction coding format The following rules should be followed in writing a program: • • • • Label fields are a maximum of eight alphanumeric characters starting with an alphabetic character. The label field must begin in column one. The mnemonic is to the right of a label, separated by at least one blank space. If no label is used, the mnemonic begins after the first column ( second column or further right ). The operand is to the right of the mnemonic and separated by at least one blank. A comment is to the right of the operand and separated by at least one blank. If a comment occupies a separate line, it must begin with an asterisk ( *) in column one. For legibility, it is recommended that fields begin in the following columns: • • • • • label fields must begin in column 1 mnemonic should begin in column 11 operands should begin in column 21 comments to an instruction should begin in column 31 full line comments must begin with an asterisk ( *) in column 1 LABEL† MNEMONIC OPERAND COMMENT * column 1 column 11 column 21 column 31 † Labels are 8 characters, max, and must start in column 1. * Asterisk in column 1 reserves the entire line for a comment. Table 8 lists the SMPL language programming instructions in each of the following major categories: • • • • • • 18 Register-to-register instructions Arithmetic instructions Arithmetic compare instructions Bit manipulation instructions Counter instructions Display instructions POST OFFICE BOX 655303 • • • • • • Miscellaneous instructions Constant transfer instructions Timer instructions Input/ output instructions Program flow control instructions A/ D conversion instructions • DALLAS, TEXAS 75265 TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 Table 8. SMPL Programming Instructions FUNCTION GROUP Register-to-Register R i t t R i t Transfer SMPL INSTRUCTION n Move FLAC to storage register n MOVSTOFL n Move storage register n to FLAC MOVRBSTO n Move REGB to storage register n MOVSTORB n Move storage register n to REGB EXCHRBFL Exchange REGB and FLAC registers MOVFLRB Move FLAC register to REGB register MOVRBFL Arithmetic Arithmetic Compare Bit Manipulation Counter Move REGB register to FLAC register MOVFLPRM label Move FLAC to EEPROM starting at address label MOVPRMRB label Move EEPROM contents starting at address label to REGB ADD Add REGB to FLAC decimally SUB Subtract REGB from FLAC decimally MPY Multiply FLAC and REGB decimally DIV Divide FLAC by REGB decimally ADDH Add REGB to FLAC hexadecimally SUBH Subtract REGB from FLAC hexadecimally HEXDEC Hexadecimal to decimal conversion ROUND n Round FLAC n times (0<n<5) SHIFTR n Shift right FLAC n times (0<n<3) SHIFTL n Shift left FLAC n times (0<n<3) CMPFLRB Compare FLAC and REGB then set status flags TSTRB Test contents of REGB then set status flags SBIT n Set flag bit n (0 ≤ n<16) RBIT n Reset flag bit n (0 ≤ n<16) TBIT n Test flag bit (0 ≤ n<16) SELGRP n Select flag bits group n (0<n<3) OR Logical OR FLAC and REGB with result to FLAC AND Logical AND FLAC and REGB with result to FLAC DECCNT n Decrement counter n decimally INCCNT n Increment counter n decimally DECDBL Decrement double counter decimally INCDBL LDCNT n Increment double counter decimally >NN MOVCNT n DISPLDG n Miscellaneous Move combined counters to REGB >NN DISPLCLR DISPLFL Load counter n decimally with constant >NN Move counter n to REGB MOVDBL Display Dis lay DESCRIPTION MOVFLSTO Display information of operand NN in digit n Clear display >MN Display FLAC from digit M to digit N and append (M–N+1) bytes containing information for each digit DONE Enter DONE mode OFF Enter OFF mode NOP SLV No operation >NN Host control instruction POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 Table 8. SMPL Programming Instructions (Continued) FUNCTION GROUP Constant Transfer SMPL INSTRUCTION LDFLPOS n Load FLAC with a positive constant (BCD format) contained in the n following bytes (n = 0 : 4 Bytes) LDFLNEG n Load FLAC with a negative constant (BCD format) contained in the n following bytes (n = 0 : 4 Bytes) LDRBPOS n Load REGB with a positive constant (BCD format) contained in the n following bytes (n = 0 : 4 Bytes) LDRBNEG n Load REGB with a negative constant (BCD format) contained in the n following bytes (n = 0 : 4 Bytes) CLRFL Clear FLAC register CLRRB Timer Input / Output Clear REGB LDTIML NNN Load long timer with constant NNN LDTIMS NNN Load short timer with constant NNN ACTTIM Actualize timers STPTIML Stop long timer STPTIMS Stop short timer SETR n Set output Rn (DLn) RSTR n Reset output Rn (DLn) TSTKEY >NN Test keyboard like described by operand KINTIM Actualize K input and timers KIN Read K inputs to FLAC (LSD) and FLAG 12 thru 15 FLKOUT Program Flow Control 20 Output LSD of FLAC to K lines KOUT n Output constant n to K lines JMP label Jump to label unconditionally JZ label Jump to label if zero (STATUS BIT ZERO = 1) JEQ label Jump to label if equal (STATUS BIT ZERO = 1) JNZ label Jump to label if not zero (STATUS BIT ZERO = 0) JNE label Jump to label if not equal (STATUS BIT ZERO = 0) JP label Jump to label if positive (STATUS BIT POS = 1) JN label Jump to label if negative (STATUS BIT NEG = 1) CALL label Call subroutine label RETN Return from subroutine SVDDON Set converter supply voltage SVDDOFF Reset converter supply voltage MEASR A / D Conversion C i DESCRIPTION a Measure addressed A / D input a+1 and following byte contains number of conversions and mode ADJBATT Measure battery voltage and put result in FLAC CHKBATT Check battery voltage ADJCOMP Measure A / D input and put result in FLAC CHKCOMP Compare A / D input with value in FLAC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VDD ( see Note 1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS – 0.3 V to VDD+0.3 V Diode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 2 mA Operating free-air temperature range, TA: TSS400CFN-S1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TSS400AFN-S1 . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50°C to 150°C NOTE 1: The voltage value is measured with respect to VSS. recommended operating conditions MIN NOM MAX Supply voltage, VDD 2.6 5.5 Supply voltage, VSS 0 0 Timer frequency (XTAL) 32.768 Operating O erating free-air tem temperature erature, TA UNIT V V kHz TSS400CFN-S1 0 70 °C TSS400AFN-S1 – 40 125 °C TYP MAX UNIT 300 500 800 1100 electrical characteristics, TA = 0°C to 70°C total device supply current PARAMETER IDD(ACTIVE) ACTIVE mode TEST CONDITIONS MIN With A/D† VDD = 3 V VDD = 5 V Without A/D† VDD = 3 V VDD = 5 V 80 140 400 500 VDD = 3 V 4 8 VDD = 5 V VDD = 3 V 10 18 0.1 1 IDD(DONE) DONE mode Standby† IDD(OFF) OFF mode Halt† VDD = 5 V 0.1 1 † Current values are for input levels in the range of 0 to 0.3 V for VKL, VIOL; and VDD – 0.3 V for VKH, VIOH ( all outputs open ). µA µA µA µA K and I/O inputs (schmitt trigger) PARAMETER VT T+ VT T– II MIN MAX Positive going threshold voltage Positive-going VDD = 3 V VDD = 5 V 1.2 2.0 2.2 3.8 Negative going threshold voltage Negative-going VDD = 3 V VDD = 5 V 0.8 1.5 Input In ut current TEST CONDITIONS 1.2 2.6 VDD = 3.8 V, VDD = 5.5 V, VI = 0 – 0.1 0.1 VIN = 0 – 0.1 0.1 VDD = 3.8 V, VDD = 5.5 V, VIN = VDD – 0.1 0.1 VIN = VDD – 0.1 0.1 UNIT V µA K outputs PARAMETER VOH High-level output out ut voltage TEST CONDITIONS VDD = 3 V, VDD = 5 V, POST OFFICE BOX 655303 IOH = – 0.1 mA IOH = – 0.5 mA • DALLAS, TEXAS 75265 MIN MAX UNIT VDD – 0.2 VDD – 0.6 VDD VDD V 21 TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 electrical characteristics, TA = 0°C to 70°C (continued) I/O output PARAMETER TEST CONDITIONS VOH High level output voltage High-level VDD = 3 V, VDD = 5 V, VOL output Low-level out ut voltage VDD = 3 V, VDD = 5 V, IOH = – 0.1 mA IOL= 0.5 mA IOH = – 0.75 mA IOL= 1 mA MIN MAX UNIT VDD – 0.2 VDD – 0.2 VDD VDD V VSS VSS VSS + 0.4 VSS + 0.4 V MIN MAX UNIT VDD – 0.2 VDD – 0.6 VDD VDD V R outputs PARAMETER VOH(R) ( ) VOL(R) TEST CONDITIONS High-level output voltage VDD = 3 V, VDD = 3 V, IOH = – 0.1 mA IOH = – 0.3 mA output Low-level out ut voltage VDD = 5 V, VDD = 3 V, VDD = 5 V, IOH = – 0.3 mA IOL = 0.3 mA VDD – 0.4 VSS VDD VSS + 0.4 IOL = 0.3 mA VSS VSS + 0.4 V INITN input PARAMETER II(INITN) ( ) TEST CONDITIONS Input current, INITN MIN MAX VDD = 3 V, VDD = 5 V, VI = 0 – 0.2 –1 VI = 0 – 0.5 – 2.2 VDD = 3.8 V to 5.5 V, VI = VDD – 0.1 0.1 UNIT µA SVDD output PARAMETER TEST CONDITIONS Output voltage, voltage switched VDD VDD = 2.6 V, VDD = 2.6 V, Output current, switched VDD VDD = 3.8 V to 5.5 V, MIN MAX UNIT ISVDD = 6.5 mA VDD – 0.2 VDD – 0.3 VDD VDD V SVDD off ( 0 V ) – 0.1 0.1 µA ISVDD = 2 mA LCD lines common, segment (1/4 duty cycle) PARAMETER VOH(COM) TEST CONDITIONS High level output voltage (COM1 – COM4) High-level 22 MAX UNIT VDD VDD V IOH = – 100 µA VDD – 0.4 VDD – 0.4 VDD = 3 V, IOZ = ± 10 nA (2/3) VDD – 0.04 (2/3) VDD (2/3) VDD +0.04 VDD = 5 V, IOZ = ± 10 nA (2/3) VDD – 0.04 (2/3) VDD (2/3) VDD +0.04 VDD = 3 V, IOZ = ± 10 nA (1/3) VDD – 0.04 (1/3) VDD (1/3) VDD +0.04 VDD = 5 V, IOZ = ± 10 nA (1/3) VDD – 0.04 (1/3) VDD (1/3) VDD +0.04 VDD = 3 V, VDD = 5 V, IOL = 50 µA 1/3 Hz (COM1 – COM4) Output voltage voltage, 1/3-Hz Low-level output out ut voltage (COM1 – COM4) TYP IOH = – 50 µA 2/3 Hz (COM1 – COM4) Output voltage voltage, 2/3-Hz VOL(COM) MIN VDD = 3 V, VDD = 5 V, POST OFFICE BOX 655303 IOL = 100 µA • DALLAS, TEXAS 75265 VSS VSS VSS+0.4 VSS+0.4 V V V TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 electrical characteristics, TA = 0°C to 70°C (continued) ADC current source, VRext = VSVDD – VRi (unless otherwise noted) PARAMETER TEST CONDITIONS Voltage ( across VR Rextt programming resistor )† MIN VDD = 3.5 V, IRi = 1.3 mA, TA = 25°C 0.240737 × SVDD VDD = 5 V, IRi = 1.3 mA, TA = 25°C 0.241959 × SVDD Rextt External programming g g resistor VDD = 3.5 V, VDD = 5 V, dN/dT Temperature stability VDD = 5 V, VDD = 5 V, dN / dSVDD SVDD rejection ratio VDD = 5 V, VDD = 5 V, TA = 25°C TA = 25°C VRext/Rext = 1.3 mA MAX UNIT 0.248069 × SVDD 0.244403 × SVDD 0.246847 × SVDD 0.10 1.6 0.10 1.6 V kΩ 0.03 LSB/°C 0.06 VRext/Rext = 1.3 mA TA = 25°C TA = 25°C TYP 0.244403 × SVDD –3 – 1.5 1 –6 –3 2 MIN TYP MAX UNIT ± 30 nA 0.487977 × SVDD 0.489899 × SVDD LSB/V ADC TEST CONDITIONS‡ PARAMETER IIB VIH VIL Input bias current ( all inputs )† g g input voltage g for High-level analog A / D conversion g input voltage g for Low-level analog A / D conversion VI = VSS to VDD, Current source off VDD = 3.5 V, N = EB916 0.486055 × SVDD VDD = 5 V, N = FD416 0.488649 × SVDD 0.490571 × SVDD 0.492493 × SVDD VDD = 3.5 V, N = 04616 0.106017 × SVDD 0.107939 × SVDD 0.109861 × SVDD VDD = 5 V, N = 02B16 0.103423 × SVDD 0.105345 × SVDD 0.107267 × SVDD V V † This range is available only for VDD ≥ 3.5 V. The A/D range is limited due to the offset of the comparator. The range can be larger, if the comparator offset is made smaller. ‡ N = A/D conversion result for a single measurement. See measurement range and conversion formulas. operating characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VDD = 3 V, Delta digital value ≤ 120 LSB VDD = 3 V, 120 LSB < DDV ≤ 240 LSB Linearity for all ranges Supply voltage, battery check tconv Conversion time 1 1.5 – 2.5 2.5 – 4.5 4.5 VDD = 5 V, Delta digital value ≤ 120 LSB VDD = 5 V, 120 LSB < DDV ≤ 240 LSB –1 1 – 1.5 1.5 – 2.5 2.5 – 4.5 4.5 VDD = 3 V, VDD = 5 V, Clock frequency frequency, internal MOS MAX – 1.5 00016 < conversion result > FFF16 N of ADC at VDD = 2.7 V, TA = 25°C Drift TYP –1 VDD = 3 V, 240 LSB < DDV ≤ 2600 LSB VDD = 3 V, DDV > 2600 LSB VDD = 5 V, 240 LSB < DDV ≤ 2600 LSB VDD = 5 V, DDV > 2600 LSB VDD(BC) MIN TA = 25 °C TA = 25 °C – 0.1 2.7 650 840 Single-compensated measurement VDD = 3.5 V 1.2 Single-uncompensated measurement VDD = 3.5 V 1 ADJCOMP VDD = 3.5 V 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT LSB LSB 4.8 V 0.1 V kHz ms 23 TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 APPLICATION INFORMATION Figure 5 shows all the components that are necessary to run a TSS400-S1 and the connected sensors for a temperature-calibrated pressure application. In this case, a 3-V lithium battery is used as a power supply. The pressure application could be an altimeter, a pressure gauge, or a manometer. This example uses simple uncalibrated silicon sensors. It is assumed that a simple, easy to perform software calibration routine is used to get accurate results. This temperature-compensation software calibration and the 12-bit ADC ensures a high degree of accuracy can be realized with this application. All of the analog circuitry in Figure 5 is connected to the SVDD ( switchable VDD ) terminal. By doing this, the sensor network is only powered when it is needed for A / D conversion. This is done to reduce total system power consumption. 7-Digit 4-MUX LCD SEG1–14 TOSCOUT VDD COM1-4 VDD 32.768 kHz TOSCIN 3.3 kΩ 2N2906 R7 22 kΩ VDD TSS400CFN-S1 EEPROM X24(L)C04 INTIN + Battery C2 C1 22 kΩ KC VSS AGND R0 A1 SVDD A2 K1 R1 K2 I/O A0 A1 A2 SDA VSS VCC SCL Temperature Sensor A0 A1 A2 SDA VSS VCC SCL Switches EEPROM X24(L)C04 Pressure Sensor – + 1/2 TLC1078 Figure 5. Temperature-Compensated Pressure Application 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 APPLICATION INFORMATION SDT-400 development tool The SDT-400 is an inexpensive software development tool used for development of TSS400-S1 applications. It consists of three basic parts: • • • a 5.25-inch floppy diskette that contains the TSS400-S1 software simulator program, the ASM400 SMPL macro language assembler program, and demonstration and example routine programs. the SDT-400 User’s Manual that details how to use the development system and the TSS400-S1. a hardware development board. The SDT-400 works with an IBM-compatible personal computer and supports program debug at the macro instruction level. It also provides on-screen simulation of the LCD display and most functions of the TSS400-S1. These functions ( all internal registers, inputs, outputs, and flags ) can be edited on the screen in the simulator with the keyboard. It also provides a BURN routine for downloading an application program into the EEPROMs on the hardware development board. The hardware development board has all of the components and connectors required for it to be connected to a personal computer parallel printer port and for it to serve as a prototyping system board for the application under development. hardware development board The hardware development board contains a seven-digit LCD display, a 16-key keypad, sockets for four 512 × 8 EEPROMs, a socket for the TSS400-S1, connectors for the parallel printer port, all supply pins, input pins, and output pins of the TSS400-S1 and an on-board voltage regulator that allows you to power the system from the personal computer cable, a 9-V transistor battery, or a DC power supply. The development system comes with four EEPROMs, two standard TSS400s, a 3-V LCD, a 5-V LCD, and a cable to connect the development board to the personal computer. software simulator The software simulator, which will run on all IBM-AT compatible personal computers, allows fast development of application software for the TSS400-S1. All functions, with the exception of the hardware communication with inputs and outputs, can be simulated. The development of program algorithms requires no hardware. As shown in Figure 6, all internal registers, inputs, outputs, and flags are shown simultaneously on one screen. These may be modified whenever needed, even during simulator’s RUN mode, from the keyboard. Figure 6 shows the simulator software running on your PC. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 TSS400-S1 µPOWER PROGRAMMABLE HIGH-PRECISION SENSOR SIGNAL PROCESSOR SLMS001 – D4071, JANUARY 1993 APPLICATION INFORMATION Step Run(Snap) Go PC/Break Mem F1/F2/F3Wdws Init Load Write Target Help OS ESC Working Registers FLAC = + 00000000 REGB = + 00000000 Storage Registers ST00 = + 00000000 ST01 = + 00000000 ST02 = + 00000000 ST03 = + 00000000 ST04 = + 00000000 ST05 = + 00000000 Output R1 = 0 R2 = 0 R3 = 0 R4 = 0 R5 = 0 R6 = 0 Keyboard (Open=0) Latches DL 8 = 0 DL 9 = 0 DL10 = 0 DL11 = 0 DL12 = 0 DL13 = 0 Bp PC 023 024 025 026 1EA 1EB 1EC 1ED 1EE 1EF Code Mneumonic Lev 81 JP 116 0 16 0 69 CALL 1EA 0 EA 0 01 SetR 1 1 02 SetR 2 1 03 SetR 3 1 04 SetR 4 1 D2 DONE 1 11 RstR 1 1 –> Effect K–Port IN A1 is selected Svdd is OFF 0–Up 1 Hz Current OFF STS P = 0 Z = 0 N = 0 Tim L S T = 000 000 B = 000 000 Counter Cnt2 Cnt1 00 00 Batt. Check Voltage = 5.00 Volts A/D–Conv A1 = 800 A2 = 800 A3 = 800 A4 = 800 K–Port K1 = 0 K2 = 0 K4 = 0 K8 = 0 Group Flag 0 Flag 1 Flag 2 Flag 3 Flag 4 Flag 5 Flag 6 Flag 7 Flag 8 Flag 9 Flag10 Flag11 Flag12 Flag13 Flag14 Flag15 = = = = = = = = = = = = = = = = 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0123 4567 89ABCDEF 0000 0000 00000000 Figure 6. SDT-400 Simulator Screen real-time debugging After verification of all software parts that do not need connection to the target hardware, the real-time tests with the development board connected to the target hardware can begin. The development board is connected to the printer port on the personal computer by means of the included cable. The tested user’s program is burned into the EEPROMs with the appropriate simulator instruction and reread for verification. The user’s program, now stored in the EEPROMs on the development board, may be started and stopped by instructions from the software simulator. Real-time debugging with the development board is made by inserting pauses into the user’s program as desired, usually when some subprogram portion is complete. This may be after computations are complete, A / D conversions are complete, the keyboard has been tested, and so on. The following are several possible locations for the pauses and checking a program: • • • • 26 jumps to the same location waiting for a definitive key to be pressed displaying of the register that contains important information displaying of the registers with wait states POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (“Critical Applications”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local SC sales office. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. Copyright 1996, Texas Instruments Incorporated