TI TLC876IDW

TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
features
applications
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
10-Bit Resolution 20 MSPS Sampling
Analog-to-Digital Converter (ADC)
Power Dissipation . . . 107 mW Typ
5-V Single Supply Operation
Differential Nonlinearity . . . ±0.5 LSB Typ
No Missing Codes
Power Down (Standby) Mode
Three State Outputs
Digital I/Os Compatible With 5-V or 3.3-V
Logic
Adjustable Reference Input
Small Outline Package (SOIC), Super Small
Outline Package (SSOP), or Thin Small
Outline Package (TSOP)
Pin Compatible With the Analog
Devices AD876
description
Communications
Multimedia
Digital Video Systems
High-Speed DSP Front-End . . . TMS320C6x
DB, DW, OR PW PACKAGE
(TOP VIEW)
AGND
DRVDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DRGND
DGND
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
AVDD
AIN
CML
REFBS
REFBF
NC
REFTF
REFTS
DGND
AGND
DVDD
STBY
OE
CLK
The TLC876 is a CMOS, low-power, 10-bit, 20
13
16
MSPS analog-to-digital converter (ADC). The
14
15
speed, resolution, and single-supply operation
are suited for applications in video, multimedia,
NC – No internal connection
imaging, high-speed acquisition, and communications. The low-power and single-supply operation satisfy requirements for high-speed portable
applications. The speed and resolution ideally suit charge-coupled device (CCD) input systems such as color
scanners, digital copiers, electronic still cameras, and camcorders. A multistage pipelined architecture with
output error correction logic provides for no missing codes over the full operating temperature range. Force and
sense connections to the reference inputs provide a more accurate internal reference voltage to the reference
resistor string.
A standby mode of operation reduces the power to typically 15 mW. The digital I/O interfaces to either 5-V or
3.3-V logic and the digital output terminals can be placed in a high-impedance state. The format of the output
data is straight binary coding.
A pipelined multistaged architecture achieves a high sample rate with low power consumption. The TLC876
distributes the conversion over several smaller ADC sub-blocks, refining the conversion with progressively
higher accuracy as the device passes the results from stage to stage. This distributed conversion requires a
small fraction of the 1023 comparators used in a traditional flash ADC. A sample-and-hold amplifier (SHA) within
each of the stages permits the first stage to operate on a new input sample while the second through the fifth
stages operate on the four preceding samples.
The TLC876C is characterized for operation from 0°C to 70°C, the TLC876I is characterized for operation from
–40°C to 85°C, and the TLC876M is characterized for operation over the full military temperature range of –55°C
to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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1
TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
AVAILABLE OPTIONS
PACKAGE
TA
SUPER SMALL
OUTLINE
(DB)
SMALL
OUTLINE
(DW)
TSSOP
(PW)
0°C to 70°C
TLC876CDB
TLC876CDW
TLC876CPW
–40°C to 85°C
TLC876IDB
TLC876IDW
TLC876IPW
–55°C to 125°C
—
TLC876MDW
—
functional block diagram
AIN
SHA†
27
SHA†
GAIN
SHA†
SHA†
GAIN
GAIN
SHA†
GAIN
ADC
ADC
DAC
2
ADC
ADC
DAC
2
ADC
DAC
2
DAC
2
2
Correction Logic
10
Output Buffers
12
10
† Sample and hold amplifier
2
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3
(MSB) D9
(LSB) D0
TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
equivalent input and output circuits
D0–D9 OUTPUT CIRCUIT
ALL DIGITAL INPUT CIRCUITS
AIN INPUT CIRCUIT
DVDD
DVDD
AVDD
DRVDD
DRVDD
30 Ω typ
AIN
0.5 pF typ
CLK
D0–D9
0.3 pF
DRGND
DGND
AGND
DRGND
DGND
REFERENCE INPUT CIRCUIT
AVDD
REFTF
30
AVSS
AVDD
REFTS
Internal Reference
Voltage
29
AGND
AVDD
REFBS
35
Internal Reference
Voltage
AVSS
AVDD
REFBF
34
AGND
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3
TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
Terminal Functions
TERMINAL
NAME
AGND
NO.
1, 19
AIN
27
AVDD
CLK
28
CML
I/O
DESCRIPTION
Analog ground
I
Analog input
5-V analog supply
15
I
Clock input
26
O
Bypass for an internal bias point. Typically a 0.1 µF capacitor minimum is connected from this terminal to ground.
DGND
14, 20
Digital ground
DVDD
18
5-V digital supply
DRVDD
DRGND
2
3.3-V/5-V digital supply. Supply for digital input and output buffers.
13
3.3-V/5-V digital ground. Ground for digital input and output buffers.
D0 –D9
3 – 12
O
Digital data out. D0:LSB, D9:MSB
OE
16
I
Output enable. When OE = low or NC, the device is in normal operating mode. When OE = high, D0–D9 are high
impedance.
REFBF
24
I
Reference bottom force
REFBS
25
I
Reference bottom sense
REFTF
22
I
Reference top force
REFTS
21
I
Reference top sense
STBY
17
I
Standby enable. When STBY = low or NC, the device is in normal operating mode. When STBY = high, the device
is in standby mode.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, AVDD to AGND, DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V
Reference voltage input range to AGND, VI(REFTF), VI(REFBF), VI(REFBS),
VI(REFTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Analog input voltage range to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V
Digital output voltage range applied from external source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to DVDD
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
Operating free-air temperature range, TA: TLC876C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TLC876I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
TLC876M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DB
1353 mW
DW
1598 mW
DERATING FACTOR
ABOVE TA = 25°C ‡
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
10.82 mW/°C
866 mW
703 mW
—
12.78 mW/°C
1023 mW
831 mW
320 mW
PW
1207 mW
9.65 mW/°C
772 mW
627 mW
—
‡ This is the inverse of the traditional junction-to-ambient thermal resistance (RΘJA). Thermal resistance is not production tested,
and values given are for informational purposes only.
4
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TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
recommended operating conditions
analog and reference inputs
MIN
Reference input voltage (top), VI(REFT)
VI(REFB) + 1
0
Reference input voltage (bottom), VI(REFB)
Analog input voltage, VI(AIN)
1
NOM
MAX
UNIT
3.6
4.5
V
1.6
VI(REFT) – 1
V
2
Vpp
power supply
MIN
Supply voltage
AVDD †
DVDD†
NOM
MAX
4.5
5.25
4.5
5.25
DRVDD
3
† The voltage difference between AVDD and DVDD terminals cannot exceed 0.5 V to maintain performance specifications.
UNIT
V
5.25
digital inputs
MIN
High-level input voltage, VIH
Low-level input voltage, VIL
DRVDD = 3 V
DRVDD = 5 V
2.4
DRVDD = 5.25 V
DRVDD = 3 V
4.2
NOM
MAX
UNIT
V
4
0.6
DRVDD = 5 V
DRVDD = 5.25 V
1
V
1.05
Clock period, tc (see Figure 1)
50
ns
Pulse duration, clock high, tw(CLKH)
23
25
ns
Pulse duration, clock low, tw(CLKL)
23
25
ns
TLC876C
Operating free-air temperature, TA
0
70
TLC876I
–40
85
TLC876M
–55
125
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°C
5
TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
electrical characteristics at AVDD = DVDD = 5 V, DRVDD = 3.3 V, VI(REFT) = 3.6 V, VI(REFB) = 1.6 V,
fCLK = 20 MSPS (unless otherwise noted)
power supply
PARAMETER
IDD
Operating supply current
PD
TEST CONDITIONS
AVDD†
DVDD†
DRVDD
MIN
Power dissipation
PD(STBY)
Standby power
STBY = High
TYP
MAX
17
25
mA
2.7
5
mA
25
100
µA
mW
107
150
CLK running
45
85
CLK inhibited at VDD or 0 V
15
35
UNIT
mW
† The voltage difference between AVDD and DVDD terminals cannot exceed 0.5 V to maintain performance specifications.
digital logic inputs
PARAMETER
TEST CONDITIONS
MIN
IIH
IIH
High-level input current, STBY, OE
DVDD = 5 V
High-level input current, all other inputs
DVDD = 5 V
IIL
IIL(CLK)
Low-level input current
DVDD = 5V
–50
Low-level input current, CLK
DVDD = 5V
–10
Ci
Input capacitance
TYP
MAX
UNIT
1.9
mA
10
µA
50
µA
10
µA
5
pF
logic outputs
PARAMETER
VOH
High-level output voltage
TEST CONDITIONS
IOH = 50 µA
IOH = 0.5 mA
VOL
Low-level output voltage
IOL = 50 µA
IOL = 0.6 mA
Co
Output capacitance
IOZ
High-impedance-state output current
6
MIN
DRVDD = 3 V
DRVDD = 5 V
2.4
DRVDD = 5 V
DRVDD = 3.6 V
2.4
TYP
MAX
V
3.8
0.7
DRVDD = 5.25 V
DRVDD = 5.25 V
1.05
–10
• DALLAS, TEXAS 75265
V
0.4
5
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UNIT
pF
10
µA
TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
operating characteristics at AVDD = DVDD = 5 V, DRVDD = 3.3 V, VI(REFT) = 3.6 V, VI(REFB) = 1.6 V,
fCLK = 20 MSPS (unless otherwise noted)
dc accuracy
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Integral nonlinearity (INL)
± 1.5
Differential nonlinearity (DNL) (see Note 1)
± 0.5
Offset error
–0.4
%FSR
Gain error
0.2
%FSR
<± 1
LSB
NOTE 1: A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
analog input
PARAMETER
Ci
TEST CONDITIONS
MIN
Input capacitance
TYP
MAX
5
UNIT
pF
reference input
PARAMETER
Rref
Reference input resistance
Iref
Reference input current
TEST CONDITIONS
MIN
TYP
350
500
MAX
UNIT
Ω
4
mA
Reference top offset voltage
35
mV
Reference bottom offset voltage
35
mV
dynamic performance†
PARAMETER
TEST CONDITIONS
All suffixes
All suffixes
Eff ti number
Effective
b off bit
bits (ENOB)
C and I suffixes
M suffix
All suffixes
All suffixes
All suffixes
Signal to total harmonic distortion+noise
Signal-to-total
(S/(THD+N))
C and I suffixes
M suffix
All suffixes
Total harmonic distortion (THD)
fI = 3.58 MHz,,
TA = Full Range
MIN
fI = 3.58 MHz,
TA = 25°C
fI = 3.58 MHz,,
TA = Full Range
fI = 10 MHz
fI = 1 MHz
TYP
MAX
UNIT
8.5
8
8.5
8
8.5
Bit
Bits
7.5
fI = 10 MHz
fI = 1 MHz
fI = 3.58 MHz
fI = 10 MHz
fI = 3.58 MHz
Spurious free dynamic range
BW
fI = 1 MHz
fI = 3.58 MHz,
TA = 25°C
8.1
53
50
53
50
53
dB
47
51
–63
–62
–56
dB
–61
–64
dB
Analog input full-power bandwidth
200
MHz
Differential phase
0.5
degrees
Differential gain
1%
† The voltage difference between AVDD and DVDD cannot exceed 0.5 V to maintain performance specifications. At input clock rise times less than
20 ns, the offset full-scale error increases approximately by a factor of (20/tr)0.5 where tr equals the actual rise time in nanoseconds.
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7
TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
operating characteristics at AVDD = DVDD = 5 V, DRVDD = 3.3 V, VI(REFT) = 3.6 V, VI(REFB) = 1.6 V,
fCLK = 20 MSPS (unless otherwise noted)
timing requirements
PARAMETER
fconv
td(o)
TEST CONDITIONS
MIN
Maximum conversion rate (see Note 2)
Delay time, output
CL = 20 pF
td(pipe)
Delay time, pipeline, latency
td(A)
Delay time, aperture
5
20
CL = 20 pF
ns
Sample N+1
ns
5
15
ns
Sample N+2
AIN
td(A)
td(pipe)
tw(CLKH)
tw(CLKL)
CLK
tc
td(o)
Data N–4
Data N–3
td(o)
Data N–2
Data N–1
Data N
Figure 1. Timing Diagram
OE
tdis(DD)
D0–D9
ten(HL)
Active
High Impedance
Figure 2. Output Enable to Data Output Timing Diagram
STBY
Output Data Valid
CLK
Figure 3. Standby Timing
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ps
15
PARAMETER MEASUREMENT INFORMATION
Sample N
Clock
cycles
5
NOTE 2: The conversion rate can be a minimum of 10 kHz without degradation in specified performance.
8
ns
22
Enable time, OE↓ to valid data
UNIT
MHz
4
Disable time, OE↑ to Hi-Z
D0 – D9
MAX
3.5
Aperture jitter
tdis(DD)
ten(HL)
TYP
20
TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
TYPICAL CHARACTERISTICS
SIGNAL-TO-NOISE AND DISTORTION
vs
INPUT FREQUENCY
GAIN
vs
INPUT FREQUENCY
2
SINAD – Signal-to-Noise and Distortion – dB
55
G – Gain – dB
0
–2
–4
–6
–8
–10
1
10
100
fCLK = 20 MSPS
AIN = – 0.5 dB
50
45
40
1000
1
10
f – Input Frequency – MHz
f – Input Frequency – MHz
Figure 4
Figure 5
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
SIGNAL-TO-NOISE AND DISTORTION
vs
CLOCK FREQUENCY
60
SINAD – Signal-to-Noise and Distortion – dB
THD – Total Harmonic Distortion – dB
– 10
– 30
– 50
THD
– 70
3 rd
2 nd
– 90
1
10
fIN = 3.58 MHz
AIN = – 0.5 dB
55
50
45
40
5
f – Input Frequency – MHz
Figure 6
10
15
f – Clock Frequency – MHz
20
Figure 7
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9
TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
TYPICAL CHARACTERISTICS
POWER DISSIPATION
vs
CLOCK FREQUENCY
150
PD – Power Dissipation – mW
140
130
120
110
100
90
80
0
5
10
15
20
f – Clock Frequency – MHz
DNL – Differential Nonlinearity – LSB
Figure 8
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
0
255
511
Input Code
Figure 9. Differential Nonlinearity
10
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767
1023
TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
INL – Integral Nonlinearity – LSB
TYPICAL CHARACTERISTICS
3
2
1
0
–1
–2
–3
0
255
511
767
1023
Input Code
Figure 10. Integral Nonlinearity
SFDR
: –64 dB
SNRD
: 52 dB
SNR
: 55 dB
THD
2nd
: –62 dB
3rd
: –72 dB
: –69 dB
4th
5th
: –68 dB
6th
7th
: –71 dB
8th
9th
: –70 dB
: –71 dB
: –70 dB
: –80 dB
1
5
6
0
0.5
1
1.5
2
7
2.5
3
3.5
4
4.5
5
4
2
8
9
5.5
6
6.5
7
7.5
8
8.5
3
9
9.5 10
Frequency – MHz
Figure 11. FFT Plot of Dynamic Performance
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11
TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
PRINCIPLES OF OPERATION
definitions of specifications and terminology
integral nonlinearity (INL)
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as a level
1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to
the true straight line between these two points. This parameter is sometimes referred to as linearity error.
differential nonlinearity (DNL)
"
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.
A differential nonlinearity error of less than 1 LSB ensures no missing codes. This parameter is sometimes
referred to as differential error.
offset error
The first transition should occur at a level 1/2 LSB above zero. Offset is defined as the deviation of the actual
first code transition from that point.
gain error
The first code transition should occur for an analog value 1/2 LSB above nominal negative full scale (the voltage
applied to the REFBF terminal). The last transition should occur for an analog value 1 1/2 LSB below nominal
positive full scale (the voltage applied to the REFTF terminal). Gain error is the deviation of the actual difference
between the first and last code transitions from the ideal difference between the first and last code transitions.
pipeline delay (latency)
The number of clock cycles between conversion initiation on an input sample and the corresponding output data
being made available. Once the data pipeline is full, new valid output data are provided every clock cycle.
reference top/bottom offset
Resistance between the reference input and comparator input tap points causes offset errors. These errors can
be nulled out by using the force-sense connection as shown in the driving the reference terminals section.
driving the analog input
Figure 12 shows an equivalent input circuit of the TLC876 sample-and-hold amplifier and it represents an
excellent first order approximation.
The total equivalent capacitance, CE, is typically less than 5 pF and the input source must be able to charge
or discharge this capacitance to 10-bit accuracy in the sample period of one half of a clock cycle. When the
switch S1 closes, the input source must charge or discharge the capacitor CE from the voltage already stored
on CE (the previously captured sample) to the new voltage. In the worst case, a full-scale voltage step on the
input, the input source must provide the charging current through the switch resistance RSW (50 Ω) of S1 and
quickly settle (within 1/2 CLK period), and, therefore, the source is driving a low input impedance. However,
when the source voltage equals the value previously stored on CE, the hold capacitor requires no input current
to maintain the charge and the equivalent input impedance is extremely high.
Adding series resistance between the output of the source and the AIN terminal reduces the drive requirements
placed on the source, as shown in Figure 13. To maintain the frequency performance outlined in the
specifications, the resistor should be limited to 200 Ω minus the source resistance or less. The maximum source
resistance, RS, for 10-bit, 1/2 LSB accuracy is given by equation 1.
12
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TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
PRINCIPLES OF OPERATION
driving the analog input (continued)
R
S
v 2f
(1)
1
– R
SW
(C ln 2048)
E
(CLK)
For f(CLK) = 20 MHz, CE = 10 pF, and RSW = 100 Ω, this equation gives 228 Ω as a maximum value; hence the
200 Ω limit on the total source resistance. For applications with an input clock less than 20 MHz, the size of the
series resistor can increase proportionally. Alternatively, adding a shunt capacitor between the AIN terminal and
analog ground can lower the ac source impedance. This capacitance value depends on the source resistance
and the required signal bandwidth.
The input span is determined by the reference voltages (see driving the reference terminals section).
TLC876
AIN
Driving
Source
RS
Ideal Source
S1
RSW
VS
RS ≤ 200 Ω
TLC876
AIN
CE
VS
Figure 13. Sample TLC876 Drive Requirements
Figure 12. TLC876 Simplified Equivalent Input
For many applications, particularly in single supply operation, ac-coupling offers a convenient way of biasing
the analog input signal at the proper signal range. Figure 14 shows a typical configuration for ac-coupling the
analog input signal to the TLC876. Maintaining the outlined specifications requires careful selection of the
component values. The most important concern is the f–3 dB high-pass corner that is a function of R2, and the
parallel combination of C1 and C2. The f–3 dB point can be approximated by equation 2.
f
*3 dB + 2p
1
(R2) Ceq
(2)
where Ceq is the parallel combination of C1 and C2. Since C1 is typically a large electrolytic or tantalum
capacitor, the impedance becomes inductive at high frequencies. Adding a small ceramic or polystyrene
capacitor, C2 of approximately 0.01 µF, which is not inductive within the frequency range of interest, maintains
a low impedance. If the minimum expected input signal frequency is 20 kHz, and R2 equals 1 kΩ and R1 equals
50 Ω, the parallel capacitance of C1 and C2 must be a minimum of 0.008 µF to avoid attenuating signals close
to 20 kHz.
TLC876
C1
R1
AIN
VIN
R2
C2
+
VBIAS
–
Figure 14. AC-Coupled Inputs
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TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
PRINCIPLES OF OPERATION
driving the analog input (continued)
The expanded input circuit shown in Figure 15 aids in understanding the voltage offset generation when using
the external input circuit in Figure 14.
The ac-coupling capacitors, C1 and C2, integrate the switching transients present at the input of the TLC876
causing a net dc bias current, IB, to flow into the input. The magnitude of this bias current increases with
increasing the dc signal level, VB, and also increases with sample frequency. When the sample clock frequency
is 20 MHz, the dc bias current is approximately 30 µA† at VBIAS equal to 3 V dc. This bias current causes an
offset error of (R1 + R2) x IB at the AIN terminal. Making R2 negligibly small or modifying VBIAS to account for
the resultant offset can compensate for this error. Note however that R2 loads the signal driving source, and
the value must be sufficient for the application.
For example, as shown in Figure 15, when VBIAS is 3 V and the resistor values stated above, the bias current
causes a 31.5 mV‡ offset from the 3 V bias, VBIAS, at the AIN terminal. For the TLC876, VBIAS can be as low
as 1 V for a 2 V peak-to-peak input signal swing.
C1
TLC876
R1
VB
VIN
AIN
RSW
IB
R2
CE
C2
+
VBIAS
–
Figure 15. Bias Current and Offset
For systems that require dc-coupling, an op-amp can level-shift a ground-referenced signal to comply with the
input requirements of the TLC876. Figure 16 shows an amplifier in an inverting mode with ac signal gain of –1.
The dc voltage at the noninverting input of the op-amp controls the amount of dc level shifting. A resistive voltage
divider attenuates the REFBF signal and the op-amp then multiplies the attenuated signal by 2. In the case
where REFBF = 1.6 V, the dc output level is 2.6 V which is approximately equal to (V(REFTF) – V(REFBF)/2.
† IB(AVG) = CE (VB) fCLK ≈ 30 µA, with RSW = 50 Ω, CE = 5 pF, R1 = 50 Ω, and R2 = 1 kΩ
‡ VOFFSET = IB(AVG) (R1 + R2)
14
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TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
PRINCIPLES OF OPERATION
driving the analog input (continued)
RL = 4.99 kΩ
VCC
0.1 µF
TLC876
NC
RIN = 4.99 kΩ
2
2V(PP)
0 V dc
3 kΩ
3
REFBF
7
1
–
A†
+
6
AIN
5
4
NC
14.7 kΩ
† Amplifier A can be an AD817 or AD818 with terminal numbers as shown. The AD817 and AD818
are wide bandwidth single supply op-amps.
Figure 16. Bipolar Level Shift
driving the reference terminals
dc considerations
The TLC876 requires an external reference on terminals REFTF and REFBF and a resistor array, nominally
500 Ω, is connected between terminals REFTF and REFBF. A Kelvin connection, using the TLC876 reference
sense terminals REFTS and REFBS, minimizes voltage drops caused by external and internal wiring
resistance.
Figure 17 shows the equivalent input structure for the reference terminals. There is approximately 5 Ω of
resistance between both REFTF and REFBF terminals and the reference ladder. If the force-sense connections
are not used, the voltage drop across the 5-Ω resistors results in a reduced voltage appearing across the ladder
resistance. This reduces the input span of the converter. Applying a slightly larger span between the REFTF
and REFBF terminals compensates for this error. Note that the temperature coefficients of the 5-Ω resistors are
1350 ppm. The effects of temperature should be considered when a force-sense reference configuration is not
used.
5Ω
TLC876
REFTF
10 Ω
5Ω
5Ω
5Ω
CLK
REFTS
RARRAY
500 Ω
DAC
C (Equivalent)
CLK
REFBS
10 Ω
5Ω
5Ω
5Ω
REFBF
5Ω
Figure 17. TLC876 Equivalent Reference Structure
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10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
PRINCIPLES OF OPERATION
dc considerations (continued)
The REFTS and REFBS terminals should not be connected in configurations that do not use a force-sense
reference. Connecting the force and sense lines together allows current to flow in the sense lines. Any current
allowed to flow through these lines must be negligibly small. Current flow causes voltage drops across the
resistance in the sense lines. Because the internal DACs tap different points along the sense lines, each DAC
would receive a slightly different reference voltage if current were flowing in these lines. To avoid this undesirable
condition, leave the sense lines unconnected. Any current allowed to flow through these lines must be negligibly
small (< 100 µA).
The voltage drop across the internal resistor array (RARRAY) determines the input span. The nominal differential
voltage is 2 Vpp. The full-scale input span is given by equation 3.
Input Voltage Span = V(REFTS) – V(REFBS)
(3)
Therefore, a full-scale input span is approximately 2 V when [V(REFTS) – V(REFBS)] = 2 V. The external
reference must provide approximately 4 mA for a 2-V drop across the internal resistor array.
Figure 18 shows the flexibility in determining both the full-scale span of the analog input and where to center
this voltage without degrading the typical performance.
5
4.5
4
REFTF, REFTS
3.5
2 V Span
3
2.5
1 V Span
2
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
REFBF, REFBS
3
3.5
4
Figure 18. TLC876 Reference Ranges
ac considerations
The simplified diagram of Figure 17 shows that the reference terminals connect to a capacitor for one half of
the clock period. The size of the capacitor is a function of the analog input voltage, therefore producing dynamic
impedance changes at the reference inputs.
The external reference source must be able to maintain a low impedance over all frequencies of interest to
provide the charge required by the capacitance. By supplying the requisite charge, the reference voltages
remain relatively constant maintaining specified performance. For some reference configurations, voltage
transients are present on the reference lines, especially during the falling edge of CLK. The reference must
recover from the transients and settle to the desired level of accuracy prior to the rising edges of CLK.
16
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10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
PRINCIPLES OF OPERATION
ac considerations (continued)
Several useful reference configurations can be used depending on the application, desired level of accuracy,
and cost tradeoffs. The simplest configuration, shown in Figure 19, utilizes a resistor divider to generate the
reference voltages from the converters analog power supply. The 0.1 µF bypass capacitors reduce high
frequency transients. The 10 µF capacitors reduce the impedances at the REFTF and REFBF terminals at lower
frequencies; however, as input frequencies approach dc, the capacitors become ineffective, and small voltage
deviations appear across the biasing resistors. This reference method maintains 10-bit accuracy for input
frequencies above approximately 200 Hz and 8-bit accuracy applications for input frequencies above
approximately 50 Hz.
TLC876
NC
140 Ω (± 1%)
REFTS
4V
5V
10 µF
REFTF
0.1 µF
500 Ω
250 Ω (± 1%)
2V
REFBF
10 µF
0.1 µF
NC
REFBS
NC – No connect
Figure 19. Low Cost Reference Circuit
The reference configuration in Figure 19 provides the lowest cost, but the disadvantages include reduced dc
power supply rejection and reduced accuracy due to the variability of the internal and external resistors.
The force-sense reference connections can eliminate the voltage drops associated with the internal
connections to the reference ladder. Figure 20 shows a circuit using a dual, rail-to-rail single-supply operational
amplifier. The operational amplifier should provide stable 3.6 V and 1.6 V reference voltages. Each half of the
amplifier is compensated to drive 1 µF and 0.1 µF decoupling capacitors at the REFTF and REFBF terminals
maintaining stability. The operational amplifiers are connected as voltage followers.
By connecting the operational amplifier feedback through the sense connections of the TLC876, the outputs
of the operational amplifiers automatically adjust to compensate for the voltage drops that occur within the
converter.
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TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
PRINCIPLES OF OPERATION
ac considerations (continued)
TLC876
REFTS
5V
C3
0.1 µF
_
REFTF
REFT
+
C2
0.1 µF
REFBS
_
C4
0.1 µF
REFBF
REFB
+
C1
0.1 µF
Figure 20. Kelvin Connection Reference Using an Operational Amplifier
With Unlimited Capacitive Load Drive Capability
Figure 21 shows a circuit using a dual operational amplifier with unlimited capacitive load drive. The operational
amplifier should provide stable 3.6 V and 1.6 V reference voltages for REFTF and REFBF, respectively. The
amplifier must be able to maintain stability while driving unlimited capacitive loads, so the 0.1 µF capacitors C1
and C2 can connect directly to the outputs of the operational amplifiers, which reduces high frequency
transients. Capacitors C3 and C4 shunt across the internal resistors of the force-sense connections and prevent
instability. The stability of any operational amplifier used must be examined closely when driving capacitive
loads.
TLC876
10 kΩ
REFTS
0.1 µF
10 kΩ
REFT
_
A†
+
10 Ω
REFTF
1 µF
0.1 µF
10 kΩ
REFBS
10 kΩ
REFB
0.1 µF
_
A†
+
10 Ω
1 µF
REFBF
0.1 µF
† This device is 1/2 of a TLV2442. The TLV2442 is a rail-to-rail output dual operational
amplifier.
Figure 21. Kelvin Connection Reference Using an Operational Amplifier
With Unlimited Capacitive Load Drive Capability
18
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TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
PRINCIPLES OF OPERATION
layout and decoupling
With high-frequency high-resolution converters, the layout and decoupling of the reference is critical. The actual
voltage digitized by the TLC876 is relative to the reference voltages. In Figure 22, for example, the reference
return and the bypass capacitors are connected to the shield of the incoming analog signal. Disturbances in the
ground of the analog input, that are common mode to the REFTF, REFBF, and AIN terminals because of the
common ground, are effectively removed by the TLC876 high common mode rejection. Also, these capacitors
should be connected as close to reference terminals as possible.
High-frequency noise sources, VN1 and VN2, are shunted to ground by decoupling capacitors. Any voltage drops
between the analog input ground and the reference bypassing points are treated as input signals by the
converter using the reference inputs. Consequently, the reference decoupling capacitors should be connected
to the same physical analog ground point used by the analog input voltage (see the grounding and layout rules
section).
4V
VN1
REFTF
4V
VN2
TLC876
REFBF
AIN
Figure 22. Recommended Bypassing for the Reference
clock input
The clock input is buffered internally with an inverter powered from the DRVDD terminal, which accommodates
either 5-V or 3.3-V CMOS logic input signal swings with the input threshold for the CLK terminal nominally at
DRVDD/2.
The internal pipelined architecture operates on both rising and falling edges of the input clock. To minimize duty
cycle variations, the recommended logic family to drive the clock input is high-speed or advanced CMOS
(HC/HCT, AC/ACT) logic. CMOS logic provides both symmetrical voltage threshold levels and sufficient rise and
fall times to support 20 MSPS operation.
The power dissipated by the correction logic and output buffers is largely proportional to the clock frequency.
Figure 8 illustrates this tradeoff between clock rates and a reduction in power consumption.
digital inputs and outputs
Each of the digital control inputs, OE and STBY, has an input buffer powered from the DRVDD supply terminal.
With DRVDD set to 5 V, all digital inputs readily interface with 5 V CMOS logic. Using lower voltage CMOS logic,
DRVDD can be set to 3.3 V, lowering the nominal input threshold of all digital inputs to (3.3 V)/2 = 1.65 V, typically.
The digital output format is straight binary. For example, Table 1 shows the output format for voltage levels of
V(REFTS) = 4 V and V(REFBS) = 2 V.
A low power mode feature is provided such that when STBY is high and the clock is disabled, the static power
of the TLC876 drops significantly (see electrical characteristics table).
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TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
PRINCIPLES OF OPERATION
digital inputs and outputs (continued)
Table 1. Output Data Format
DATA
AIN VOLTAGE
(APPROXIMATE)
THREE
STATE
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
>4V
0
1
1
1
1
1
1
1
1
1
1
4V
0
1
1
1
1
1
1
1
1
1
1
3V
0
1
0
0
0
0
0
0
0
0
0
2V
0
0
0
0
0
0
0
0
0
0
0
<2V
0
0
0
0
0
0
0
0
0
0
0
X
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
grounding and layout rules
Proper grounding and layout techniques are essential for achieving optimal performance. The analog and digital
grounds on the TLC876 have been separated to optimize the management of return currents in a system. A
printed circuit board (PCB) of at least 4 layers employing a ground plane and power planes should be used with
the TLC876. The use of ground and power planes offers distinct advantages:
D
D
D
Minimizes the loop area encompassed by a signal and its return path
Minimizes the impedance associated with ground and power paths
The inherent distributed capacitor formed by the power plane, PCB insulation, and ground plane
These characteristics produce a reduction of electromagnetic interference (EMI) and an overall improvement
in performance.
A properly designed layout prevents noise from coupling onto the input signal. Digital signal traces should not
run parallel with the input signal traces and should be routed away from the input circuitry. The separate analog
and digital grounds should be joined together directly under the TLC876. A solid ground plane under the TLC876
is also acceptable if no significant currents are flowing in that portion of the ground plane under the device. The
general rule for mixed signal layouts is that return currents from digital circuitry should not pass through or under
critical analog circuitry. The system design should minimize the analog lead-in to reduce potential noise pickup.
digital outputs
The DRVDD supply terminal powers each of the on-chip buffers for the output bits (D0–D9) and is a separate
lead from AVDD or DVDD. The output drivers are sized to drive a variety of logic families, while minimizing the
amount of glitch energy generated. A recommended fan-out of one keeps the capacitive load on the output data
drivers below the specified 20 pF level.
For DRVDD = 5 V, the output signal swing can drive both high-speed CMOS and TTL logic families. For TTL,
the on-chip output drivers are designed to support several of the high-speed TTL families (F, AS, S). For
applications where the clock rate is below 20 MSPS, other TTL families are appropriate. For interfacing with
lower voltage CMOS logic, the TLC876 sustains 20 MSPS operation with DRVDD = 3.3 V. Refer to logic family
data sheets for compatibility with the TLC876 digital specifications.
20
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PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
5962-9954001NXD
ACTIVE
SOIC
DW
28
1
Lead/Ball Finish
Green (RoHS &
no Sb/Br)
CU NIPDAU
MSL Peak Temp (3)
Level-1-260C-UNLIM
TLC876CDB
OBSOLETE
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DB
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PW
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(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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