HD74HCT237 3-to-8-line Decoder/Demultiplexer with Address Latch Description The HD74HCT237 decodes a three-bit Address to one-of-eight active-high outputs. The device has a transparent latch for storage of the Address. Two Chip Selects, one active-low and one active-high, are provided to facilitate the demultiplexing, cascading, and chip-selecting functions. The demultiplexing function is accomplished by using the Address inputs to select the desired device output, and then by using one of the Chip Select as a data input while holding the other one active. The HD74HCT237 is the noninverting version of the HD74HCT137. Features • • • • • • LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (A, B, C to Y) = 23 ns typ (C L = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) HD74HCT237 Function Table Inputs Enable Select Outputs GL G1 G2 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X H X X X L L L L L L L L X L X X X X L L L L L L L L L H L L L L H L L L L L L L L H L L L H L H L L L L L L L H L L H L L L H L L L L L L H L L H H L L L H L L L L L H L H L L L L L L H L L L L H L H L H L L L L L H L L L H L H H L L L L L L L H L L H L H H H L L L L L L L H H H L X X X Output Corresponding to stored address L; all others H A 1 16 VCC B 2 B C 3 GL Pin Arrangement A Y0 15 Y0 C Y1 14 Y1 4 GL Y2 13 Y2 G2 5 G2 Y3 12 Y3 G1 6 G1 Y4 11 Y4 Y7 7 Y7 Y5 10 Y5 GND 8 Y6 9 (Top view) 2 Y6 HD74HCT237 Logic Diagram A Y0 Y1 B Y2 Y3 Y4 C Y5 Y6 GL Y7 G2 G1 DC Characteristics Ta = –40 to +85°C Ta = 25°C Test Conditions Item Symbol Min Typ Max Min Max Unit VCC (V) Input voltage VIH 2.0 — — — V 4.5 to 5.5 VIL — — 0.8 — 0.8 V 4.5 to 5.5 VOH 4.4 — — 4.4 — V 4.5 Vin = VIH or VIL I OH = –20 µA 4.18 — — 4.13 — 4.5 I OH = –4 mA — — 0.1 — 0.1 — — 0.26 — 0.33 Output voltage VOL 2.0 V 4.5 Vin = VIH or VIL I OL = 20 µA 4.5 I OL = 4 mA Input current Iin — — ±0.1 — ±1.0 µA 5.5 Vin = VCC or GND Quiescent supply current I CC — — 4.0 — 40 µA 5.5 Vin = VCC or GND, Iout = 0 µA 3 HD74HCT237 AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Ta = –40 to +85°C Ta = 25°C Test Conditions Min Typ Max Min Max Unit VCC (V) Propagation delay t PLH — 21 37 — 46 ns 4.5 time t PHL — 25 37 — 46 t PLH — 18 29 — 36 t PHL — 14 29 — 36 t PLH — 16 29 — 36 t PHL — 18 29 — 36 t PLH — 22 38 — 48 t PHL — 27 38 — 48 Pulse width tw 16 8 — 20 — ns 4.5 Setup time t su 20 6 — 25 — ns 4.5 Hold time th 5 –1 — 5 — ns 4.5 Output rise/fall time t TLH t THL — 5 15 — 19 ns 4.5 Input capacitance Cin — 5 10 — 10 pF — Item 4 Symbol A, B or C to Y 4.5 ns 4.5 G2 to Y 4.5 ns 4.5 G1 to Y 4.5 ns 4.5 4.5 GL to Y Unit: mm 19.20 20.00 Max 1 7.40 Max 9 6.30 16 8 1.3 0.48 ± 0.10 2.54 Min 5.06 Max 2.54 ± 0.25 0.51 Min 1.11 Max 7.62 + 0.13 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-16 Conforms Conforms 1.07 g Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0.80 Max *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 5.5 16 0.20 7.80 +– 0.30 1.15 0° – 8° 0.70 ± 0.20 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DA — Conforms 0.24 g Unit: mm 9.9 10.3 Max 9 1 8 0.635 Max *0.42 ± 0.08 0.40 ± 0.06 0.15 *0.22 ± 0.03 0.20 ± 0.03 1.27 0.11 0.14 +– 0.04 1.75 Max 3.95 16 0.10 6.10 +– 0.30 1.08 0° – 8° 0.67 0.60 +– 0.20 0.25 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DN Conforms Conforms 0.15 g Cautions 1. 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