bq24640 www.ti.com SLUSA44 – MARCH 2010 High-Efficiency Synchronous Switch-Mode Super Capacitor Charger Check for Samples: bq24640 FEATURES 1 • • • • APPLICATIONS • • • LODRV PACKAGE 16 15 14 13 VCC 1 12 REGN 11 GND 10 SRP 9 SRN OGA CE 2 bq24640 QFN-16 STAT 3 TOP VIEW TS 4 5 6 7 8 VFB • The bq24640 has an input CE pin to enable and disable charge; and, the STAT and PG output pins report charge and adapter status. The TS pin on the bq24640 monitors the temperature of the capacitor and suspends charge during HOT/COLD conditions. PH • The bq24640 enters a low-current sleep mode (<15mA) when the input voltage falls below the output capacitor voltage. ISET • The bq24640 charges super capacitor in two phases: constant current and constant voltage. The charge starts from down to 0V with current set on ISET pin. The charge current starts tapering down, when the voltage on VFB reaches an internal reference, HIDRV • • The bq24640 is highly integrated switch-mode super capacitor charge controller. It offers a constantfrequency synchronous PWM controller with high accuracy charge current and voltage regulation, and charge status monitoring. VREF • DESCRIPTION BTST • Charge Super Capacitor Pack from 2.1V to 26V CC–CV Charge Profile from 0V Without Precharge 600kHz NMOS-NMOS Synchronous Buck Controller Over 90% Efficiency for up to 10A Charge Current 5V–28V VCC Input Voltage Range Accuracy – ±0.5% Charge Voltage Regulation – ±3% Charge Current Regulation High Integration – Internal Loop Compensation – Internal Digital Soft Start Safety – Input Over-Voltage Protection – Capacitor Temperature Sensing Hot/Cold Charge Suspend – Thermal Shutdown Status Outputs – Adapter Present – Charger Operation Status Charge Enable Pin 30ns Driver Dead Time and 99.5% Max Effective Duty Cycle Automatic Sleep Mode for Low Power Consumption – <15µA Off-State Super Capacitor Discharge Current – <1.5mA Off-State Input Quiescent Current Small 3.5 × 3.5 mm2 QFN-16 Package PG • • Memory Backup System Industrial UPS system and Power Transient Buffering Bridge Power to Buffer the Battery 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated bq24640 SLUSA44 – MARCH 2010 www.ti.com TYPICAL APPLICATION D2 MBRS540T3 Adapter R6: 10 W R 11 2W C2 2.2 mF Temp S ensing C8 10 m F C 7: 1 mF R7 100 kW R9 9.31 kW C4 1 mF VREF CE VCC REGN ISET BTST R 5: 100 W HIDRV TS R8 22.1 kW R10 10k (SEMITEC 430 kW 103AT - 2) C1 0.1 m F PH C5:1 mF D1 BAT54 Q4 C6 0. 1 mF SRP R1 4:10 kW L: 6.8 µ H SiS412DN STAT R1 3 :10 kW RSR 10m W SiS412DN Q5 LODRV GND Adapter C9 10 m F C10 0.1 m F C1 1: 0.1 µ F PG C12 10mF C13 10 mF R2 300 kW Cff 22 pF R1 105 kW SRN bq24640 Super C apacitor VFB PwrPad VIN = 19 V, VOUT = 8.1 V, Icharge = 3 A, Temperature range 0–45°C Figure 1. Typical System Schematic PIN FUNCTIONS PIN NO. NAME TYPE (1) PIN DESCRIPTION 1 VCC P IC power positive supply. Connect through a 10-Ω resistor to the cathode of input diode. Place a 1-mF ceramic capacitor from VCC to GND and place it as close as possible to IC to filter out the noise. 2 CE I Charge enable, active HIGH logic input. HI enables charge, and LO disables charge. Connect to pull-up rail with 10-kΩ resistor. It has an internal 1-MΩ pull-down resistor. 3 STAT O Open drain charge status output to indicate various charger operation. Connect to the pull-up rail through the LED and 10-kΩ. (See Table 3) 4 TS I Temperature qualification voltage input for negative temperature coefficient thermistor. Program the hot and cold temperature window with a resistor divider from VREF to TS to GND. Recommend SEMITEC 103AT-2 10-kΩ thermister. 5 PG O Open drain active-low adapter status output. Connect to pull-up rail through LED and 10 kΩ resistor. The LED turns on when a valid is detected, and off in the sleep mode. 6 VREF P 3.3V reference voltage output. Place a 1-mF ceramic capacitor from VREF to GND pin close to the IC. This voltage could be used for programming charge current regulation on ISET and for thermal threshold on TS. It can be used as the pull up rail of STAT, and PG. 7 ISET I Charge current set point. The voltage is set through a voltage divider from VREF to ISET and to GND. ICHG = (1) 2 VISET 20 ´ RSR 8 VFB I Charge voltage analog feedback adjustment. Connect a resistor divider from output to VFB to GND to adjust the output voltage. The internal regulation limit is 2.1V. 9 SRN I Charge current sense resistor, negative input. A 0.1-mF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. An optional 0.1-mF ceramic capacitor is placed from SRN pin to GND for common-mode filtering. 10 SRP P/I Charge current sense resistor, positive input. A 0.1-mF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. A 0.1-mF ceramic capacitor is placed from SRP pin to GND for common-mode filtering. 11 GND P Low-current sensitive analog/digital ground. On PCB layout, connect with PowerPad underneath the IC. 12 REGN P PWM low side driver positive 6V supply output. Connect a 1-mF ceramic capacitor from REGN to GND pin close to the IC. Use for low side driver and high-side driver bootstrap voltage by small signal Schottky diode from REGN to BTST. 13 LODRV O PWM low side driver output. Connect to the gate of the low side N-channel power MOSFET with a short trace. P - Power, I - Input, O - Output Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24640 bq24640 www.ti.com SLUSA44 – MARCH 2010 PIN FUNCTIONS (continued) PIN NO. NAME TYPE (1) PIN DESCRIPTION 14 PH P Switching node, charge current output inductor connection. Connect the 0.1-mF bootstrap capacitor from PH to BTST. 15 HIDRV O PWM high side driver output. Connect to the gate of the high side N-channel power MOSFET with a short trace. 16 BTST P PWM high side driver positive supply. Connect the 0.1-mF bootstrap capacitor from PH to BTST. PowerPad Exposed pad beneath the IC. Always solder Power Pad to the board, and have vias on the Power Pad plane star-connecting to GND and ground plane for high-current power converter. It also serves as a thermal pad to dissipate the heat. ORDERING INFORMATION PART NUMBER IC MARKING PACKAGE bq24640 OGA 16-PIN 3.5×3.5 mm QFN ODERING NUMBER (Tape and Reel) QUANTITY bq24640RVAR 3000 bq24640RVAT 250 THERMAL INFORMATION bq24640 THERMAL METRIC (1) (RVA) UNITS (QFN-16) PINS Junction-to-ambient thermal resistance (2) qJA 43.8 (3) qJC(top) Junction-to-case(top) thermal resistance qJB Junction-to-board thermal resistance yJT Junction-to-top characterization parameter yJB Junction-to-board characterization parameter qJC(bottom) (1) (2) (3) (4) (5) (6) (7) 81 (4) 16 (5) Junction-to-case(bottom) thermal resistance 0.6 (6) (7) °C/W 15.77 4 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, yJB estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24640 3 bq24640 SLUSA44 – MARCH 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE VCC, SRP, SRN, STAT, PG, CE PH Voltage range (2) Maximum difference voltage VFB (3) MAX –0.3 33 –2 33 –0.3 16 REGN, LODRV, TS –0.3 7 BTST, HIDRV with respect to GND –0.3 39 VREF, ISET –0.3 3.6 SRP–SRN –0.5 0.5 Electrostatic Discharge (HBM) QSS 009-105 (JESD22-A114A) Electrostatic Discharge (CDM) QSS 009-147 (JESD22-C101B.01) Temperature (1) (2) (3) UNIT MIN V 2 kV 500 V TJ –40 155 Tstg –55 155 °C Must have a series resistor between output to VFB if output voltage is expected to be greater than 16V. Usually the resistor divider top resistor will take care of this. Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult the Package Option Addendum at the end of the data sheet for thermal limitations and considerations. RECOMMENDED OPERATING CONDITIONS VALUE / UNIT VCC, SRP, SRN, STAT, PG, CE Voltage range (with respect to GND) –0.3 V to 28 V PH –2 V to 30 V VFB –0.3 V to 14 V REGN, LODRV, TS –0.3 V to 6.5 V BTST, HIDRV with respect to GND –0.3 V to 34 V ISET –0.3 V to 3.3 V VREF Maximum difference voltage 3.3 v SRP–SRN –0.2 V to 0.2 V Junction temperature range, TJ 0°C to 125°C Storage temperature range, Tstg –55°C to 155°C ELECTRICAL CHARACTERISTICS 5.0 V ≤ V(VCC) ≤28 V, 0°C < T < +125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS OPERATING CONDITIONS VVCC_OP VCC input voltage operating range 5 28 V 15 µA 1 1.5 mA 2 5 mA QUIESCENT CURRENTS IOUT Total output discharge current (sum of currents into VCC, BTST, PH, SRP, SRN, VFB), VFB ≤ 2.1V VUVLO < VVCC < VSRN (SLEEP) VVCC > VSRN, VVCC > VUVLO, CE = LOW IAC VVCC > VSRN, VVCC > VVCCLOWV, Adapter supply current into VCC pin CE = HIGH, charge done VVCC > VSRN, VVCC > VVCCLOWV, CE = HIGH, Charging, Qg_total = 20 nC, VVCC = 20 V 4 Submit Documentation Feedback 25 mA Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24640 bq24640 www.ti.com SLUSA44 – MARCH 2010 ELECTRICAL CHARACTERISTICS (continued) 5.0 V ≤ V(VCC) ≤28 V, 0°C < T < +125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS CHARGE VOLTAGE REGULATION VFB Feedback regulation voltage 2.1 Charge voltage regulation accuracy IVFB Leakage current into VFB pin V TJ = 0°C to 85°C –0.5% 0.5% TJ = –40°C to 125°C –0.7% 0.7% VFB = 2.1 V 100 nA 2 V CURRENT REGULATION VISET1 ISET voltage range VIREG_CHG SRP-SRN current sense voltage range VIREG_CHG = VSRP – VSRN KISET1 Charge current set factor (amps of charge current per volt on ISET pin) RSENSE = 10 mΩ Charge current regulation accuracy IISET Leakage current into ISET pin 100 5 mV A/V VIREG_CHG = 40 mV -3% VIREG_CHG = 20 mV -5% 3% 5% VIREG_CHG = 5 mV –25% 25% VIREG_CHG = 1.5 mV –50% 50% VISET1 = 2 V 100 nA INPUT UNDER-VOLTAGE LOCK-OUT COMPARATOR (UVLO) VUVLO AC under-voltage rising threshold VUVLO_HYS AC under-voltage hysteresis, falling Measure on VCC 3.65 3.85 4 V 350 mV 4.1 V VCC LOWV COMPARATOR VLOWV_FALL Falling threshold, disable charge VLOWV_RISE Rising threshold, resume charge Measure on VCC 4.35 4.5 V 100 150 mV SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION) VSLEEP _FALL SLEEP falling threshold VVCC – VSRN to enter SLEEP 40 SLEEP hysteresis 500 mV SLEEP rising delay VCC falling below SRN, Delay to pull up PG 1 µs SLEEP falling delay VCC rising above SRN, Delay to pull down PG 30 ms SLEEP rising shutdown deglitch VCC falling below SRN, Delay to enter SLEEP mode 100 ms SLEEP falling powerup deglitch VCC rising above SRN, Delay to exit SLEEP mode 30 ms VSLEEP_HYS OUT OVER-VOLTAGE COMPARATOR VOV_RISE Over-voltage rising threshold As percentage of VVFB 104% VOV_FALL Over-voltage falling threshold As percentage of VVFB 102% INPUT OVER-VOLTAGE COMPARATOR (ACOV) VACOV AC over-voltage rising threshold VACOV_HYS AC over-voltage falling hysteresis Measured on VCC 31 32 33 V 1 V AC over-voltage rising deglitch Delay to disable charge 1 ms AC over-voltage falling deglitch Delay to resume charge 1 ms Temperature Increasing 145 °C 15 °C Thermal shutdown rising deglitch Temperature Increasing 100 µs Thermal shutdown falling deglitch Temperature Decreasing 10 ms THERMAL SHUTDOWN COMPARATOR TSHUT Thermal shutdown rising temperature TSHUT_HYS Thermal shutdown hysteresis Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24640 5 bq24640 SLUSA44 – MARCH 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) 5.0 V ≤ V(VCC) ≤28 V, 0°C < T < +125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS THERMISTOR COMPARATOR VLTF Cold temperature rising threshold As percentage to VVREF VLTF_HYS Rising hysteresis As percentage to VVREF 72.5% 73.5% 74.5% 0.2% VHTF Hot temperature rising threshold As percentage to VVREF 36.4% VTCO Cut-off temperature rising threshold As percentage to VVREF 33.7% 34.4% 35.1% Deglitch time for temperature out of range detection VTS < VLTF, or VTS < VTCO, or VTS < VHTF Deglitch time for temperature in valid range detection VTS > VLTF – VLTF_HYS or VTS >VTCO, or VTS > VHTF 0.4% 0.6% 37% 37.6% 400 ms 20 ms 45.5 mV CHARGE OVER-CURRENT COMPARATOR (CYCLE-BY-CYCLE) Charge over-current rising threshold VOC Current rising, in non-synchronous mode, measure on V(SRP-SRN), VSRP < 2V Current rising, as percentage of V(IREG_CHG), in synchronous mode, VSRP > 2.2V 160% Charge over-current threshold floor Minimum OCP threshold in synchronous mode, measure on V(SRP-SRN), VSRP > 2.2V 50 mV Charge over-current threshold ceiling Maximum OCP threshold in synchronous mode, measure on V(SRP-SRN), VSRP > 2.2V 180 mV CHARGE UNDER-CURRENT COMPARATOR (CYCLE-BY-CYCLE) VISYNSET Charge under-current falling threshold Switch from CCM to DCM, VSRP>2.2V 1 5 9 mV LOW CHARGE CURRENT COMPARATOR VLC Low charge current (average) falling threshold to force into Measure V(SRP-SRN) non-synchronous mode 1.25 mV VLC_HYS Low charge current rising hysteresis 1.25 mV VLC_DEG Deglitch on both edge 1 µs VREF REGULATOR VVREF_REG VREF regulator voltage VVCC > VUVLO (0–35 mA load) 3.267 IVREF_LIM VREF current limit VVREF = 0 V, VVCC > VUVLO 35 3.3 3.333 V mA REGN REGULATOR VREGN_REG REGN regulator voltage VVCC > 10V, CE = HIGH (0–40mA load) 5.7 IREGN_LIM REGN current limit VREGN = 0V, VVCC > VUVLO, CE = HIGH 40 6.0 6.3 V mA PWM HIGH SIDE DRIVER (HIDRV) RDS_HI_ON High side driver (HSD) turn-on resistance VBTST – VPH = 5.5 V 3.3 6 Ω RDS_HI_OFF High side driver turn-off resistance VBTST – VPH = 5.5 V 1 1.3 Ω VBTST_REFRESH Bootstrap refresh comparator threshold voltage VBTST – VPH when low side refresh pulse is requested 4.0 4.2 V PWM LOW SIDE DRIVER (LODRV) RDS_LO_ON Low side driver (LSD) turn-on resistance RDS_LO_OFF Low side driver turn-off resistance 4.1 7 Ω 1 1.4 Ω PWM DRIVERS TIMING Driver Dead-Time Dead time when switching between LSD and HSD, no load at LSD and HSD PWM ramp height As percentage of VCC 30 ns PWM OSCILLATOR VRAMP_HEIGHT PWM switching frequency 6 7% 510 Submit Documentation Feedback 600 690 kHz Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24640 bq24640 www.ti.com SLUSA44 – MARCH 2010 ELECTRICAL CHARACTERISTICS (continued) 5.0 V ≤ V(VCC) ≤28 V, 0°C < T < +125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS INTERNAL SOFT START (8 steps to regulation current ICHG) Soft start steps Soft start step time 8 step 1.6 ms LOGIC IO PIN CHARACTERISTICS (CE, STAT, PG) VIN_LO CE input low threshold voltage VIN_HI CE input high threshold voltage 0.8 V VBIAS_CE CE input bias current VCE = 3.3V (CE has internal 1MΩ pulldown resistor) 6 mA VOUT_LO STAT, PG output low saturation voltage Sink current = 5 mA 0.5 V IOUT_HI Leakage current V = 32V 1.2 mA 2.1 vertical spacer vertical spacer TYPICAL CHARACTERISTICS Table 1. Table of Graphs FIGURES Power Up (VREF, REGN, PG) Figure 2 Charge Enable and Disable Figure 3 Current Soft Start (CE=HIGH) Figure 4 Continuous Conduction Mode Switching Waveform Figure 6 Discontinuous Conduction Mode Switching Waveform Figure 7 Charge Profile Figure 8 VCC VREF STAT PG Figure 2. Power Up Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24640 7 bq24640 SLUSA44 – MARCH 2010 www.ti.com CE REGN PH IOUT Figure 3. Charge Enable and Disable CE REGN PH IOUT Figure 4. Current Soft Start (CE = HIGH) 8 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24640 bq24640 www.ti.com SLUSA44 – MARCH 2010 PH LODRV CE IOUT Figure 5. Charge Stops on CE LOW PH HIDRV LODRV IL Figure 6. Continuous Conduction Mode Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24640 9 bq24640 SLUSA44 – MARCH 2010 www.ti.com PH LODRV IL Figure 7. Discontinuous Conduction Mode VCC STAT VOUT IOUT Figure 8. Charge Profile 10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24640 bq24640 www.ti.com SLUSA44 – MARCH 2010 BLOCK DIAGRAM VREF bq24640 VOLTAGE REFERENCE VREF 3.3V LDO VCC - SRN+100mV + SLEEP UVLO VCC VCC - VUVLO + SLEEP UVLO VCC CE FBO 1M COMP ERROR AMPLIFIER EAI EAO - + 1V VREG PWM + + VFB BTST CE LEVEL SHIFTER - OUT_OVP 20uA SRP-SRN SRP + SYNCH PH + 20X - V(SRP-SRN) HIDRV PWM CONTROL LOGIC + 5 mV - + - SRN BTST _+ PH 20uA VCC 6V LDO REFRESH - CE 4V CHARGE REGN + LODRV V(SRP-SRN) - 160% X ISET + CHG_OCP GND 8mA CHARGE IC Tj + 145 degC - STAT TSHUT STAT ISET VFB - 104% X VREG + VCC + OUT_OVP STATE MACHINE LOGIC PG PG ACOV VREF VACOV +LTF + TS SUSPEND HTF + - TCO + - Figure 9. Functional Block Diagram Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24640 11 bq24640 SLUSA44 – MARCH 2010 www.ti.com DETAILED DESCRIPTIONS Constant Current VOREG (PROG) ICHARGE (PROG) Constant Voltage Taper Current Time Figure 10. Typical Charging Profile OUTPUT VOLTAGE REGULATION The bq24640 uses a high accuracy voltage regulator for the charging voltage. The charge voltage is programmed via a resistor divider from the output to ground, with the midpoint tied to the VFB pin. The voltage at the VFB pin is regulated to 2.1V, giving the following equation for the regulation voltage: R2 ù é VOUT = 2.1V ´ ê1 + R1 úû ë (1) where R2 is connected from VFB to the output and R1 is connected from VFB to GND. OUTPUT CURRENT REGULATION The ISET input sets the maximum charging current. Output current is sensed by resistor RSR connected between SRP and SRN. The full-scale differential voltage between SRP and SRN is 100mV. Thus, for a 10mΩ sense resistor, the maximum charging current is 10A. The equation for charge current is: VISET ICHARGE = 20 ´ R SR (2) The input voltage range of ISET is between 0 and 2V. The SRP and SRN pins are used to sense voltage across RSR with default value of 10mΩ. However, resistors of other values can also be used. A larger sense resistor will give a larger sense voltage, a higher regulation accuracy; but, at the expense of higher conduction loss. POWER UP The bq24640 uses a SLEEP comparator to determine if the source of power on the VCC pin is a valid supply to charge the capacitor. If the VCC voltage is above the UVLO threshold and greater than the SRN voltage, and all other conditions are met, bq24640 will then start to charge (See Enabling and Disabling Charging). If the SRN voltage is greater than VCC, the bq24640 enters a low quiescent current SLEEP mode to minimize current drain from the capacitor (<15µA). If VCC is below the UVLO threshold, the device is disabled. ENABLE AND DISABLE CHARGING The following conditions have to be valid before charge is enabled: • CE is HIGH • The device is not in Under-Voltage-Lockout (UVLO) mode, and not in VCCLOWV • The device is not in SLEEP mode (i.e., VCC > SRN) • The VCC voltage is lower than the AC over-voltage threshold (VCC < VACOV) • 30ms delay is complete after initial power-up • The REGN LDO and VREF LDO voltages are at the correct levels 12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24640 bq24640 www.ti.com • • SLUSA44 – MARCH 2010 Thermal Shut (TSHUT) is not valid TS fault is not detected One of the following conditions will stop on-going charging: • CE is LOW; • Adapter is removed, causing the device to enter VCCLOWV; • The device is in SLEEP mode (i.e., VCC < SRN); • Adapter is over voltage; • The REGN or VREF LDOs voltage are not valid; • TSHUT IC temperature threshold is reached; • TS voltage goes out of range indicating the temperature is too hot or too cold. AUTOMATIC INTERNAL SOFT-START CHARGER CURRENT The charger automatically soft-starts the charger regulation current to ensure there is no overshoot or stress on the output capacitor. The soft-start consists of stepping-up the charge regulation current into 8 evenly divided steps up to the programmed charge current. Each step lasts around 1.6ms, for a typical rise time of 13ms. No external components are needed for this function. CONVERTER OPERATION The synchronous buck PWM converter uses a fixed frequency voltage mode with feed-forward control scheme. A type III compensation network allows using ceramic capacitors at the output of the converter. The compensation input stage is connected internally between the feedback output (FBO) and the error amplifier input (EAI). The feedback compensation stage is connected between the error amplifier input (EAI) and error amplifier output (EAO). The LC output filter is selected to give a resonant frequency of 12 kHz–17 kHz, where resonant frequency, fo, is given by: 1 ¦o = 2p L o Co (3) An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty-cycle of the converter. The ramp height is 7% of the input adapter voltage making it always directly proportional to the input adapter voltage. This cancels out any loop gain variation due to a change in input voltage, and simplifies the loop compensation. The ramp is offset in order to allow zero percent duty-cycle when the EAO signal is below the ramp. The EAO signal is also allowed to exceed the saw-tooth ramp signal in order to get a 100% duty-cycle PWM request. Internal gate drive logic allows achieving 99.98% duty-cycle while ensuring the N-channel upper device always has enough voltage to stay fully on. If the BTST pin to PH pin voltage falls below 4.2V for more than 3 cycles, then the high-side n-channel power MOSFET is turned off and the low-side n-channel power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the high-side driver returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected to fall low again due to leakage current discharging the BTST capacitor below the 4.2 V, and the reset pulse is issued. The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, output voltage, charge current, and temperature, simplifying output filter design and keeping it out of the audible noise region. SYNCHRONOUS AND NON-SYNCHRONOUS OPERATION The charger operates in synchronous mode when the SRP-SRN voltage is above 5mV (0.5A inductor current for a 10mΩ sense resistor). During synchronous mode, the internal gate drive logic ensures there is break-before-make complimentary switching to prevent shoot-through currents. During the 30ns dead time where both FETs are off, the body-diode of the low-side power MOSFET conducts the inductor current. Having the low-side FET turn-on keeps the power dissipation low, and allows safely charging at high currents. During synchronous mode the inductor current is always flowing and converter operates in continuous conduction mode (CCM), creating a fixed two-pole system. The charger operates in non-synchronous mode when the SRP-SRN voltage is below 5mV (0.5A inductor current on 10mΩ sense resistor). The charger is forced into non-synchronous mode when the average SRP-SRN voltage is lower than 1.25mV (125mA on 10mΩ sense resistor). Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24640 13 bq24640 SLUSA44 – MARCH 2010 www.ti.com During non-synchronous operation, the body-diode of lower-side MOSFET can conduct the positive inductor current after the high-side n-channel power MOSFET turns off. When the load current decreases and the inductor current drops to zero, the body diode will be naturally turned off and the inductor current will become discontinuous. This mode is called Discontinuous Conduction Mode (DCM). During DCM, the low-side n-channel power MOSFET will turn on when the bootstrap capacitor voltage drops below 4.2V, then the low-side power MOSFET will turn off and stay off until the beginning of the next cycle, where the high-side power MOSFET is turned on again. The low-side MOSFET on-time is required to ensure the bootstrap capacitor is always recharged and able to keep the high-side power MOSFET on during the next cycle. At very low currents during non-synchronous operation, there may be a small amount of negative inductor current during the recharge pulse. The charge should be low enough to be absorbed by the input capacitance. Whenever the converter goes into zero percent duty-cycle, the high-side MOSFET does not turn on, and the low-side MOSFET does not turn on (only recharge pulse) either, and there is almost no discharge from the output. During the DCM mode the loop response automatically changes and has a single pole system at which the pole is proportional to the load current, because the converter does not sink current, and only the load provides a current sink. This means at very low currents the loop response is slower, as there is less sinking current available to discharge the output voltage. INPUT OVER VOLTAGE PROTECTION (ACOV) ACOV provides protection to prevent system damage due to high input voltage. Once the adapter voltage reaches the ACOV threshold, charge is disabled. OUTPUT OVER-VOLTAGE PROTECTION The converter will not allow the high-side FET to turn-on until the output voltage goes below 102% of the regulation voltage. This allows one-cycle response to an over-voltage condition – such as occurs when the load is removed. An 8mA current sink from SRP/SRN to GND is on during charge and allows discharging the output capacitors. CYCLE-BY-CYCLE CHARGE OVER-CURRENT PROTECTION The charger has a secondary cycle-to-cycle over-current protection. It monitors the charge current, and prevents the current from exceeding 160% of the programmed charge current. The high-side gate drive turns off when the over-current is detected, and automatically resumes when the current falls below the over-current threshold. THERMAL SHUTDOWN PROTECTION The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the ambient, to keep junctions temperatures low. As added level of protection, the charger converter turns off and self-protects whenever the junction temperature exceeds the TSHUT threshold of 145°C. The charger stays off until the junction temperature falls below 130°C. TEMPERATURE QUALIFICATION The controller continuously monitors load temperature by measuring the voltage between the TS pin and GND. A negative temperature coefficient thermistor (NTC) and an external voltage divider typically develop this voltage. The controller compares this voltage against its internal thresholds to determine if charging is allowed. To initiate a charge cycle, the temperature must be within the V(LTF) to V(HTF) thresholds. If temperature is outside of this range, the controller suspends charge and waits until the temperature is within the V(LTF) to V(HTF) range. During the charge cycle the temperature must be within the V(LTF) to V(TCO) thresholds. If temperature is outside of this range, the controller suspends charge and waits until the temperature is within the V(LTF) to V(HTF) range. The controller suspends charge by turning off the PWM charge FETs. If the TS function is not required, R9 and R10 can be the same value so the voltage on TS is 1.65V with VREF as the reference supply. 14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24640 bq24640 www.ti.com SLUSA44 – MARCH 2010 VREF VREF CHARGE SUSPENDED CHARGE SUSPENDED VLTF VLTFH VLTF VLTFH TEMPERATURE RANGE TO INITIATE CHARGE TEMPERATURE RANGE DURING A CHARGE CYCLE VHTF VTCO CHARGE SUSPENDED CHARGE SUSPENDED GND GND Figure 11. TS Pin, Thermistor Sense Thresholds Assuming a 103AT NTC thermistor is selector, the value RT1 and RT2 can be determined by using the following equations: æ 1 1 ö VVREF ´ RTHCOLD ´ RTHHOT ´ ç ÷ V V TCO ø è LTF RT2 = æV ö æV ö RTHHOT ´ ç VREF - 1÷ - RTHCOLD ´ ç VREF - 1÷ è VLTF ø è VTCO ø (4) VVREF - 1 VLTF RT1 = 1 1 + RT2 RTHCOLD (5) VREF bq24640 RT 1 TS RT 2 RTH 103 AT Figure 12. TS Resistor Network CE (Charge Enable) The CE digital input is used to disable or enable the charge process. A high-level signal on this pin enables charge, provided all the other conditions for charge are met (see Enabling and Disabling Charge). A high to low transition on this pin also resets all timers and fault conditions. There is an internal 1 MΩ pulldown resistor on the CE pin, so if CE is floated the charge will not turn on. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24640 15 bq24640 SLUSA44 – MARCH 2010 www.ti.com PG OUTPUT The open drain PG (power good) output indicates when the VCC voltage is present. The open drain FET turns on whenever bq24640 is not in UVLO mode and not in SLEEP mode (i.e., V(VCC) > V(SRN) and V(VCC) > V(UVLO)). The PG pin can be used to drive an LED or communicate to the host processor. CHARGE STATUS OUTPUTS The open-drain STAT output indicates various charger operations as shown in Table 2. These status pins can be used to drive LEDs or communicate with the host processor. Note that OFF indicates that the open-drain transistor is turned off. Table 2. STAT Pin Definition CHARGE STATE STAT CE high ON Sleep mode OFF Charge Suspend (TS), Input or Output Over-voltage, CE low Blinking Inductor, Capacitor, and Sense Resistor Selection Guidelines The bq24640 provides internal loop compensation. With this scheme, best stability occurs when the LC resonant frequency, fo, is approximately 12kHz–17kHz. Table 3 provides a summary of typical LC components for various charge currents. See INDUCTOR SELECTION section for infomation on controlling ripple current. Table 3. Typical Inductor, Capacitor, and Sense Resistor Values as a Function of Charge Current Charge Current Output Inductor Lo 2A 4A 6A 8A 10A 10 µH 6.8 µH 4.7 µH 3.3 µH 3.3 µH Output Capacitor Co 15 µF 20 µF 30 µF 40 µF 40 µF Sense Resistor 10 mΩ 10 mΩ 10 mΩ 10 mΩ 10 mΩ 16 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24640 bq24640 www.ti.com SLUSA44 – MARCH 2010 Table 4. Component List for Typical System Circuit of Figure 1 PART DESIGNATOR Qty DESCRIPTION Q4, Q5 2 N-channel MOSFET, 30 V, 12 A, PowerPAK 1212-8, Vishay-Siliconix, Sis412DN D1 1 Diode, Dual Schottky, 30 V, 200 mA, SOT23, Fairchild, BAT54C D2 1 Schottky Diode, 40V, 5A, SMC, ON Semiconductor, MBRS540T3 D3, D4 2 LED Diode, Green, 2.1V, 10mΩ, Vishay-Dale, WSL2010R0100F RSR 1 Sense Resistor, 10 mΩ, 1%, 1 W, 2010, Vishay-Dale, WSL2010R0100F L 1 Inductor, 6.8 mH, 5.5A, Vishay-Dale IHLP2525CZ C8, C9, C12, C13 4 Capacitor, Ceramic, 10 mF, 35 V, 20%, X7R C4, C5 2 Capacitor, Ceramic, 1 mF, 16 V, 10%, X7R C7 1 Capacitor, Ceramic, 1 mF, 50 V, 10%, X7R C1, C6, C11 3 Capacitor, Ceramic, 0.1 mF, 16 V, 10%, X7R C2 1 Capacitor, Ceramic, 2.2 mF, 50V, 10%, X7R Cff 1 Capacitor, Ceramic, 22 pF, 35V, 10%, X7R C10 1 Capacitor, Ceramic, 0.1 mF, 35V, 10%, X7R R1 1 Resistor, Chip, 105 kΩ, 1/16W, 0.5% R2 1 Resistor, Chip, 300 kΩ, 1/16W, 0.5% R7 1 Resistor, Chip, 100 kΩ, 1/16W, 0.5% R8 1 Resistor, Chip, 22.1 kΩ, 1/16W, 0.5% R9 1 Resistor, Chip, 9.31 kΩ, 1/16W, 1% R10 1 Resistor, Chip, 430 kΩ, 1/16W, 1% R11 1 Resistor, Chip, 2 Ω, 1W, 5% R13, R14 2 Resistor, Chip, 100 kΩ, 1/16W, 5% R5 1 Resistor, Chip, 100 Ω, 1/16W, 0.5% R6 1 Resistor, Chip, 10 Ω, 0.25W, 5% Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24640 17 bq24640 SLUSA44 – MARCH 2010 www.ti.com APPLICATION INFORMATION INDUCTOR SELECTION The bq24640 has 600kHz switching frequency to allow the use of small inductor and capacitor values. The Inductor saturation current should be higher than the charging current (ICHG) plus half the ripple current (IRIPPLE): ISAT ³ ICHG + (1/2) IRIPPLE (6) The inductor ripple current depends on input voltage (VIN), duty cycle (D = VOUT/VIN), switching frequency (fs) and inductance (L): V ´ D ´ (1 - D) IRIPPLE = IN ¦s ´ L (7) The maximum inductor ripple current happens with D = 0.5 or close to 0.5. Usually inductor ripple is designed in the range of (20–40%) maximum charging current as a trade-off between inductor size and efficiency for a practical design. INPUT CAPACITOR Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at 50% duty cycle, then the worst case capacitor RMS current ICIN occurs where the duty cycle is closest to 50% and can be estimated by the following equation: ICIN = ICHG ´ D × (1 - D) (8) Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage rating of the capacitor must be higher than normal input voltage level. 25V rating or higher capacitor is preferred for 20V input voltage. The 20mF capacitance is suggested for typical of 3–4A charging current. OUTPUT CAPACITOR Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The output capacitor RMS current ICOUT is given: I ICO UT = RIPPLE » 0.29 ´ IRIPPLE 2 ´ 3 (9) The output capacitor voltage ripple can be calculated as follows: 2 æ ö VOUT 1 ΔVO = V ç ÷ 2 ç OUT VIN ÷ø 8LC¦ s è (10) At certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the output filter LC. The bq24640 has internal loop compensator. To get good loop stability, the resonant frequency of the output inductor and output capacitor should be designed between 12 kHz and 17 kHz. The preferred ceramic capacitor is 25V or higher rating, X7R or X5R. POWER MOSFETs SELECTION Two external N-channel MOSFETs are used for a synchronous switching charger. The gate drivers are internally integrated into the IC with 6V of gate drive voltage. 30V or higher voltage rating MOSFETs are preferred for 20V input voltage and 40V or higher rating MOSFETs are preferred for 20–28V input voltage. Figure-of-merit (FOM) is usually used for selecting proper MOSFET based on a tradeoff between the conduction loss and switching loss. For top side MOSFET, FOM is defined as the product of a MOSFET's on-resistance, RDS(ON), and the gate-to-drain charge, QGD. For bottom side MOSFET, FOM is defined as the product of the MOSFET's on-resistance, RDS(ON), and the total gate charge, QG. 18 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24640 bq24640 www.ti.com FOM top = RDS(on) ´ QGD ; SLUSA44 – MARCH 2010 FOM bottom = RDS(on) ´ QG (11) The lower the FOM value, the lower the total power loss. Usually lower RDS(ON) has higher cost with the same package size. The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle (D=VOUT/VIN), charging current (ICHG), MOSFET's on-resistance RDS(ON)), input voltage (VIN), switching frequency (F), turn on time (ton) and turn off time (toff): 1 Ptop = D ´ ICHG2 ´ RDS(on) + ´ VIN ´ ICHG ´ (t on + t off ) ´ fS 2 (12) The first item represents the conduction loss. Usually MOSFET RDS(ON) increases by 50% with 100ºC junction temperature rise. The second term represents the switching loss. The MOSFET turn-on and turn off times are given by: Q Q ton = SW , toff = SW Ion Ioff (13) where QSW is the switching charge, Ion is the turn-on gate driving current and IOFF is the turn-off gate driving current. If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge (QGD) and gate-to-source charge (QGS): 1 QSW = QGD + ´ QGS 2 (14) Gate driving current total can be estimated by REGN voltage (VREGN), MOSFET plateau voltage (VPLT), total turn-on gate resistance (RON) and turn-off gate resistance ROFF) of the gate driver: VREGN - Vplt Vplt Ion = , Ioff = R on R off (15) The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in synchronous continuous conduction mode: Pbottom = (1 - D) ´ ICHG 2 ´ RDS(on) (16) If the SRP-SRN voltage decreases below 5mV (The charger is also forced into non-synchronous mode when the average SRP-SRN voltage is lower than 1.25mV), the low side FET will be turned off for the remainder of the switching cycle to prevent negative inductor current. As a result all the freewheeling current goes through the body-diode of the bottom-side MOSFET. The maximum charging current in non-synchronous mode can be up to 0.9A (0.5A typ) for a 10mΩ charging current sensing resistor considering IC tolerance. Choose the bottom-side MOSFET with either an internal Schottky or body diode capable of carrying the maximum non-synchronous mode charging current. MOSFET gate driver power loss contributes to the dominant losses on controller IC, when the buck converter is switching. Choosing the MOSFET with a small Qg_total will reduce the IC power loss to avoid thermal shutdown. PICLoss_driver = VIN ´ Qg_total ´ fS (17) Where Qg_total is the total gate charge for both upper and lower MOSFET at 6V VREGN. INPUT FILTER DESIGN During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a second order system. The voltage spike at VCC pin may be beyond IC maximum voltage rating and damage IC. The input filter must be carefully designed and tested to prevent over voltage event on VCC pin. There are several methods to damping or limit the over voltage spike during adapter hot plug-in. An electrolytic capacitor with high ESR as an input capacitor can damp the over voltage spike well below the IC maximum pin voltage rating. A high current capability TVS Zener diode can also limit the over voltage level to an IC safe level. However these two solutions may not have low cost or small size. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24640 19 bq24640 SLUSA44 – MARCH 2010 www.ti.com A cost effective and small size solution is shown in Figure 13. The R1 and C1 are composed of a damping RC network to damp the hot plug-in oscillation. As a result the over voltage spike is limited to a safe level. D1 is used for reverse voltage protection for VCC pin. C2 is VCC pin decoupling capacitor and it should be place to VCC pin as close as possible. The R2 and C2 form a damping RC network to further protect the IC from high dv/dt and high voltage spike. C2 value should be less than C1 value so R1 can dominant the equivalent ESR value to get enough damping effect for hot plug-in. R1 and R2 package must be sized enough to handle inrush current power loss according to resistor manufacturer’s datasheet. The filter components value always need to be verified with real application and minor adjustments may need to fit in the real application circuit. D1 Adapter Connector R1 (2010) 2W R2 (1206) 4.7 - 30 W VCC pin C1 2.2 mF C2 0.1 - 1 mF Figure 13. Input Filter PCB LAYOUT The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the components to minimize high frequency current path loop (see Figure 14) is important to prevent electrical and magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout PCB according to this specific order is essential. 1. Place input capacitor as close as possible to switching MOSFET’s supply and ground connections and use shortest copper trace connection. These parts should be placed on the same layer of PCB instead of on different layers and using vias to make this connection. 2. The IC should be placed close to the switching MOSFET’s gate terminals and keep the gate drive signal traces short for a clean MOSFET drive. The IC can be placed on the other side of the PCB of switching MOSFETs. 3. Place inductor input terminal to switching MOSFET’s output terminal as close as possible. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane. 4. The charging current sensing resistor should be placed right next to the inductor output. Route the sense leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop area) and do not route the sense leads through a high-current path (see Figure 14 for Kelvin connection for best current accuracy). Place decoupling capacitor on these traces next to the IC. 5. Place output capacitor next to the sensing resistor output and ground. 6. Output capacitor ground connections need to be tied to the same copper that connects to the input capacitor ground before connecting to system ground. 7. Route analog ground separately from power ground and use single ground connection to tie charger power ground to charger analog ground. Just beneath the IC use analog ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling. Connect analog ground to GND pin. using PowerPAD as the single ground connection point to connect analog ground and power ground together. Or using a 0Ω resistor to tie analog ground to power ground (PowerPAD should tie to analog ground in this case). A star-connection under PowerPAD is highly recommended. 8. It is critical that the exposed PowerPAD on the backside of the IC package be soldered to the PCB ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other layers. 9. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible. 10. All via size and number should be enough for a given current path. 20 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24640 bq24640 www.ti.com SLUSA44 – MARCH 2010 L1 SW R1 V OUT High Frequency V IN Current C1 Path C2 PGND C3 Super Capacitor Figure 14. High Frequency Current Path Charge Current Direction R SNS To Inductor To Capacitor and Output Current Sensing Direction To SRP and SRN pin Figure 15. Sensing Resistor PCB Layout Refer to the EVM design (SLUU410) for the recommended component placement with trace and via locations. For the QFN information, refer to SCBA017 and SLUA271A. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24640 21 PACKAGE OPTION ADDENDUM www.ti.com 9-Apr-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty BQ24640RVAR ACTIVE VQFN RVA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24640RVAT ACTIVE VQFN RVA 16 250 CU NIPDAU Level-2-260C-1 YEAR Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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