HD74LVCZ240A Octal Buffers / Line Drivers with 3–state Outputs ADE-205-229A (Z) 2nd. Edition February 1999 Description The HD74LVCZ240A has eight inverter drivers with three state outputs in a 20 pin package. This device is a inverting buffer and has two active low enables (1G and 2G). Each enable independently controls four buffers. When VCC is between 0 and 1.5 V, the device is in the high impedance state during power up or power down. Low voltage and high speed operation is suitable at battery drive product (note type personal computer) and low power consumption extends the life of a battery for long time operation. Features • VCC = 2.7 to 5.5 V • All inputs VIH (Max) = 5.5 V (@VCC = 0 to 5.5 V) • All outputs VO (Max) = 5.5 V (@VCC = 0 V or output off state) • Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) • Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) • High impedance state during power up and power down • Power off disables outputs, permitting live insertion • High output current ±24 mA (@V CC = 3.0 to 5.5 V) HD74LVCZ240A Function Table Output Y Inputs G A H X Z L H L L L H H : High level L : Low level X : Immaterial Z : High impedance Pin Arrangement 20 VCC 1G 1 1A1 2 19 2G 2Y4 3 18 1Y1 1A2 4 17 2A4 2Y3 5 16 1Y2 1A3 6 15 2A3 2Y2 7 14 1Y3 1A4 8 13 2A2 2Y1 9 12 1Y4 GND 10 11 2A1 (Top view) 2 HD74LVCZ240A Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage VCC –0.5 to 7.0 V Input voltage VI –0.5 to 7.0 V Output voltage VO –0.5 to 7.0 V –0.5 to VCC+0.5 Conditions Output “Z” or VCC : OFF Output “H” or “L” Input diode current I IK –50 mA VI < 0 Output diode current I OK –50 mA VO < 0 Output current IO ±50 mA VCC, GND current I CC or IGND ±100 mA Storage temperature Tstg –65 to 150 °C Note: The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Symbol Ratings Unit Conditions Supply voltage VCC 2.7 to 5.5 V At operation Input voltage VI 0 to 5.5 V Output voltage VO 0 to 5.5 V 0 to V CC Output current I OH –12 –24 I OL Output “H” or “L” mA *1 VCC = 2.7 V *1 VCC = 3.0 to 5.5 V Input rise / fall time t r, t f 0 to 6 ns / V Operating temperature Ta –40 to +85 °C Note: VCC = 2.7 V VCC = 3.0 to 5.5 V 12 24 Output “Z” or VCC : OFF 1. Duty cycle ≤ 50% 3 HD74LVCZ240A Logic Diagram 1G 1A1 1A2 1A3 1A4 4 1 2G 2 18 4 16 6 14 8 12 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 19 11 9 13 7 15 5 17 3 2Y1 2Y2 2Y3 2Y4 HD74LVCZ240A Electrical Characteristics (Ta = –40 to 85°C) Item Symbol VCC (V) Input voltage VIH VIL Output voltage VOH Min Typ Max Unit Test Conditions — — V 4.5 to 5.5 VCC×0.7 — — 2.7 to 3.6 — — 0.8 4.5 to 5.5 — — VCC×0.3 2.7 to 3.6 2.0 — 2.7 2.2 — — 3.0 2.4 — — 3.0 2.2 — — 4.5 3.8 — — 2.7 to 5.5 — — 0.2 I OL = 100 µA 2.7 — — 0.4 I OL = 12 mA 3.0 — — 0.55 I OL = 24 mA 4.5 — — 0.55 0 to 5.5 — — ±5 µA VIN = 0 to 5.5 V 2.7 to 5.5 — — ±5 µA VOUT = 0 to 5.5 V I OZPU 0 to 1.5 — — ±5 VOUT = 0.5 to 5.5 V, I OZPD 1.5 to 0 — — ±5 Output enable = don’t care Output leak current I OFF 0 — — ±5 µA VIN or VO = 5.5 V Quiescent supply I CC 2.7 to 3.6 — — 225 µA VIN = 3.6 to 5.5 V *1 , I O = 0 2.7 to 5.5 — — 350 VIN = VCC or GND ∆I CC 2.7 to 3.6 — — 500 VIN = one input at (VCC–0.6) V, other inputs at V CC or GND Input capacitance CIN 3.3 — 3.4 — pF VIN = VCC or GND Output capacitance CO 3.3 — 7.5 — pF VOUT = VCC or GND VOL Input current I IN Off state output current I OZ current Note: V I OH = –100 µA 2.7 to 5.5 VCC–0.2 — I OH = –12 mA I OH = –24 mA 1. This applies in the disabled state only. 5 HD74LVCZ240A Switching Characteristics (Ta = –40 to 85°C) Item Symbol VCC (V) Min Typ Max Unit FROM (Input) TO (Output) Propagation delay time t PLH 2.7 — — 7.5 ns A Y t PHL 3.3±0.3 1.3 — 6.5 5.0±0.5 — — 5.0 t ZH 2.7 — 9.0 ns G Y t ZL 3.3±0.3 1.1 — 8.0 5.0±0.5 — — 6.5 t HZ 2.7 — 8.0 ns G Y t LZ 3.3±0.3 1.4 — 7.0 5.0±0.5 — — 6.0 t OSLH 2.7 — — — t OSHL 3.3±0.3 — — 1.0 5.0±0.5 — — 1.0 Output enable time Output disable time Between output pin skew *1 — — ns Note : 1. This parameter is characterized but not tested. t OSLH = |tPLHm–t PLHn |, tOSHL = |tPHLm–t PHLn | Test Circuit VCC VCC Output Input Pulse generator Zout = 50 Ω See Function Table 1G, 2G 500 Ω 1Y1 to 2Y4 1A1 to 2A4 C L= 50 pF 450 Ω Note: 1. C L includes probe and jig capacitance. OPEN See under table *1 GND 50 Ω Scope Symbol 6 S1 S1 Vcc=2.7V, 3.3±0.3V Vcc=5.0±0.5V t PLH / t PHL OPEN OPEN t ZH/ t HZ t ZL / t LZ GND 6V GND 2×VCC HD74LVCZ240A • Waveforms – 1 tf tr VIH 90 % Vref 90 % Vref Input A 10 % t PLH 10 % GND t PHL VOH Output Y Vref Vref VOL • Waveforms – 2 tf Input G tr 90 % Vref VIH 90 % Vref 10 % t ZL 10 % GND t LZ ≈VOH1 Waveform – A Vref t ZH Waveform – B Vref VOL + 0.3 V VOL t HZ VOH VOH – 0.3 V ≈VOL1 TEST VIH Vcc=2.7V, 3.3±0.3V Vcc=5.0±0.5V 2.7 V 1.5 V VOH1 3V VCC 50%VCC VCC VOL1 GND GND Vref Notes: 1. Input waveform : PRR = 10 MHz, duty cycle 50%, t r = 2.5 ns, t f = 2.5 ns 2. Waveform – A shows input conditions such that the output is “L” level when enabled by the output control. 3. Waveform – B shows input conditions such that the output is “H” level when enabled by the output control. 7 HD74LVCZ240A Power up / down Characteristics 4.0 Ta = 25°C Output enable = “L” VOUT (V) 3.0 2.0 Disable area Enable area 1.0 0 0 1.0 2.0 VCC (V) 8 3.0 4.0 HD74LVCZ240A Package Dimensions Unit : mm 12.6 13 Max 11 1 10 1.27 0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0.80 Max 0.22 ± 0.05 0.20 ± 0.04 2.20 Max 5.5 20 0.20 7.80 +– 0.30 1.15 0° – 8° 0.70 ± 0.20 0.15 0.12 M Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-20DA — Conforms 0.31 g 9 HD74LVCZ240A 6.50 6.80 Max 11 1 10 4.40 20 0.65 0.22 +0.08 –0.07 0.20 ± 0.06 1.0 0.13 M 6.40 ± 0.20 Dimension including the plating thickness Base material dimension 10 0.07 +0.03 –0.04 0.10 0.17 ± 0.05 0.15 ± 0.04 1.10 Max 0.65 Max 0° – 8° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-20DA — — 0.07 g Cautions 1. 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