HITACHI HM62V8512C

HM62V8512C Series
4 M SRAM (512-kword × 8-bit)
ADE-203-1210A (Z)
Rev. 1.0
Jan. 31, 2001
Description
The Hitachi HM62V8512C is a 4-Mbit static RAM organized 512-kword × 8-bit. It realizes higher density,
higher performance and low power consumption by employing CMOS process technology (6-transistor
memory cell). The device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II is
available for high density mounting. The HM62V8512C is suitable for battery backup system.
Features
• Single 3.0 V supply: 2.7 V to 3.6 V
• Access time: 55/70 ns (max)
• Power dissipation
 Active: 6.0 mW/MHz (typ)
 Standby: 2.4 µW (typ)
• Completely static memory. No clock or timing strobe required
• Equal access and cycle times
• Common data input and output: Three state output
• Directly LV-TTL compatible: All inputs
• Battery backup operation
HM62V8512C Series
Ordering Information
Type No.
Access time
Package
HM62V8512CLFP-5
HM62V8512CLFP-7
55 ns
70 ns
525-mil 32-pin plastic SOP (FP-32D)
HM62V8512CLFP-5SL
HM62V8512CLFP-7SL
55 ns
70 ns
HM62V8512CLTT-5
HM62V8512CLTT-7
55 ns
70 ns
HM62V8512CLTT-5SL
HM62V8512CLTT-7SL
55 ns
70 ns
HM62V8512CLRR-5
HM62V8512CLRR-7
55 ns
70 ns
HM62V8512CLRR-5SL
HM62V8512CLRR-7SL
55 ns
70 ns
2
400-mil 32-pin plastic TSOP II (TTP-32D)
400-mil 32-pin plastic TSOP II reverse (TTP-32DR)
HM62V8512C Series
Pin Arrangement
32-pin SOP
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32-pin TSOP
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
(Top view)
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
(Top view)
32-pin TSOP (reverse)
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
(Top view)
Pin Description
Pin name
Function
A0 to A18
Address input
I/O0 to I/O7
Data input/output
CS
Chip select
OE
Output enable
WE
Write enable
VCC
Power supply
VSS
Ground
3
HM62V8512C Series
Block Diagram
LSB
MSB
A11
A9
A8
A15
A18
A10
A13
A17
A16
A14
A12
V CC
V SS
Row
Decoder
I/O0
•
•
•
•
•
Memory Matrix
2,048 × 2,048
•
•
Column I/O
Input
Data
Control
Column Decoder
I/O7
LSB A3 A2A1A0 A4 A5 A6 A7 MSB
••
CS
WE
OE
4
Timing Pulse Generator
Read/Write Control
•
•
HM62V8512C Series
Function Table
WE
CS
OE
Mode
VCC current
Dout pin
Ref. cycle
×
H
×
Not selected
I SB , I SB1
High-Z
—
H
L
H
Output disable
I CC
High-Z
—
H
L
L
Read
I CC
Dout
Read cycle
L
L
H
Write
I CC
Din
Write cycle (1)
L
L
L
Write
I CC
Din
Write cycle (2)
Note: ×: H or L
Absolute Maximum Ratings
Parameter
Symbol
Value
Power supply voltage
VCC
–0.5 to +4.6
1
Unit
V
2
Voltage on any pin relative to V SS
VT
–0.5* to V CC + 0.5*
V
Power dissipation
PT
1.0
W
Operating temperature
Topr
–20 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
Storage temperature under bias
Tbias
–20 to +85
°C
Notes: 1. VT min: –3.0 V for pulse half-width ≤ 30 ns.
2. Maximum voltage is 4.6 V.
Recommended DC Operating Conditions (Ta = –20 to +70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VCC
2.7
3.0
3.6
V
VSS
0
0
0
V
VIH
2.0
—
VCC + 0.3
V
—
0.8
V
Input high voltage
Input low voltage
Note:
VIL
1
–0.3*
1. VIL min: –3.0 V for pulse half-width ≤ 30 ns.
5
HM62V8512C Series
DC Characteristics
Parameter
Symbol Min
Typ*1
Max
Unit Test conditions
Input leakage current
|ILI|
—
—
1
µA
Vin = VSS to V CC
Output leakage current
|ILO |
—
—
1
µA
CS = VIH or OE = VIH or
WE = VIL, VI/O = VSS to V CC
Operating power
supply current: DC
I CC
—
5
10
mA
CS = VIL,
others = VIH/VIL, I I/O = 0 mA
HM62V8512C-5 I CC1
—
18
35
mA
Min cycle, duty = 100%
CS = VIL, others = VIH/VIL
I I/O = 0 mA
HM62V8512C-7 I CC1
—
15
30
mA
Operating power
supply current
I CC2
—
2
10
mA
Cycle time = 1 µs,
duty = 100%
I I/O = 0 mA, CS ≤ 0.2 V
VIH ≥ V CC – 0.2 V,
VIL ≤ 0.2 V
Standby power supply
current: DC
I SB
—
0.1
0.3
mA
CS = VIH
Standby power supply
current (1): DC
I SB1
—
0.8*2
20* 2
µA
Vin ≥ 0 V,
CS ≥ V CC – 0.2 V
—
0.8*3
10* 3
µA
—
—
0.4
V
I OL = 2.1 mA
—
—
0.2
V
I OL = 100 µA
VCC – 0.2 —
—
V
I OH = –100 µA
2.4
—
V
I OH = –1.0 mA
Operating
power supply
current
Output low voltage
VOL
Output high voltage
VOH
—
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
2. This characteristics is guaranteed only for L version.
3. This characteristics is guaranteed only for L-SL version.
Capacitance (Ta = +25°C, f = 1 MHz)
Parameter
1
Input capacitance*
Input/output capacitance*
Note:
6
1
Symbol
Typ
Max
Unit
Test conditions
Cin
—
8
pF
Vin = 0 V
CI/O
—
10
pF
VI/O = 0 V
1. This parameter is sampled and not 100% tested.
HM62V8512C Series
AC Characteristics (Ta = –20 to +70°C, VCC = 2.7 V to 3.6 V, unless otherwise noted.)
Test Conditions
•
•
•
•
Input pulse levels: 0.4 V to 2.4 V
Input rise and fall time: 5 ns
Input timing reference levels: 1.4 V
Output timing reference level: 1.4 V/1.4 V(HM62V8512C-5)
0.8 V/2.0 V(HM62V8512C-7)
• Output load: See figure (Including scope & jig)
500 Ω
Dout
1.4 V
50 pF
Read Cycle
HM62V8512C
-5
-7
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Read cycle time
t RC
55
—
70
—
ns
Address access time
t AA
—
55
—
70
ns
Chip select access time
t CO
—
55
—
70
ns
Output enable to output valid
t OE
—
30
—
35
ns
Chip selection to output in low-Z
t LZ
10
—
10
—
ns
2
Output enable to output in low-Z
t OLZ
5
—
5
—
ns
2
Chip deselection to output in high-Z
t HZ
0
20
0
30
ns
1, 2
Output disable to output in high-Z
t OHZ
0
20
0
30
ns
1, 2
Output hold from address change
t OH
10
—
10
—
ns
7
HM62V8512C Series
Write Cycle
HM62V8512C
-5
-7
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Write cycle time
t WC
55
—
70
—
ns
Chip selection to end of write
t CW
50
—
60
—
ns
4
Address setup time
t AS
0
—
0
—
ns
5
Address valid to end of write
t AW
50
—
60
—
ns
Write pulse width
t WP
40
—
50
—
ns
3, 12
Write recovery time
t WR
0
—
0
—
ns
6
WE to output in high-Z
t WHZ
0
20
0
30
ns
1, 2, 7
Data to write time overlap
t DW
25
—
30
—
ns
Data hold from write time
t DH
0
—
0
—
ns
Output active from output in high-Z
t OW
5
—
5
—
ns
2
Output disable to output in high-Z
t OHZ
0
20
0
30
ns
1, 2, 7
Notes: 1. t HZ , t OHZ and t WHZ are defined as the time at which the outputs achieve the open circuit conditions and
are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (tWP) of a low CS and a low WE. A write begins at the later
transition of CS going low or WE going low. A write ends at the earlier transition of CS going high
or WE going high. tWP is measured from the beginning of write to the end of write.
4. t CW is measured from CS going low to the end of write.
5. t AS is measured from the address valid to the beginning of write.
6. t WR is measured from the earlier of WE or CS going high to the end of write cycle.
7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to
the outputs must not be applied.
8. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition,
the output remain in a high impedance state.
9. Dout is the same phase of the write data of this write cycle.
10. Dout is the read data of next address.
11. If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of the
opposite phase to the outputs must not be applied to them.
12. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of
data bus contention. t WP ≥ tDW min + tWHZ max
8
HM62V8512C Series
Timing Waveforms
Read Timing Waveform (WE = VIH)
tRC
Address
tAA
tCO
CS
tLZ
tHZ
tOE
tOLZ
OE
tOHZ
Dout
Valid Data
tOH
9
HM62V8512C Series
Write Timing Waveform (1) (OE Clock)
tWC
Address
tAW
tWR
OE
tCW
CS
*8
tWP
tAS
WE
tOHZ
Dout
tDW
Din
10
Valid Data
tDH
HM62V8512C Series
Write Timing Waveform (2) (OE Low Fixed)
tWC
Address
tCW
tWR
CS
*8
tAW
tWP
WE
tOH
tAS
tOW
tWHZ
*9
*10
Dout
tDW
tDH
*11
Din
Valid Data
11
HM62V8512C Series
Low VCC Data Retention Characteristics (Ta = –20 to +70°C)
Parameter
Symbol
Min
Typ
VCC for data retention
VDR
2
—
Data retention current
I CCDR
Chip deselect to data retention time
Operation recovery time
t CDR
tR
4
Max
Unit
Test conditions*3
—
CS ≥ V CC – 0.2 V, Vin ≥ 0 V
µA
VCC = 3.0 V, Vin ≥ 0 V
CS ≥ V CC – 0.2 V
—
0.8*
—
0.8*4
10* 2
µA
—
—
ns
—
—
ns
0
t RC*
5
20*
V
1
See retention waveform
Notes: 1. For L-version and 10 µA (max.) at Ta = –20 to +40°C.
2. For L-SL-version and 5 µA (max.) at Ta = –20 to +40°C.
3. CS controls address buffer, WE buffer, OE buffer, and Din buffer. In data retention mode, Vin
levels (address, WE, OE, I/O) can be in the high impedance state.
4. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
5. t RC = read cycle time.
Low V CC Data Retention Timing Waveform (CS Controlled)
t CDR
Data retention mode
V CC
2.7 V
V DR
2.0 V
CS
0V
12
CS ≥ VCC – 0.2 V
tR
HM62V8512C Series
Package Dimensions
HM62V8512CLFP Series (FP-32D)
Unit: mm
20.45
20.95 Max
17
11.30
32
1
1.27
*0.40 ± 0.08
0.38 ± 0.06
0.10
0.15 M
*Dimension including the plating thickness
Base material dimension
0.12
0.15 +– 0.10
1.00 Max
*0.22 ± 0.05
0.20 ± 0.04
3.00 Max
16
14.14 ± 0.30
1.42
0° – 8°
0.80 ± 0.20
Hitachi Code
JEDEC
EIAJ
Mass (reference value)
FP-32D
Conforms
—
1.3 g
13
HM62V8512C Series
Package Dimensions (cont.)
HM62V8512CLTT Series (TTP-32D)
Unit: mm
20.95
21.35 Max
17
10.16
32
1.27
*0.42 ± 0.08
0.40 ± 0.06
0.21
16
M
0.80
11.76 ± 0.20
0.10
*Dimension including the plating thickness
Base material dimension
14
*0.17 ± 0.05
0.125 ± 0.04
1.20 Max
1.15 Max
0.13 ± 0.05
1
0° – 5° 0.50 ± 0.10
Hitachi Code
JEDEC
EIAJ
Mass (reference value)
TTP-32D
Conforms
—
0.51 g
HM62V8512C Series
Package Dimensions (cont.)
HM62V8512CLRR Series (TTP-32DR)
Unit: mm
20.95
21.35 Max
16
10.16
1
1.27
*0.42 ± 0.08
0.40 ± 0.06
0.21
17
M
0.80
11.76 ± 0.20
0.10
*Dimension including the plating thickness
Base material dimension
*0.17 ± 0.05
0.125 ± 0.04
1.20 Max
1.15 Max
0.13 ± 0.05
32
0° – 5° 0.50 ± 0.10
Hitachi Code
JEDEC
EIAJ
Mass (reference value)
TTP-32DR
Conforms
—
0.51 g
15
HM62V8512C Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
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Copyright © Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.
Colophon 2.0
16