TPS7A49xx www.ti.com SBVS121A – AUGUST 2010 – REVISED SEPTEMBER 2010 +36V, +150mA, Ultralow-Noise, Positive LINEAR REGULATOR FEATURES DESCRIPTION • • The TPS7A49xx series of devices are positive, high-voltage (+36V), ultralow noise (15.4mVRMS, 72dB PSRR) linear regulators capable of sourcing a load of 150mA. 1 23 • • • • • • • • • Input Voltage Range: +3V to +36V Noise: – 12.7mVRMS (20Hz to 20kHz) – 15.4mVRMS (10Hz to 100kHz) Power-Supply Ripple Rejection: – 72dB (120Hz) – ≥ 52dB (10Hz to 400kHz) Adjustable Output: +1.194V to +33V Output Current: 150mA Dropout Voltage: 260mV at 100mA Stable with Ceramic Capacitors ≥ 2.2mF CMOS Logic-Level-Compatible Enable Pin Built-In, Fixed, Current-Limit and Thermal Shutdown Protection Available in High Thermal Performance MSOP-8 PowerPAD™ Package Operating Tempature Range: –40°C to +125°C APPLICATIONS • • • • • • • Supply Rails for Op Amps, DACs, ADCs, and Other High-Precision Analog Circuitry Audio Post DC/DC Converter Regulation and Ripple Filtering Test and Measurement RX, TX, and PA Circuitry Industrial Instrumention Base Stations and Telecom Infrastrucure These linear regulators include a CMOS logic-level-compatible enable pin and capacitor-programmable soft-start function that allows for customized power-management schemes. Other features available include built-in current limit and thermal shutdown protection to safeguard the device and system during fault conditions. The TPS7A49xx family is designed using bipolar technology, and is ideal for high-accuracy, high-precision instrumentation applications where clean voltage rails are critical to maximize system performance. This design makes it an excellent choice to power operational amplifiers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and other high-performance analog circuitry. In addition, the TPS7A49xx family of linear regulators is suitable for post dc/dc converter regulation. By filtering out the output voltage ripple inherent to dc/dc switching conversion, maximum system performance is provided in sensitive instrumentation, test and measurement, audio, and RF applications. For applications where both positive and negative high-performance rails are required, consider TI’s TPS7A30xx family of negative high-voltage, ultralow-noise linear regulators as well. Typical Application DGN PACKAGE 3mm ´ 5mm MSOP-8 PowerPAD (TOP VIEW) OUT FB NC GND 1 2 3 4 8 7 6 5 IN DNC NR/SS EN +18V IN OUT +15V TPS7A49 -18V EN GND IN OUT -15V TPS7A30 EN GND EVM Post DC/DC Converter Regulation for High-Performace Analog Circuitry 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated TPS7A49xx SBVS121A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT VOUT XX is nominal output voltage (01 = Adjustable). (2) YYY is package designator. Z is package quantity. TPS7A49xx yyy z (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder on www.ti.com. For fixed -1.2V operation, tie FB to OUT. (2) ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). VALUE Voltage Current MAX UNIT IN pin to GND pin –0.3 +36 V OUT pin to GND pin –0.3 +33 V OUT pin to IN pin –36 +0.3 V FB pin to GND pin –0.3 +2 V FB pin to IN pin –36 +0.3 V EN pin to IN pin –36 0.3 EN pin to GND pin –0.3 +36 V NR/SS pin to IN pin –36 +0.3 V NR/SS pin to GND pin –0.3 +2 V Peak output Temperature Electrostatic discharge rating (1) MIN Internally limited Operating virtual junction, TJ –40 +125 °C Storage, Tstg –65 +150 °C Human body model (HBM) 500 V Charged device model (CDM) 500 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability. THERMAL INFORMATION TPS7A49xx THERMAL METRIC (1) DGN UNITS 8 PINS qJA Junction-to-ambient thermal resistance 55.09 qJC(top) Junction-to-case(top) thermal resistance 8.47 qJB Junction-to-board thermal resistance yJT Junction-to-top characterization parameter 0.36 yJB Junction-to-board characterization parameter 14.6 qJC(bottom) Junction-to-case(bottom) thermal resistance — (1) — °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. DISSIPATION RATINGS (1) 2 BOARD PACKAGE RqJA RqJC DERATING FACTOR ABOVE TA = +25°C TA ≤ +25°C POWER RATING TA = +70°C POWER RATING TA = +85°C POWER RATING High-K (1) DGN 55.9°C/W 8.47°C/W 16.6mW/°C 1.83W 1.08W 0.833W The JEDEC High-K (2s2p) board design used to derive this data was a 3-inch x 3-inch multilayer board with 2-ounce internal power and ground planes and 2-ounce copper traces on top and bottom of the board. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated TPS7A49xx www.ti.com SBVS121A – AUGUST 2010 – REVISED SEPTEMBER 2010 ELECTRICAL CHARACTERISTICS At TJ = –40°C to +125°C, VIN = VOUT(NOM) + 1.0V or VIN = 3.0V (whichever is greater), VEN = VIN, IOUT = 1mA, CIN = 2.2mF, COUT = 2.2mF, CNR/SS = 0nF, and the FB pin tied to OUT, unless otherwise noted. TPS7A49xx PARAMETER TEST CONDITIONS MIN TYP MAX 35 V 1.194 1.212 V VIN Input voltage range VREF Internal reference TJ = +25°C, VNR/SS = VREF Output voltage range (1) VIN ≥ VOUT(NOM) + 1.0V VREF 33.0 V Nominal accuracy TJ = +25°C, VIN = VOUT(NOM) + 0.5V –1.5 +1.5 %VOUT Overall accuracy VOUT(NOM) + 1.0V ≤ VIN ≤ 35V 1mA ≤ IOUT ≤ 150mA –2.5 +2.5 %VOUT DVOUT(DVIN) VOUT(NOM) Line regulation TJ = +25°C, VOUT(NOM) + 1.0V ≤ VIN ≤ 35V 0.11 %VOUT DVOUT(DIOUT) VOUT(NOM) Load regulation TJ = +25°C, 1mA ≤ IOUT ≤ 150mA 0.04 %VOUT VDO Dropout voltage VIN = 95% VOUT(NOM), IOUT = 100mA 260 VIN = 95% VOUT(NOM), IOUT = 150mA 333 600 mV ILIM Current limit 309 500 mA 61 100 mA VOUT VOUT = 90% VOUT(NOM) Ground current ISHDN Shutdown supply current Feedback current 1.176 220 IOUT = 0mA IGND I FB 3.0 UNIT mV IOUT = 100mA 800 VEN = +0.4V 0.8 3.0 (2) VEN = VIN = VOUT(NOM) + 1.0V mA mA 3 100 nA 0.02 1.0 mA 0.2 1.0 mA IEN Enable current VEN_HI Enable high-level voltage +2.1 VIN V VEN_LO Enable low- level voltage 0 +0.4 V VNOISE Output noise voltage PSRR Power-supply rejection ratio TSD Thermal shutdown temperature TJ Operating junction temperature range (1) (2) (3) VEN = VIN = +35V VIN = +3V, VOUT(NOM) = VREF, COUT = 10mF, CNR/SS = 10nF, BW = 10Hz to 100kHz 15.4 mVRMS VIN = +6.2V, VOUT(NOM) = +5V, COUT = 10mF, CNR/SS = CBYP (3) = 10nF, BW = 10Hz to 100kHz 21.15 mVRMS VIN = +6.2V, VOUT(NOM) = +5V, COUT = 10mF, CNR/SS = CBYP (3) = 10nF, f = 120Hz 72 dB Shutdown, temperature increasing +170 °C Reset, temperature decreasing +150 °C –40 +125 °C To ensure stability at no load conditions, a current from the feedback resistive network equal to or greater than 5mA is required. IFB > 0 flows out of the device. CBYP refers to a bypass capacitor connected to the FB and OUT pins. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS7A49xx SBVS121A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com DEVICE INFORMATION FUNCTIONAL BLOCK DIAGRAM OUT IN Pass Device UVLO Thermal Shutdown Current Limit FB Error Amp Enable EN VREF NR/SS GND TYPICAL APPLICATION CIRCUIT VIN EN VOUT OUT IN CIN 10mF CBYP 10nF TPS7A4901 R1 FB R2 CNR/SS 10nF NR/SS GND Where: COUT 10mF VOUT ³ 5mA, and R1 + R2 R1 = R2 VOUT -1 VREF Maximize PSRR Performance and Minimize RMS Noise 4 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated TPS7A49xx www.ti.com SBVS121A – AUGUST 2010 – REVISED SEPTEMBER 2010 PIN CONFIGURATION DGN PACKAGE MSOP-8 (TOP VIEW) OUT FB NC GND 1 2 3 4 8 7 6 5 IN DNC NR/SS EN PIN DESCRIPTIONS TPS7A49xx NAME NO. OUT 1 Regulator output. A capacitor ≥ 2.2mF must be tied from this pin to ground to assure stability. DESCRIPTION FB 2 This pin is the input to the control-loop error amplifier. It is used to set the output voltage of the device. NC 3 Not internally connected. This pin may either be left open or tied to GND. GND 4 Ground EN 5 This pin turns the regulator on or off. If VEN ≥ VEN_HI, the regulator is enabled. If VEN_LO ≥ VEN, the regulator is disabled. The EN pin can be connected to IN, if not used. VEN ≤ VIN. NR/SS 6 Noise reduction pin. Connecting an external capacitor to this pin bypasses noise generated by the internal bandgap. This capacitor allows RMS noise to be reduced to very low levels and also controls the soft-start function. DNC 7 DO NOT CONNECT. Do not route this pin to any electrical net, not even GND or IN. IN 8 Input supply PowerPAD Must either be left open or tied to ground. Solder to printed circuit board (PCB) plane to enhance thermal performance. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5 TPS7A49xx SBVS121A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS At TJ = –40°C to +125°C, VIN = VOUT(NOM) + 1.0V or VIN = 3.0V (whichever is greater), VEN = VIN, IOUT = 1mA, CIN = 2.2mF, COUT = 2.2mF, CNR/SS = 0nF, and the FB pin tied to OUT, unless otherwise noted. FEEDBACK VOLTAGE vs INPUT VOLTAGE FEEDBACK CURRENT vs TEMPERATURE 1.205 +125°C +105°C +85°C +25°C -40°C 90 80 70 IFB (nA) 1.2 VFB (V) 100 1.195 60 50 40 30 1.19 20 10 1.185 0 0 5 10 15 20 VIN (V) 25 30 35 40 -40 -25 -10 5 20 35 50 65 Temperature (°C) Figure 1. 95 GROUND CURRENT vs INPUT VOLTAGE GROUND CURRENT vs INPUT VOLTAGE 1200 0mA 10mA 50mA 100mA 150mA 2000 TJ = +25°C 1000 800 IGND (mA) 1500 1000 600 +125°C +105°C +85°C +25°C -40°C 400 500 200 IOUT = 100mA 0 0 0 5 10 15 20 VIN (V) 25 30 35 40 0 5 10 15 Figure 3. 20 VIN (V) 25 30 35 40 Figure 4. GROUND CURRENT vs OUTPUT CURRENT ENABLE CURRENT vs ENABLE VOLTAGE 2500 100 +125°C +105°C +85°C +25°C -40°C 2000 1500 1000 +125°C +105°C +85°C +25°C -40°C 90 80 70 IEN (nA) IGND (mA) 110 125 Figure 2. 2500 IGND (mA) 80 60 50 40 30 500 20 10 0 0 0 15 30 45 60 75 90 IOUT (mA) Figure 5. 6 Submit Documentation Feedback 105 120 135 150 0 5 10 15 20 VEN (V) 25 30 35 40 Figure 6. Copyright © 2010, Texas Instruments Incorporated TPS7A49xx www.ti.com SBVS121A – AUGUST 2010 – REVISED SEPTEMBER 2010 TYPICAL CHARACTERISTICS (continued) At TJ = –40°C to +125°C, VIN = VOUT(NOM) + 1.0V or VIN = 3.0V (whichever is greater), VEN = VIN, IOUT = 1mA, CIN = 2.2mF, COUT = 2.2mF, CNR/SS = 0nF, and the FB pin tied to OUT, unless otherwise noted. QUIESCENT CURRENT vs INPUT VOLTAGE SHUTDOWN CURRENT vs INPUT VOLTAGE 100 3.5 90 +125°C +105°C +85°C +25°C -40°C 3 80 2.5 ISHDN (mA) IQ (mA) 70 60 50 40 +125°C +105°C +85°C +25°C -40°C 30 20 IOUT = 0mA 10 0 0 5 10 15 20 VIN (V) 25 30 35 2 1.5 1 0.5 VEN = 0.4V 0 40 0 5 10 Figure 7. 20 VIN (V) 25 30 35 40 Figure 8. DROPOUT VOLTAGE vs OUTPUT CURRENT DROPOUT VOLTAGE vs TEMPERATURE 450 500 400 450 350 400 350 VDO (mV) 300 VDO (mV) 15 250 200 +125°C +105°C +85°C +25°C -40°C 150 100 50 10mA 50mA 100mA 150mA 300 250 200 150 100 50 0 0 0 15 30 45 105 120 135 150 60 75 90 IOUT (mA) -40 -25 -10 5 Figure 9. 95 110 125 CURRENT LIMIT vs TEMPERATURE 500 VOUT = 90% VOUT(NOM) 400 80 Figure 10. CURRENT LIMIT vs INPUT VOLTAGE 450 20 35 50 65 Temperature (°C) VOUT = 90% VOUT(NOM) 450 350 400 ILIM (mA) ILIM (mA) 300 250 200 +125°C +105°C +85°C +25°C -40°C 150 100 50 350 300 250 0 200 0 5 10 15 20 VIN (V) Figure 11. Copyright © 2010, Texas Instruments Incorporated 25 30 35 40 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 Figure 12. Submit Documentation Feedback 7 TPS7A49xx SBVS121A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = –40°C to +125°C, VIN = VOUT(NOM) + 1.0V or VIN = 3.0V (whichever is greater), VEN = VIN, IOUT = 1mA, CIN = 2.2mF, COUT = 2.2mF, CNR/SS = 0nF, and the FB pin tied to OUT, unless otherwise noted. ENABLE THRESHOLD VOLTAGE vs TEMPERATURE POWER-SUPPLY REJECTION RATIO vs COUT 90 2.5 80 2 COUT = 10mF 70 ON PSRR (dB) VEN (V) 60 1.5 OFF 1 50 40 30 20 0.5 10 COUT = 2.2mF VOUT = 5V VIN = 6.2V IOUT = 150mA CNR/SS = 10nF CBYP = 10nF 0 0 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 10 110 125 100 1k Figure 13. LINE REGULATION POWER-SUPPLY REJECTION RATIO vs CNR/SS +125°C +105°C +85°C +25°C -40°C 0.4 0.2 80 CNR/SS = 10nF 70 60 PSRR (dB) 0.6 VOUT(NOM) (%) 10M 90 0.8 0 -0.2 50 40 30 -0.4 -0.6 20 -0.8 10 -1 VOUT = 1.2V VIN = 3.2V IOUT = 150mA COUT = 10mF CBYP = 0nF CNR/SS = 0nF 0 0 5 10 15 20 VIN (V) 25 30 35 40 10 100 1k Figure 15. 10k 100k Frequency (Hz) 1M 10M Figure 16. LOAD REGULATION POWER-SUPPLY REJECTION RATIO vs CBYP 1 90 0.6 0.4 0.2 0 -0.2 80 CBYP = 10nF 70 60 PSRR (dB) +125°C +105°C +85°C +25°C -40°C 0.8 VOUT(NOM) (%) 1M Figure 14. 1 50 40 30 -0.4 -0.6 20 -0.8 10 -1 VOUT = 5V VIN = 6.2V IOUT = 150mA COUT = 10mF CNR/SS = 10nF CBYP = 0nF 0 0 15 30 45 60 75 90 IOUT (mA) Figure 17. 8 10k 100k Frequency (Hz) Submit Documentation Feedback 105 120 135 150 10 100 1k 10k 100k Frequency (Hz) 1M 10M Figure 18. Copyright © 2010, Texas Instruments Incorporated TPS7A49xx www.ti.com SBVS121A – AUGUST 2010 – REVISED SEPTEMBER 2010 TYPICAL CHARACTERISTICS (continued) At TJ = –40°C to +125°C, VIN = VOUT(NOM) + 1.0V or VIN = 3.0V (whichever is greater), VEN = VIN, IOUT = 1mA, CIN = 2.2mF, COUT = 2.2mF, CNR/SS = 0nF, and the FB pin tied to OUT, unless otherwise noted. Output Spectral Noise Density (mV/ÖHz) OUTPUT SPECTRAL NOISE DENSITY vs OUTPUT CURRENT 10 VOUT = 1.2V VIN = 3V CIN = 2.2mF CNR/SS = 10nF COUT = 10mF 1 RMS NOISE IOUT 10Hz to 100kHz 100Hz to 100kHz 1mA 15.44 14.14 150mA 17.27 16.46 IOUT = 150mA 0.1 IOUT = 1mA 0.01 10 100 1k Frequency (Hz) 10k 100k Figure 19. Output Spectral Noise Density (mV/ÖHz) OUTPUT SPECTRAL NOISE DENSITY vs CNR/SS 10 VOUT = 1.2V VIN = 3V IOUT = 150mA CIN = 2.2mF COUT = 10mF CNR/SS = 0nF 1 RMS NOISE CNR/SS 10Hz to 100kHz 100Hz to 100kHz 0nF 69.04 67.87 10nF 16.58 15.86 0.1 CNR/SS = 10nF 0.01 10 100 1k Frequency (Hz) 10k 100k Figure 20. Output Spectral Noise Density (mV/ÖHz) OUTPUT SPECTRAL NOISE DENSITY vs VOUT(NOM) 10 VOUT(NOM) = 5V 1 IOUT = 1mA CIN = 2.2mF CNR = 10nF CBYP = 10nF COUT = 10mF RMS NOISE VOUT(NOM) 10Hz to 100kHz 100Hz to 100kHz 5V 21.15 14.74 1.2V 15.44 14.14 0.1 VOUT(NOM) = 1.2V 0.01 10 100 1k Frequency (Hz) 10k 100k Figure 21. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 9 TPS7A49xx SBVS121A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = –40°C to +125°C, VIN = VOUT(NOM) + 1.0V or VIN = 3.0V (whichever is greater), VEN = VIN, IOUT = 1mA, CIN = 2.2mF, COUT = 2.2mF, CNR/SS = 0nF, and the FB pin tied to OUT, unless otherwise noted. CAPACITOR-PROGRAMMABLE SOFT-START CAPACITOR-PROGRAMMABLE SOFT-START VEN VOUT = 1.2V VIN = 3V IOUT = 100mA COUT = 10mF CNR/SS = 0nF VOUT 1V/div 1V/div 5V/div 5V/div VEN Time (5ms/div) Figure 22. Figure 23. LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE VOUT VOUT = 15V VIN = 18V to 33V IOUT = 100mA COUT = 10mF CNR/SS = 10nF 5V/div VIN 20mV/div 5V/div 20mV/div Time (50ms/div) VOUT Time (10ms/div) Figure 24. Figure 25. LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE VOUT = 15V VIN = 18V IOUT = 1mA to 120mA COUT = 10mF CNR/SS = 10nF VOUT IOUT Time (100ms/div) Figure 26. Submit Documentation Feedback 100mA/div 50mV/div 100mA/div 50mV/div VOUT = 15V VIN = 33V to 18V IOUT = 100mA COUT = 10mF CNR/SS = 10nF VIN Time (10ms/div) 10 VOUT = 1.2V VIN = 3V IOUT = 100mA COUT = 10mF CNR/SS = 10nF VOUT VOUT VOUT = 15V VIN = 18V IOUT = 120mA to 1mA COUT = 10mF CNR/SS = 10nF IOUT Time (100ms/div) Figure 27. Copyright © 2010, Texas Instruments Incorporated TPS7A49xx www.ti.com SBVS121A – AUGUST 2010 – REVISED SEPTEMBER 2010 THEORY OF OPERATION GENERAL DESCRIPTION The TPS7A49xx belongs to a family of new generation linear regulators that use an innovative bipolar process to achieve ultralow-noise and very high PSRR levels at a wide input voltage range. These features, combined with a high thermal performance MSOP-8 with PowerPAD package make this device ideal for high-performance analog applications. ADJUSTABLE OPERATION The TPS7A4901 has an output voltage range of +1.194 to +33V. The nominal output voltage of the device is set by two external resistors, as shown in Figure 28. VOUT VIN OUT IN CIN 10mF EN CBYP 10nF TPS7A4901 R1 FB R2 CNR/SS 10nF NR/SS COUT 10mF GND Figure 28. Adjustable Operation for Maximum AC Performance R1 and R2 can be calculated for any output voltage range using the formula shown in Equation 1. To ensure stability under no load conditions, this resistive network must provide a current equal to or greater than 5mA. VOUT VOUT ³ 5mA R1 = R2 - 1 , where R1 + R2 VREF (1) If greater voltage accuracy is required, take into account the output voltage offset contributions because of the feedback pin current and use 0.1% tolerance resistors. CAPACITOR RECOMMENDATIONS Low ESR capacitors should be used for the input, output, noise reduction, and bypass capacitors. Ceramic capacitors with X7R and X5R dielectrics are preferred. These dielectrics offer more stable characteristics. Ceramic X7R capacitors offer improved over-temperature performance, while ceramic X5R capacitors are the most cost-effective and are available in higher values. Note that high ESR capacitors may degrade PSRR. To ensure stability, maximum ESR must be less than 200mΩ. INPUT AND OUTPUT CAPACITOR REQUIREMENTS The TPS7A49xx family of positive, high-voltage linear regulators achieve stability with a minimum input and output capacitance of 2.2mF; however, it is highly recommended to use a 10mF capacitor to maximize ac performance. NOISE REDUCTION AND BYPASS CAPACITOR REQUIREMENTS Although noise reduction and bypass capacitors (CNR/SS and CBYP, respectively) are not needed to achieve stability, it is highly recommended to use 0.01mF capacitors to minimize noise and maximize ac performance. MAXIMUM AC PERFORMANCE In order to maximize noise and PSRR performance, it is recommended to include 10mF or higher input and output capacitors, and 0.01mF noise reduction and bypass capacitors, as shown in Figure 28. The solution shown delivers minimum noise levels of 15.4mVRMS and power-supply rejection levels above 52dB from 10Hz to 400kHz; see Figure 18 and Figure 19. ENABLE PIN OPERATION The TPS7A49xx provides an enable feature (EN) that turns on the regulator when VEN > 2.1V. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 11 TPS7A49xx SBVS121A – AUGUST 2010 – REVISED SEPTEMBER 2010 OUTPUT NOISE The TPS7A49xx provides low output noise when a noise reduction capacitor (CNR/SS) is used. The noise reduction capacitor serves as a filter for the internal reference. By using a 0.01mF noise reduction capacitor, the output noise is reduced by almost 75% (from 69mVRMS to 17mVRMS); see Figure 20. www.ti.com Additionally, ac performance can be maximized by adding a 0.01mF bypass capacitor (CBYP) from the FB pin to the OUT pin. This capacitor greatly improves power-supply rejection at lower frequencies, for the band from 10Hz to 200kHz; see Figure 18. TPS7A49xx low output voltage noise makes it an ideal solution for powering noise-sensitive circuitry. The very high power-supply rejection of the TPS7A49xx makes it a good choice for powering high-performance analog circuitry, such as operational amplifiers, ADCs, DACS, and audio amplifiers. POWER-SUPPLY REJECTION TRANSIENT RESPONSE The 0.01mF noise reduction capacitor greatly improves TPS7A49xx power-supply rejection, achieving up to 15dB of additional power-supply rejection for frequencies between 110Hz and 200KHz. As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude but increases duration of the transient response. 12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated TPS7A49xx www.ti.com SBVS121A – AUGUST 2010 – REVISED SEPTEMBER 2010 APPLICATION INFORMATION POWER FOR PRECISION ANALOG One of the primary TPS7A49xx applications is to provide ultralow-noise voltage rails to high-performance analog circuitry in order to maximize system accuracy and precision. The TPS7A49xx family of positive high-voltage linear regulators in conjunction with its negative counterpart (the TPS7A30xx family of negative high-voltage linear regulators), provide ultralow-noise, positive and negative voltage rails for high-performance analog circuitry, such as operational amplifiers, ADCs, DACs, and audio amplifiers. Because of the ultralow noise levels at high voltages, analog circuitry with high-voltage input supplies can be used. This characteristic allows for high-performance analog solutions to optimize the voltage range, maximizing system accuracy. The TPS7A49xx offers a wide-bandwidth, very-high power-supply rejection ratio. This specification makes it ideal for post dc/dc converter filtering, as shown in Figure 29. It is highly recommended to use the maximum performance schematic shown in Figure 28. Also, verify that the fundamental frequency (and its first harmonic, if possible) is within the bandwidth of the regulator PSRR, shown in Figure 18. +18V IN OUT +15V TPS7A49 POST DC/DC CONVERTER FILTERING Most of the time, the voltage rails available in a system do not match the voltage specifications demanded by one or more of its circuits; these rails must be stepped up or down, depending on specific voltage requirements. DC/DC converters are the preferred solution to step up or down a voltage rail when current consumption is not negligible. They offer high efficiency with minimum heat generation, but they have one primary disadvantage: they introduce a high-frequency component, and the associated harmonics, on top of the dc output signal. This high-frequency component, if not filtered properly, degrades analog circuitry performance, reducing overall system accuracy and precision. -18V EN GND IN OUT -15V TPS7A30 EN GND EVM Figure 29. Post DC/DC Converter Regulation to High-Performance Analog Circuitry AUDIO APPLICATIONS Audio applications are extremely sensitive to any distortion and noise in the audio band from 20Hz to 20kHz. This stringent requirement demands clean voltage rails to power critical high-performance audio systems. The very-high power-supply rejection ratio (> 55dB) and low noise at the audio band of the TPS7A49xx maximize performance for audio applications; see Figure 18. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 13 TPS7A49xx SBVS121A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com LAYOUT PACKAGE MOUNTING Solder pad footprint recommendations for the TPS7A49xx are available at the end of this product datasheet and at www.ti.com. BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for IN and OUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor should connect directly to the GND pin of the device. Equivalent series inductance (ESL) and equivalent series resistance (ESR) must be minimized to maximize performance and ensure stability. Every capacitor (CIN, COUT, CNR/SS, CBYP) must be placed as close as possible to the device and on the same side of the printed circuit board (PCB) as the regulator itself. Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use of vias and long traces is strongly discouraged because they may impact system performance negatively and even cause instability. If possible, and to ensure the maximum performance denoted in this product datasheet, use the same layout pattern used for TPS7A49 evaluation board, available at www.ti.com. THERMAL PROTECTION Thermal protection disables the output when the junction temperature rises to approximately +170°C, allowing the device to cool. When the junction temperature cools to approximately +150°C, the output circuitry is enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to a maximum of +125°C. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger 14 Submit Documentation Feedback at least +35°C above the maximum expected ambient condition of your particular application. This configuration produces a worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS7A49xx has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS7A49xx into thermal shutdown degrades device reliability. POWER DISSIPATION The ability to remove heat from the die is different for each package type, presenting different considerations in the PCB layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data or JEDEC low- and high-K boards are given in the Dissipation Ratings Table. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat dissipating layers also improves the heatsink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current times the voltage drop across the output pass element, as shown in Equation 2: PD = (VIN - VOUT) IOUT (2) SUGGESTED LAYOUT AND SCHEMATIC Layout is a critical part of good power-supply design. There are several signal paths that conduct fast-changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power-supply performance. To help eliminate these problems, the IN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with a X5R or X7R dielectric. The GND pin should be tied directly to the PowerPAD under the IC. The PowerPAD should be connected to any internal PCB ground planes using multiple vias directly under the IC. It may be possible to obtain acceptable performance with alternate PCB layouts; however, the layout shown in Figure 30 and the schematic shown in Figure 31 have been shown to produce good results and are meant as a guideline. Copyright © 2010, Texas Instruments Incorporated TPS7A49xx www.ti.com SBVS121A – AUGUST 2010 – REVISED SEPTEMBER 2010 Figure 30. PCB Layout Example U1 TPS7A49XXDGN 5 6 C4 7 8 Vin J1 4 GND EN 3 NR/SS NC DNC FB 2 IN PwPd J1 1 OUT C1 J7 GND R1 9 J4 C2 C3 R3 Figure 31. Schematic for PCB Layout Example Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 15 TPS7A49xx SBVS121A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (August, 2010) to Revision A Page • Revised Features list ............................................................................................................................................................ 1 • Changed Description text (paragraph 1) to remove description of maximum load .............................................................. 1 • Revised shutdown supply current, feedback current, and enable current specifications; rounded typical performance values .................................................................................................................................................................................... 3 • Revised Functional Block Diagram for clarification .............................................................................................................. 4 • Changed description of NC pin (pin 3) in Pin Descriptions table ......................................................................................... 5 • Updated Figure 1 to show correct device performance ........................................................................................................ 6 16 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 25-Aug-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPS7A4901DGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples TPS7A4901DGNT ACTIVE MSOPPowerPAD DGN 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS7A4901DGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS7A4901DGNT MSOPPower PAD DGN 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS7A4901DGNR MSOP-PowerPAD DGN 8 2500 346.0 346.0 29.0 TPS7A4901DGNT MSOP-PowerPAD DGN 8 250 190.5 212.7 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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