SLAS409 − DECEMBER 2003
FEATURES
D 1.25 MHz Sample Rate, 14-Bit Resolution
D Zero Latency
D Unipolar, Pseudo Differential Input, Range:
D
D
D
D
D
D
D
D
− 0 V to 2.5 V
SPIE Compatible Serial Interface
77.5 dB SNR and −95 dB THD at 0.5 MHz I/P
Power Dissipation 45 mW at 1.25 MSPS
Nap Mode (10 mW Power Dissipation)
Power Down (10 mW)
Internal Reference
Internal Reference Buffer
48-Pin TQFP Package
APPLICATIONS
D Optical Networking (DWDM, MEMS Based
Switching)
Spectrum Analyzers
High Speed Data Acquisition Systems
D
D
D High Speed Close-Loop Systems
D Telecommunication
DESCRIPTION
The ADS7890 is a 14-bit 1.25-MSPS A-to-D converter with 2.5-V internal reference. The device includes a
capacitor based SAR A/D converter with inherent sample and hold. The device offers a 14-bit serial SPI or DSP
compatible interface. The device has a pseudo-differential input stage.
The −IN swing of ±200 mV is useful to compensate for ground voltage mismatch between the ADC and sensor
and also to cancel common-mode noise. The device operates at lower power when used at lower conversion
rates because of the nap feature. The device is available in a 48-pin TQFP package.
SDO
SAR
+IN
−IN
+
_
Output
Latches
and
3-State
Drivers
CDAC
Comparator
REFIN
CLOCK
REFOUT
2.5 V
Internal
Reference
Conversion
and
Control Logic
SCLK
BUSY
CS
FS
PWD/RST
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI is a trademark of Motorola, Inc.
!"#$%&" ' ()##*& %' "! +),-(%&" .%&* #".)(&'
("!"#$ &" '+*(!(%&"' +*# &/* &*#$' "! *0%' '&#)$*&' '&%.%#. 1%##%&2
#".)(&" +#"(*''3 ."*' "& *(*''%#-2 (-).* &*'&3 "! %-- +%#%$*&*#'
Copyright 2003, Texas Instruments Incorporated
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SLAS409 − DECEMBER 2003
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
MODEL
MAXIMUM
INTEGRAL
LINEARITY
(LSB)
ADS7890
MAXIMUM
DIFFERENTIAL
LINEARITY
(LSB)
±1.5
NO MISSING
CODES AT
RESOLUTION
(BIT)
PACKAGE
TYPE
14
48-Pin
TQFP
+1.5/−1
PACKAGE
DESIGNATOR
PFB
TEMPERATURE
RANGE
ORDERING
INFORMATION
TRANSPORT
MEDIA QUANTITY
ADS7890IPFBT
Tape and reel
250
ADS7890IPFBR
Tape and reel
1000
−40°C to 85°C
NOTE: For most current specifications and package information, refer to the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range(1)
UNIT
+IN to AGND
−0.3 V to +VA + 0.1 V
−IN to AGND
−0.3 V to 0.5 V
+VA to AGND
−0.3 V to 7 V
+VBD to BDGND
−0.3 V to 7 V
Digital input voltage to GND
−0.3 V to (+VBD + 0.3 V)
Digital output to GND
−0.3 V to (+VBD + 0.3 V)
Operating temperature range
−40°C to 85°C
Storage temperature range
−65°C to 150°C
Junction temperature (TJmax)
150°C
Power dissipation
TQFP package
Lead temperature, soldering
θJA Thermal impedance
Vapor phase (60 sec)
Infrared (15 sec)
(TJ Max–TA)/ θJA
86°C/W
215°C
220°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
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SLAS409 − DECEMBER 2003
SPECIFICATIONS
TA = −40°C to 85°C, +VA = 5 V, +VBD = 5 V or 3.3 V, Vref = 2.5 V, fsample = 1.25 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Full-scale input span(1)
Absolute input range
+IN – (−IN)
0
+IN
−0.2
−IN
−0.2
Input capacitance
Input leakage current
Vref
Vref + 0.2
+0.2
V
V
27
pF
500
pA
14
Bits
SYSTEM PERFORMANCE
Resolution
No missing codes
Integral linearity(2)
−1.5
14
±0.75
1.5
−1
±0.75
1.5
Bits
LSB(3)
LSB(3)
Differential linearity
Offset error(4)
External reference
−1.5
±0.5
1.5
mV
Gain error(4)
External reference
−1
±0.25
1
mV
Common-mode rejection ratio
With common mode input signal = 200
mVp−p at 0.5 MHz
60
dB
Power supply rejection
At 3FF0H output code,
+VA = 4.75 V to 5.25 V , Vref = 2.50 V
80
dB
SAMPLING DYNAMICS
Conversion time
Acquisition time
+VDB = 5 V
365
nsec
+VDB = 3 V
365
nsec
+VDB = 5 V
187.5
+VDB = 3 V
187.5
nsec
nsec
Maximum throughput rate
1.25
MHz
Aperture delay
5
nsec
Aperture jitter
20
psec
Step response
50
nsec
Over voltage recovery
50
nsec
DYNAMIC CHARACTERISTICS
Total harmonic distortion(5)
VIN = 2.496 Vp−p at 100 kHz/2.5 Vref
VIN = 2.496 Vp−p at 0.5 MHz/2.5 Vref
SNR
VIN = 2.496 Vp−p at 100 kHz/2.5 Vref
VIN = 2.496 Vp−p at 0.5 MHz/2.5 Vref
SINAD
VIN = 2.496 Vp−p at 100 kHz/2.5 Vref
VIN = 2.496 Vp−p at 0.5 MHz/2.5 Vref
SFDR
VIN = 2.496 Vp−p at 0.5 MHz/2.5 Vref
−95
−95
−88
78
dB
77.5
77
dB
77
89
−3 dB Small signal bandwidth
dB
97
dB
50
MHz
EXTERNAL REFERENCE INPUT
Input VREF range
Resistance(6)
2.4
2.5
500
2.6
V
kΩ
(1) Ideal input span; does not include gain or offset error.
(2) This is endpoint INL, not best fit.
(3) LSB means least significant bit.
(4) Measured relative to actual measured reference.
(5) Calculated on the first nine harmonics of the input frequency.
(6) Can vary ±20%.
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SLAS409 − DECEMBER 2003
SPECIFICATIONS Continued
TA = −40°C to 85°C, +VA = 5 V, +VBD = 5 V or 3.3 V, Vref = 2.5 V, fsample = 1.25 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL REFERENCE OUTPUT
From 95% (+VA), with 1-µF storage
capacitor on REFOUT to AGND
Start-up time
VREF Range
Source current
IOUT=0
Line regulation
+VA = 4.75 V to 5.25 V
Drift
IOUT = 0
2.48
2.5
Static load
120
msec
2.52
V
10
µA
1
mV
25
PPM/C
DIGITAL INPUT/OUTPUT
Logic family
Logic level
CMOS
VIH
VIL
IIH = 5 µA
IIL = 5 µA
VOH
VOL
IOH = 2 TTL loads
IOL = 2 TTL loads
+VBD −1
−0.3
+VBD + 0.3
0.8
+VBD − 0.6
0
+VBD
0.4
V
V
V
Straight
Binary
Data format
POWER SUPPLY REQUIREMENTS
Power supply voltage
+VBD
+VA
2.7
3.3
5.25
V
4.75
5
5.25
V
Supply current, +VA, 1.25 MHz sample rate
Power dissipation, 1.25 MHz sample rate
+VA = 5 V
9
12
mA
45
60
mW
2
3
mA
2
2.5
NAP MODE
Supply current, +VA
POWER DOWN
Supply current, +VA
Power down time(1)
Power up time
1-µF Storage capacitor on REFOUT to
AGND
Invalid conversions after power up or reset
µA
10
µsec
25
msec
4
Numbers
85
°C
TEMPERATURE RANGE
Operating free-air
(1) Time required to reach level of 2.5 µA.
4
−40
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SLAS409 − DECEMBER 2003
TIMING REQUIREMENTS
All specifications typical at −40°C to 85°C, +VA = +5 V, +VBD = +5 V (see Notes 1, 2, and 3)
PARAMETER
Conversion time
Acquisition time
SYMBOL
t(conv)
t(acq)
MIN
TYP
MAX
UNITS
REF FIG.
365
ns
1,2
187.5
ns
1,2
25
ns
1,2
Pulse duration, SCLK low
t(cyc)
twL
10
ns
Pulse duration, SCLK high
twH
10
ns
tsu1
td1
8
tw1
th1
Cycle time, SCLK
DSP INTERFACE
Setup time CS low to FS high
Delay time FS high to MSB valid
FS pulse duration
Hold time, SCLK falling edge to FS falling edge (last SCLK falling edge when
FS high)
Setup time, FS falling edge to first falling edge of SCLK after FS low
Hold time, internal conversion (indicated by tconv) end to FS rising edge to avoid
conversion abort
Delay time, 9th SCLK rising edge to FS rising edge for frame abort during
sample
ns
2
ns
2
15
ns
2
5
ns
2
9
tsu2
th3
5
ns
2
10
ns
2
td8
5
ns
10
tw5
th2
15
ns
1
5
ns
1
tsu3
td3
5
ns
1
ns
1
th3
10
ns
1
td2
th4
ns
1, 2
10
ns
1, 2
40
ns
1, 2
365
ns
1, 2
ns
6, 11
10
ns
1, 2
6140
ns
4
ns
3
ms
3
SPI INTERFACE
Pulse duration, CS minimum
Hold time, SCLK falling edge (last SCLK falling edge when CS is high) to CS
falling edge
Setup time, CS low to first SCLK falling edge after CS low
Delay time, CS low to MSB valid
Hold time, internal conversion (indicted by tconv) end to CS falling edge to avoid
conversion abort
9
DSP AND SPI INTERFACE
Delay time, SCLK rising edge to SDO valid
Hold time, 16th SCLK falling edge to CS rising edge
Delay time, 16th SCLK falling edge to BUSY rising edge
Pulse duration, BUSY high
9
td4
tw2
Delay time, 9th SCLK rising edge to CS rising edge for frame abort during
sample
td8
Delay time, CS high to SDO three-state
td5
5
POWER DOWN/RESET
Pulse width, low for PWD/RST to reset the device
Pulse width, low for PWD/RST to power down the device
Delay time, power up after PWD/RST is high
tw3
tw4
td6
td7
45
7200
25
Delay time, falling edge of PWD/RST to SDO three-state
10
ns
3, 4
(1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2.
(2) See timing diagram.
(3) All timings are measured with 20-pF equivalent loads at 5 V +VBD and 10-pF equivalent loads at 3 V +VBD on the SDO and BUSY pins.
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SLAS409 − DECEMBER 2003
PWD/RST
BDGND
SCLK
+VBD
CS
FS
+VA
AGND
AGND
+VA
REFM
REFM
PIN ASSIGNMENTS
48 47 46 45 44 43 42 41 40 39 38 37
REFIN
1
36
BUSY
REFOUT
2
35
BDGND
NC
3
34
+VBD
+VA
4
33
NC
NC
5
32
+IN
6
31
SDO
−IN
7
30
NC
AGND
8
29
+VA
9
28
NC
NC
+VA
10
27
NC
11
26
NC
AGND 12
25
BDGND
AGND
AGND
6
24
NC
+VBD
NC
NC
NC
NC
NC
NC
NC
AGND
+VA
NC − No connection
AGND
13 14 15 16 17 18 19 20 21 22 23
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SLAS409 − DECEMBER 2003
Terminal Functions
I/O
DESCRIPTION
31
PIN
SDO
NAME
O
Serial data out. Data (excluding MSB) is latched out on the rising of SCLK with MSB first format. MSB
is latched with the rising edge of FS or falling edge of CS depending on whether a DSP or SPI
interface is used.
36
BUSY
O
Status output. This pin is high when a conversion is in progress.
39
SCLK
I
Serial clock. The device needs a minimum of 16 clocks per frame. As described in the timing
diagrams, it controls serial data out (first 14 clocks), powerup (from nap) on the 8th rising edge of
SCLK, start of sample (track) on the 9th rising edge and end of sample or start of conversion on the
16th falling edge of SCLK. The clock can be stopped after the 16th falling edge. It is important to have
minimum jitter on SCLK as it decides the sampling instance and the jitter results in a loss of SNR
performance.
41
FS
I
Frame sync. The rising edge of FS starts a new sample and convert frame. The MSB from the
previous conversion is latched out on the rising edge of FS. The rising edge of FS during an internal
convert (see Figure 12) aborts the conversion and starts a new frame.
42
CS
I
Chip Select. Active low signal. The falling edge of CS starts a new sample and convert frame. The
MSB from the previous conversion is latched out on the falling edge of CS. This signal can be pulled
high after the 16th falling edge of SCLK during the frame. SDO goes to three-state with CS high. The
falling edge of CS during internal convert (see Figure 7) aborts the conversion and starts a new
frame.
24, 34, 40
+VBD
Digital power supply for all digital inputs and outputs. Refer to Table 2 for layout guidelines.
25, 35, 37
BDGND
Digital ground for all digital inputs and outputs. Needs to be shorted to analog ground plane below
the device.
38
PWD/RST
5, 8, 11, 12, 14,
15, 44, 45
AGND
Analog ground pins. Need to be shorted to analog ground plane below the device.
4, 9, 10, 13, 43,
46
+VA
Analog power supplies. Refer to Table 2 for layout guidelines.
6
+IN
I
Non inverting analog input channel
7
−IN
I
Inverting analog input channel
1
REFIN
I
Reference (positive) input. Needs to be decoupled with REFM pin using 0.1-µF bypass capacitor
and 1-µF storage capacitor.
2
REFOUT
O
Internal reference output. To be shorted to REFIN pin when internal reference is used. Do not
connect to REFIN pin when external reference is used. Always needs to be decoupled with AGND
using 0.1-µF bypass capacitor.
47, 48
REFM
I
Reference ground. To be connected to analog ground plane.
3, 16 − 23, 26 −
30, 32, 33
NC
I
Active low input, acts as device power down/device reset signal.
No connection pins.
DESCRIPTION AND TIMING DIAGRAMS
DEVICE OPERATION WITH SPI INTERFACE (See Figure 1)
Device operation is controlled with CS and SCLK with FS always held high. The frame starts with the falling
edge of CS. The MSB is latched out first on the SDO pin. The clock cycle, with the first falling edge after the
falling edge of CS, is counted as first clock. Subsequent data bits are latched out on the SDO pin with every
rising edge of further clocks (until the 14th rising edge of SCLK). The device has a built-in NAP mode. The device
enters the NAP state with an end of conversion and continues to be in this state until the 8th SCLK rising edge.
The sampling switch is closed on the 9th SCLK rising edge and the device samples the analog input [+IN− (−IN)]
and enters the conversion phase on the 16th SCLK falling edge. The BUSY signal goes high to indicate the
conversion is in progress and continues to be high until the end of conversion. A new frame can be started with
the end of conversion.
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SLAS409 − DECEMBER 2003
1
2
3
8
9
t(cyc)
14
15
16
th4
SCLK
th2
twH
tsu3
td5
twL
CS
tw5
td2
th3
td3
SDO
MSB
LSB
td4
BUSY
tw2
t(conv)
t(acq), SAMPLE
Power Up
Figure 1. Device Operation With SPI Interface (FS Held High)
DEVICE OPERATION WITH DSP INTERFACE (See Figure 2)
Device operation is controlled with CS, SCLK, and FS. The frame starts with the rising edge of FS with CS
already low. The MSB is latched out first on the SDO pin. The clock cycle, with the first falling edge after the
falling edge of FS is counted as first clock. Subsequent data bits are latched out on the SDO pin with every rising
edge of further clocks (until the 14th rising edge of SCLK). The device has a built-in NAP mode. The device
enters the NAP state with an end of conversion and continues to be in this state until the 8th SCLK rising edge.
The sampling switch is closed on the 9th rising edge and the device samples the analog input [+IN− (−IN)] and
enters the conversion phase on the 16th SCLK falling edge.
CS can be pulled high at any time after this. The BUSY signal goes high to indicate the conversion is in progress
and continues to be high until the end of conversion. A new frame can be started with the end of conversion.
1
2
3
8
9
14
15
16
th4
t(cyc)
SCLK
th1
twH
tsu2
twL
td5
CS
tsu1
th3
td2
FS
tw1
td1
SDO
LSB
MSB
td4
BUSY
t(acq), SAMPLE
tw2
t(conv)
Power Up
Figure 2. Device Operation With DSP Interface
POWERDOWN/RESET
A low level on the PWD/RST pin puts the device in the powerdown phase. This is an asynchronous signal. As
shown in Figure 4, the device is in the reset phase for the first tw3 period after the falling edge of PWD/RST.
SDO goes to three-state for a period of td7 after the falling edge of PWD/RST. The device powers down if the
PWD/RST pin continues to be low for a time period of more than tw4. Data is not valid for the first four
conversions after powerup (see Figure 3) or the end of reset (see Figure 4). The device is initialized during the
first four conversions.
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SLAS409 − DECEMBER 2003
tw4
td7
Valid Conversions
PWD/RST
First 4 Invalid Conversions
BUSY
1
2
3
4
5
td6
SDO
Power Down
Phase
RESET Phase
Invalid Data
Valid Data
Figure 3. Device Power Down
tw3
td7
PWD/RST
Valid Conversions
First 4 Invalid Conversions
BUSY
SDO
RESET Phase
Invalid Data
Valid Data
Figure 4. Device Reset
FRAME ABORT
A frame can be aborted at any time. There are three phases in the frame, data frame before sample start (first
8 clocks), sample phase (9th rising edge to the 16th falling edge of SCLK), and the conversion phase. The
following sections describe a frame abort during each of these phases, for both SPI and DSP interfaces.
FRAME ABORT IN SPI INTERFACE MODE (FS Held High)
The rising edge of CS after a frame start (falling edge of CS) before the 9th rising edge of SCLK aborts a frame
(see Figure 5). SDO goes to three-state with CS high. A new frame is started with the falling edge of CS.
Previous conversion results are available on SDO during the new frame.
2
3
D13
D12
8
9
2
3
15
16
SCLK
CS
BUSY
SDO
D6
MSB-D13
LSB-D0
Data From Last Conversion
Figure 5. Frame Abort Before Sample Start
A CS rising edge during the sample period (td8 after the 9th rising edge of SCLK to the 16th falling edge of SCLK)
aborts the sample and the device enters the conversion phase. As expected, SDO goes to three-state with CS
high. The conversion results can be latched in the next frame, however reliability of the data depends on the
sampling time available before the frame abort.
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SLAS409 − DECEMBER 2003
2
3
9
10
16
SCLK
td8
CS
BUSY
SDO
D13
D12
Figure 6. Frame Abort During Sample
The falling edge of CS during a conversion (from BUSY high until the end of t(conv) as shown in Figure 7) aborts
the ongoing conversion. This starts the next frame. The device outputs 3F80 (hex) on SDO during the first frame
after the conversion abort.
2
3
15
16
1
2
3
4
5
SCLK
CS
td4
Busy Fall Without
Conversion Abort
tw2
BUSY
t(CONV)
SDO
MSB
3F80 (hex)
Figure 7. Frame Abort During Conversion
FRAME ABORT IN DSP INTERFACE MODE
The rising edge of FS (see Figure 8) or the rising edge of CS (see Figure 9) after the falling edge of FS and
before the 9th rising edge of SCLK aborts the frame. SDO goes to three-state with CS high and a new frame
is started with the rising edge of FS (see Figure 8 and Figure 9). Previous conversion results are available on
SDO during the new frame.
2
3
MSB− D13
D12
8
9
2
3
15
16
SCLK
FS
BUSY
CS
(Held Low)
SDO
D6
MSB−D13
LSB−D0
Data From Last Conversion
Figure 8. Frame Abort Using FS Before Sample Start
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SLAS409 − DECEMBER 2003
2
3
9
2
3
15
16
SCLK
FS
BUSY
CS
SDO
MSB-D13
MSB-D13
D12
LSB-D0
Data From Last Conversion
Figure 9. Frame Abort Using CS Before Sample Start
The rising edge of FS (see Figure 10) or rising edge of CS (see Figure 11) during a sample period (td8 after the
9th rising edge of SCLK) to the 16th falling edge of SCLK aborts the sample and the device enters the
conversion phase, this also aborts the current data out operation on SDO (if aborted before 14th clock). As
expected, SDO goes to three-state with CS high. The conversion results can be latched in the next frame,
however reliability of the data depends on the sampling time available before the frame abort.
2
3
9
10
16
SCLK
FS
td8
BUSY
CS
(Held Low)
SDO
MSB− D13
D12
LSB−D0
Figure 10. Frame Abort Using FS During Sample
2
3
9
10
16
SCLK
td8
FS
BUSY
CS
SDO
MSB− D13
D12
Figure 11. Frame Abort Using CS During Sample
The rising edge of FS during a conversion (from BUSY high until the end of t(conv) as shown in Figure 12) aborts
the ongoing conversion. This starts the next frame. The device outputs 3F80 (hex) on SDO during the first frame
after the conversion abort. Toggling CS during a conversion (with FS low) does not have any effect on the
conversion.
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SLAS409 − DECEMBER 2003
2
3
15
16
1
2
3
SCLK
FS
td4
Busy Fall Without
Conversion Abort
tw2
BUSY
t(CONV)
SDO
CS
(Held Low)
MSB
3F80 (hex)
Figure 12. Frame Abort During Conversion
12
4
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SLAS409 − DECEMBER 2003
TYPICAL CHARACTERISTICS(1)
EFFECTIVE NUMBER OF BITS
vs
FREE-AIR TEMPERATURE
DC CODE SPREAD AT CENTER OF CODE
13
3128
+VA = 5 V,
+VBD = 5 V,
Code = 8192,
Sample Rate = 1.25 MSPS,
Vref = 2.5 V,
TA = 255C
3000
Count
2500
2000
1500
1124
1000
658
500
0
0
ENOB − Effective Number of Bits − Bits
3500
12.9
12.8
12.7
fi = 100 kHz,
Sample Rate = 1.25 MSPS,
+VA = 5 V,
+VBD = 5 V,
Vref = 2.5 V
12.6
12.5
12.4
12.3
12.2
12.1
50
40
0
8189 8190 8191 8192 8193 8194 8195
12
−40
−20
0
20
40
60
TA − Free-Air Temperature − °C
Code
Figure 13
Figure 14
SIGNAL-TO-NOISE AND DISTORTION
vs
FREE-AIR TEMPERATURE
SIGNAL-TO-NOISE RATIO
vs
FREE-AIR TEMPERATURE
79
77.6
77.4
fi = 100 kHz,
Sample Rate = 1.25 MSPS,
+VA = 5 V,
+VBD = 5 V,
Vref = 2.5 V
78.8
SNR − Signal-to-Noise Ratio − dB
SINAD − Signal-to-Noise and Distortion − dB
78
77.8
77.2
77
76.8
76.6
76.4
78.6
78.4
fi = 100 kHz,
Sample Rate = 1.25 MSPS,
+VA = 5 V,
+VBD = 5 V,
Vref = 2.5 V
78.2
78
77.8
77.6
77.4
77.2
76.2
76
−40
80
−20
0
20
40
60
TA − Free-Air Temperature − °C
Figure 15
80
77
−40
−20
0
20
40
60
TA − Free-Air Temperature − °C
80
Figure 16
(1) Vref = 2.5 V external, unless otherwise specified.
13
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SLAS409 − DECEMBER 2003
TOTAL HARMONIC DISTORTION
vs
FREE-AIR TEMPERATURE
SPURIOUS FREE DYNAMIC RANGE
vs
FREE-AIR TEMPERATURE
−85
THD − Total Harmonic Distortion − dB
SFDR − Spurious Free Dynamic Range − dB
105
100
95
fi = 100 kHz,
Sample Rate = 1.25 MSPS,
+VA = 5 V,
+VBD = 5 V,
Vref = 2.5 V
90
85
−40
−20
0
20
40
60
−90
−95
−100
−105
−40
80
Figure 17
0
20
40
60
80
Figure 18
SIGNAL-TO-NOISE AND DISTORTION
vs
INPUT FREQUENCY
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY
79
14
TA = 255C,
Sample Rate = 1.25 MSPS,
+VA = 5 V,
+VBD = 5 V,
Vref = 2.5 V
13.5
SINAD − Signal-to-Nois and Distortion − dB
ENOB − Effective Number of Bits − Bits
−20
TA − Free-Air Temperature − °C
TA − Free-Air Temperature − °C
13
12.5
12
11.5
TA = 255C,
Sample Rate = 1.25 MSPS,
+VA = 5 V,
+VBD = 5 V,
Vref = 2.5 V
78
77
76
75
74
73
11
0
100
200
300
400
fi − Input Frequency − kHz
Figure 19
14
fi = 100 kHz,
Sample Rate = 1.25 MSPS,
+VA = 5 V,
+VBD = 5 V,
Vref = 2.5 V
500
0
100
200
300
400
fi − Input Frequency − kHz
Figure 20
500
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SLAS409 − DECEMBER 2003
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY
SIGNAL-TO-NOISE RATIO
vs
INPUT FREQUENCY
110
SFDR − Spurious Free Dynamic Range − dB
SNR − Signal-to-Noise Ratio − dB
79
78
77
76
75
TA = 255C,
Sample Rate = 1.25 MSPS,
+VA = 5 V,
+VBD = 5 V,
Vref = 2.5 V
74
105
100
95
90
85
TA = 255C,
Sample Rate = 1.25 MSPS,
+VA = 5 V,
+VBD = 5 V,
Vref = 2.5 V
80
75
73
0
0
50 100 150 200 250 300 350 400 450 500
100
200
300
400
fi − Input Frequency − kHz
fi − Input Frequency − kHz
Figure 21
Figure 22
GAIN ERROR
vs
SUPPLY VOLTAGE
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
1
−75
TA = 255C,
Sample Rate = 1.25 MSPS,
+VA = 5 V,
+VBD = 5 V,
Vref = 2.5 V
−80
−85
0.8
0.6
E G − Gain Error − mV
THD − Total Harmonic Distortion − dB
500
−90
−95
TA = 255C,
Sample Rate = 1.25 MSPS,
+VBD = 5 V,
Vref = 2.5 V
0.4
0.2
0
−0.2
−0.4
−100
−0.6
−105
−0.8
−110
0
100
200
300
400
fi − Input Frequency − kHz
Figure 23
500
600
−1
4.75
4.85
4.95
5.05
5.15
5.25
+VA − Supply Voltage − V
Figure 24
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SLAS409 − DECEMBER 2003
GAIN ERROR
vs
FREE-AIR TEMPERATURE
OFFSET ERROR
vs
SUPPLY VOLTAGE
1
TA = 255C,
Sample Rate = 1.25 MSPS,
+VBD = 5 V,
Vref = 2.5 V
0.5
0.75
0.5
E G − Gain Error − mV
E O − Offset Error − mV
1
0
Sample Rate = 1.25 MSPS,
+VA = 5 V,
+VBD = 5 V,
Vref = 2.5 V
0.25
0
−0.25
−0.5
−0.5
−0.75
−1
4.75
4.85
4.95
5.05
5.15
+VA − Supply Voltage − V
−1
−40
5.25
−20
0
20
40
60
TA − Free-Air Temperature − °C
Figure 25
Figure 26
POWER DISSIPATION
vs
SAMPLE RATE
OFFSET ERROR
vs
FREE-AIR TEMPERATURE
E O − Offset Error − mV
0.75
50
Sample Rate = 1.25 MSPS,
+VA = 5 V,
+VBD = 5 V,
Vref = 2.5 V
45
PD− Power Dissipation − mW
1
0.5
0.25
0
−0.25
−0.5
35
30
25
20
15
5
0
−20
0
20
40
60
TA − Free-Air Temperature − °C
Figure 27
16
40
TA = 255C,
+VA = 5 V,
+VBD = 5 V,
Vref = 2.5 V
10
−0.75
−1
−40
80
80
0
200
400
600
800
Sample Rate − KSPS
Figure 28
1000
1200
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SLAS409 − DECEMBER 2003
DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
1
46.5
DNL − Differential Nonlinearity − LSBs
PD − Power Dissipation − mW
47.5
Sample Rate = 1.25 MSPS,
+VA = 5 V,
+VBD = 5 V,
Vref = 2.5 V
45.5
44.5
43.5
42.5
−40
−20
0
20
40
60
TA − Free-Air Temperature − °C
0.75
Max
0.5
0.25
Sample Rate = 1.25 MSPS,
+VA = 5 V,
+VBD = 5 V,
Vref = 2.5 V
0
−0.25
Min
−0.5
−0.75
−1
−40
80
−20
0
Figure 29
2.5045
Vref − Internal Reference Output − V
INL − Integral Nonlinearity − LSBs
80
2.505
Sample Rate = 1.25 MSPS,
+VA = 5 V,
+VBD = 5 V,
Vref = 2.5 V
Max
0.75
0.5
0.25
0
−0.25
−0.5
Min
−0.75
−1
+VA = 5 V,
+VBD = 5 V
2.504
2.5035
2.503
2.5025
2.502
2.5015
2.501
2.5005
−1.25
−1.5
−40
60
INTERNAL REFERENCE OUTPUT
vs
FREE-AIR TEMPERATURE
1.5
1
40
Figure 30
INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
1.25
20
TA − Free-Air Temperature − °C
2.5
−20
0
20
40
60
TA − Free-Air Temperature − °C
Figure 31
80
−40
−20
0
20
40
60
TA − Free-Air Temperature − °C
80
Figure 32
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SLAS409 − DECEMBER 2003
INTERNAL REFERENCE OUTPUT
vs
SUPPLY VOLTAGE
2.505
Vref − Internal Reference Output − V
2.5045
TA = 255C,
+VBD = 5 V
2.504
2.5035
2.503
2.5025
2.502
2.5015
2.501
2.5005
2.5
4.75
4.85
4.95
5.05
5.15
5.25
+VA − Supply Voltage − V
Figure 33
DNL − LSB
DIFFERENTIAL NONLINEARITY
1
0.8
0.6
0.4
0.2
TA = 255C, +VA = 5 V, +VBD = 5 V,
Sample Rate = 1.25 MSPS,
Vref = 2.5 V
0
−0.2
−0.4
−0.6
−0.8
−1
0
2000
4000
6000
8000
Code
10000
12000
14000
16000
12000
14000
16000
Figure 34
INTEGRAL NONLINEARITY
INL − LSB
1
0.8
0.6
TA = 255C, +VA = 5 V, +VBD = 5 V,
Sample Rate = 1.25 MSPS,
Vref = 2.5 V
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
0
2000
4000
6000
8000
Code
Figure 35
18
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SLAS409 − DECEMBER 2003
Signal Power − dB
AC PERFORMANCE
20
0
−20
−40
−60
−80
−100
−120
−140
−160
−180
TA = 255C, +VA = 5 V, +VBD = 5 V,
Sample Rate = 1.25 MSPS,
Vref = 2.5 V, fi = 500 kHz
0
100000
200000
300000
400000
fi − Input Frequency − Hz
500000
600000
Figure 36
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SLAS409 − DECEMBER 2003
PRINCIPLES OF OPERATION
The ADS7890 is a member of a family of high-speed successive approximation register (SAR) analog-to-digital
converters (ADC). The architecture is based on charge redistribution, which inherently includes a sample/hold
function.
The conversion clock is generated internally. The conversion time is 365 ns max (at 5 V +VBD).
The analog input is provided to two input pins: +IN and −IN. (Note that this is pseudo differential input and there
are restrictions on –IN voltage range.) When a conversion is initiated, the difference voltage between these pins
is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from
any internal function.
REFERENCE
The ADS7890 has a built-in 2.5-V (nominal value) reference but can operate with an external reference. When
an internal reference is used, pin 2 (REFOUT) should be connected to pin 1 (REFIN) with an 0.1-µF decoupling
capacitor and a 1-µF storage capacitor between pin 2 (REFOUT) and pins 47 and 48 (REFM). The internal
reference of the converter is buffered . There is also a buffer from REFIN to CDAC. This buffer provides isolation
between the external reference and the CDAC and also recharges the CDAC during conversion. It is essential
to decouple REFOUT to AGND with a 0.1-µF capacitor while the device operates with an external reference.
ANALOG INPUT
When the converter enters hold mode, the voltage difference between the +IN and −IN inputs is captured on
the internal capacitor array. The voltage on the −IN input is limited to between –0.2 V and 0.2 V, thus allowing
the input to reject a small signal which is common to both the +IN and −IN inputs. The +IN input has a range
of –0.2 V to (+Vref +0.2 V). The input span (+IN – (−IN)) is limited from 0 V to VREF.
The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, signal
frequency, and source impedance. Essentially, the current into the ADS7890 charges the internal capacitor
array during the sample period. After this capacitance has been fully charged, there is no further input current
(this may not happen when a signal is moving continuously). The source of the analog input voltage must be
able to charge the input capacitance (27 pF) to better than a 14-bit settling level with a step input within the
acquisition time of the device. The step size can be selected equal to the maximum voltage difference between
two consecutive samples at the maximum signal frequency. (Refer to Figure 39 for the suggested input circuit.)
When the converter goes into hold mode, the input impedance is greater than 1 GΩ.
Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, both
−IN and +IN inputs should be within the limits specified. Outside of these ranges, the converter’s linearity may
not meet specifications.
Care should be taken to ensure that +IN and −IN see the same impedance to the respective sources. (For
example, both +IN and −IN are connected to a decoupling capacitor through a 21-Ω resistor as shown in
Figure 39.) If this is not observed, the two inputs could have different settling times. This may result in an offset
error, gain error, or linearity error which changes with temperature and input voltage.
RECOMMENDED OPERATIONAL AMPLIFIERS
It is recommended to use the THS4031 or THS4211 for the analog input. All of the performance figures in this
data sheet are measured using the THS4031. Refer to Figure 39 for more information.
DIGITAL INTERFACE
The device can operate in SPI or DSP interface mode. A busy signal is available to indicate a conversion is in
progress apart from CS, SCLK in SPI and CS, SCLK, and FS in DSP mode.
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SLAS409 − DECEMBER 2003
TIMING AND CONTROL
Refer to the DEVICE OPERATION IN SPI INTERFACE, DEVICE OPERATION IN DSP INTERFACE and
FRAME ABORT in the DESCRIPTION AND TIMING sections.
READING DATA
The ADS7890 outputs serial data in straight binary format as listed in Table 1. Also refer to Figure 1 and Figure
2 for more details.
Table 1. Ideal Input Voltages and Output Codes(1)
DESCRIPTION
Full scale
Midscale
Midscale − 1 LSB
ANALOG VALUE
BINARY CODE
HEX CODE
Vref − 1 LSB
Vref/2
11 1111 1111 1111
3FFF
10 0000 0000 0000
2000
Vref/2 − 1 LSB
0V
01 1111 1111 1111
1FFF
Zero
00 0000 0000 0000
000
(1) Full-scale range = Vref and least significant bit (LSB) = Vref/16384
Reset
Refer to the POWERDOWN/RESET section for the device reset sequence.
It is recommended to reset the device after power on. A reset can be issued once the power has reached 95%
of its final value.
PWD/RST is an asynchronous active low input signal. A current conversion is aborted no later than 45 ns after
the converter is in the reset mode. In addition, the device output SDO goes to three-state. The converter returns
back to normal operation mode immediately after the PWD/RST input is brought high.
Data is not valid for the first four conversions after a device reset.
Powerdown
Refer to the POWERDOWN/RESET section for the device powerdown sequence.
The device enters powerdown mode if a PWD/RST low duration is extended for more than a period of tw4.
The converter goes back to normal operation mode no later than a period of td6 after the PWD/RST input is
brought high.
After this period, normal conversion and sampling operation can be started as discussed in previous sections.
Data is not valid for the first four conversions after a device reset.
Nap Mode
The device enters nap mode at the end of every conversion (with BUSY falling edge). The device powers up
again on the 8th SDO rising edge in the next frame. Refer to Figure 1 and Figure 2 for more information. The
power dissipation during nap mode is 10 mW. This offers power savings when the device is operated at lower
throughput. Refer to Figure 28 for more information on power saving.
21
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SLAS409 − DECEMBER 2003
APPLICATION INFORMATION
LAYOUT
For optimum performance, care should be taken with the physical layout of the ADS7890 circuitry.
As the ADS7890 offers single-supply operation, it is often used in close proximity with digital logic,
micro-controllers, microprocessors, and digital signal processors. The more digital logic present in the design
and the higher the switching speed, the more difficult it is to achieve acceptable performance from the converter.
The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground
connections, and digital inputs that occur just prior to the end of sampling (close to the 16th SCLK falling edge)
and just prior to latching the output of the analog comparator during the conversion phase. Thus, driving any
single conversion for an n-bit SAR converter, there are n+1 windows in which large external transient voltages
can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital
logic, or high power devices.
The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the
external event.
On average, the ADS7890 draws very little current from an external reference as the reference voltage is
internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive
the bypass capacitor or capacitors without oscillation. A 0.1-µF bypass capacitor and 1-µF storage capacitor
are recommended from REFIN (pin 1) directly to REFM (pin 48).
The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the analog
ground. Avoid connections which are too close to the grounding point of a micro-controller or digital signal
processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal
layout consists of an analog ground plane dedicated to the converter and associated analog circuitry.
As with the AGND connections, +VA should be connected to a 5-V power supply plane that is separate from
the connection for +VBD and digital logic until they are connected at the power entry point onto the PCB. Power
to the ADS7890 should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as
close to the device as possible. See Table 2 for the placement of capacitor. In addition to a 0.1-µF capacitor,
a 1-µF capacitor is recommended. In some situations, additional bypassing may be required, such as a 100-µF
electrolytic capacitor or even a Pi filter made up of inductors and capacitors, all designed to essentially low-pass
filter the 5-V supply, removing the high frequency noise.
Table 2. Power Supply Decoupling Capacitor Placement
POWER SUPPLY PLANE
CONVERTER ANALOG SIDE
SUPPLY PINS
Pairs of pins that require a shortest path to decoupling
capacitors
(4,5), (9,8), (10,11), (13, 15), (43, 44) (46, 45)
Pins that require no decoupling
14, 12
Analog 5 V
+VA
0.1 µF
1 µF
ADS7890
AGND
AGND
0.1 µF
REFOUT
External
Reference in
REFIN
1 µF
0.1 µF
REFM
AGND
21 Ω
Analog Input
Circuit
21 Ω
+IN
−IN
Figure 37. Using External Reference
22
CONVERTER DIGITAL SIDE
(24, 25), (34, 35)
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SLAS409 − DECEMBER 2003
Analog 5 V
+VA
0.1 µF
1 µF
ADS7890
AGND
AGND
REFOUT
0.1 µF
1 µF
REFIN
REFM
AGND
21 Ω
Analog Input
Circuit
21 Ω
+IN
−IN
Figure 38. Using Internal Reference
130 pF
1 kΩ
Bipolar Signal Input (+1.25 Vp−p)
2.5 V DC
1 kΩ
_
100 Ω
3 kΩ
1 kΩ
12 Ω
21 Ω
THS4031
+
1 nF
21 Ω
680 pF
+IN
ADS7890
−IN
AGND
AGND
Figure 39. Typical Analog Input Circuit
23
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
0°– 7°
1,05
0,95
Seating Plane
0,75
0,45
0,08
1,20 MAX
4073176 / B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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