TI THS4275DGN

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SLOS397E − JULY 2002 − REVISED JANUARY 2004
FEATURES
D Unity Gain Stability
D Low Voltage Noise
D
D
D
D
D
D
APPLICATIONS
D
D
D
D
D
− 3 nV/√Hz
High Slew Rate: 1000 V/µs
Low Distortion
− −92 dBc THD at 30 MHz
Wide Bandwidth: 1.4 GHz
Supply Voltages
− +5 V, ±5 V, +12 V, +15 V
Power Down Functionality (THS4275)
Evaluation Module Available
High Linearity ADC Preamplifier
Wireless Communication Receivers
Differential to Single-Ended Conversion
DAC Output Buffer
Active Filtering
THS4271
NC
IN−
IN+
VS−
DESCRIPTION
The THS4271 and THS4275 are low-noise, high slew rate,
unity gain stable voltage feedback amplifiers designed to
run from supply voltages as low as 5 V and as high as 15 V.
The THS4275 offers the same performance as the
THS4271 with the addition of power down capability. The
combination of low-noise, high slew rate, wide bandwidth,
low distortion, and unity gain stability make the THS4271
and THS4275 high performance devices across multiple
ac specifications.
+
VI
49.9 Ω
THS4271
_
−5 V
249 Ω
249 Ω
VO
3
6
4
5
NC
VS+
VOUT
NC
DESCRIPTION
THS4211
1-GHz voltage feedback amplifier
THS4503
Wideband fully differential amplifier
THS3202
Dual, wideband current feedback amplifier
Harmonic and Intermodulation Distortion − dB
50 Ω
7
DEVICE
Low-Noise, Low-Distortion, Wideband Application Circuit
+5 V
8
2
RELATED DEVICES
Designers using the THS4271 are rewarded with higher
dynamic range over a wider frequency band without the
stability concerns of decompensated amplifiers. The
devices are available in SOIC, MSOP with PowerPAD,
and leadless MSOP with PowerPAD packages.
50 Ω Source
1
HARMONIC AND INTERMODULATION
DISTORTION
vs
FREQUENCY
−40
Gain = 2
Rf = 249 Ω
RL = 150 Ω
VO = 2 VPP
VS = ±5 V
−50
−60
IMD3
200 kHz Tone Spacing
VO = 2 VPP Envelope
−70
−80
HD2
−90
HD3
−100
1
10
f − Frequency − MHz
100
NOTE: Power supply decoupling capacitors not shown
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
!" #$%&'()* %$)*+!)" !),$-'+*!$) $) .-$#&%*" !) '$-( *+) $)( .+"( $,
#(/(0$.'()*1 ( "*+*&" $, (+% #(/!%( !" !)#!%+*(# $) *( .+2(3"4 ".(%!,5!)2 !*"
(0(%*-!%+0 %+-+%*(-!"*!%"1
Copyright  2002 − 2004, Texas Instruments Incorporated
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SLOS397E − JULY 2002 − REVISED JANUARY 2004
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
16.5 V
Supply voltage, VS
±VS
Input voltage, VI
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
100 mA
Output current, IO
Continuous power dissipation
See Dissipation Rating Table
PACKAGE DISSIPATION RATINGS
150°C
Maximum junction temperature, TJ
Maximum junction temperature, continuous
operation, long term reliability TJ (2)
PACKAGE
θJC
(°C/W)
θJA(1)
(°C/W)
D (8 pin)
38.3
DGN (8 pin)(3)
4.7
125°C
−65°C to 150°C
Storage temperature range, Tstg
Lead temperature
1,6 mm (1/16 inch) from case for 10 seconds
ESD ratings:
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
300°C
HBM
3000 V
CDM
1500 V
MM
1000 V
(1)
The absolute maximum temperature under any condition is
limited by the constraints of the silicon process. Stresses above
these ratings may cause permanent damage. Exposure to
absolute maximum conditions for extended periods may degrade
device reliability. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond
those specified is not implied.
(2) The maximum junction temperature for continuous operation is
limited by package constraints. Operation above this temperature
may result in reduced reliability and/or lifetime of the device.
POWER RATING(2)
97.5
TA ≤ 25°C
1.02 W
TA = 85°C
410 mW
58.4
1.71 W
685 mW
DGK (8 pin)
54.2
260
385 mW
154 mW
DRB (8 pin)(3)
5
45.8
2.18 W
873 mW
(1) This data was taken using the JEDEC standard High-K test PCB.
(2) Power rating is determined with a junction temperature of 125°C.
This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the
junction temperature at or below 125°C for best performance and
long term reliability.
(3)
The THS4271/5 may incorporate a PowerPAD on the underside
of the chip. This acts as a heat sink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure
to do so may result in exceeding the maximum junction
temperature which could permanently damage the device. See TI
technical briefs SLMA002 and SLMA004 for more information
about utilizing the PowerPAD thermally enhanced package.
RECOMMENDED OPERATING CONDITIONS
Supply voltage, (VS+ and VS−)
MIN
MAX
Dual supply
±2.5
±7.5
Single supply
5
15
VS− + 1.4
VS+ − 1.4
Input common-mode voltage range
UNIT
V
V
PACKAGING/ORDERING INFORMATION
ORDERABLE PACKAGE AND NUMBER
PLASTIC
SMALL OUTLINE
(D) (1)
LEADLESS MSOP 8 (2)
(DRB)
PLASTIC MSOP (1)
PowerPAD
(DGN)
THS4271D
THS4271DRBT
THS4271DGN
THS4271DR
THS4271DRBR
THS4271DGNR
THS4275D
THS4275DRBT
THS4275DGN
THS4275DR
THS4275DRBR
THS4275DGNR
PLASTIC MSOP (1)
PACKAGE
MARKING
(DGK)
PACKAGE
MARKING
THS4271DGK
BFQ
THS4271DGKR
BEY
THS4275DGK
BFR
THS4275DGKR
BJD
(1) All packages are available taped and reeled. The R suffix standard quantity is 2500 (e.g., THS4271DGNR).
(2) All packages are available taped and reeled. The R suffix standard quantity is 3000. The T suffix standard quantity is 250 (e.g., THS4271DRBT).
2
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SLOS397E − JULY 2002 − REVISED JANUARY 2004
PIN ASSIGNMENTS
(TOP VIEW)
D, DRB, DGN, DGK
(TOP VIEW)
D, DRB, DGN, DGK
THS4271
NC
IN−
IN+
VS−
1
8
2
7
3
6
4
5
THS4275
NC
VS+
VOUT
NC
REF
IN−
IN+
VS−
1
8
2
7
3
6
4
5
PD
VS+
VOUT
NC
NC − No internal connection
ELECTRICAL CHARACTERISTICS VS = ±5 V
RF = 249 Ω, RL = 499 Ω, G = +2, unless otherwise noted.
TYP
PARAMETER
TEST CONDITIONS
25°C
OVER TEMPERATURE
25°C
0°C TO
70°C
−40°C
TO 85°C
UNITS
MIN/
TYP/
MAX
AC PERFORMANCE
G = 1, VO = 100 mVPP, RL = 150 Ω
1.4
GHz
Typ
G = −1, VO = 100 mVPP
400
MHz
Typ
G = 2, VO = 100 mVPP
390
MHz
Typ
G = 5, VO = 100 mVPP
85
MHz
Typ
G = 10, VO = 100 mVPP
40
MHz
Typ
0.1 dB flat bandwidth
G = 1, VO = 100 mVPP, RL = 150 Ω
200
MHz
Typ
Gain bandwidth product
G > 10, f = 1 MHz
400
MHz
Typ
Full-power bandwidth
G = −1, VO = 2 Vp
80
MHz
Typ
G = 1, VO = 2 V Step
950
V/µs
Typ
G = −1, VO = 2 V Step
1000
V/µs
Typ
Settling time to 0.1%
G = −1, VO = 4 V Step
25
ns
Typ
Settling time to 0.01%
G = −1, VO = 4 V Step
38
ns
Typ
Harmonic distortion
G = 1, VO = 1 VPP, f = 30 MHz
Second harmonic distortion
RL = 150 Ω
RL = 499 Ω
−92
dBc
Typ
−80
dBc
Typ
Third harmonic distortion
RL = 150 Ω
RL = 499 Ω
−95
dBc
Typ
−95
dBc
Typ
Harmonic distortion
G = 2, VO = 2 VPP, f = 30 MHz
Second harmonic distortion
RL = 150 Ω
RL = 499 Ω
−65
dBc
Typ
−70
dBc
Typ
Third harmonic distortion
RL = 150 Ω
RL = 499 Ω
−80
dBc
Typ
−90
dBc
Typ
Third order intermodulation (IMD3)
G = 2, VO = 2 VPP, RL = 150 Ω,
f = 70 MHz
−60
dBc
Typ
Third order output intercept (OIP3)
G = 2, VO = 2 VPP, RL = 150 Ω,
f = 70 MHz
35
dBm
Typ
Differential gain (NTSC, PAL)
G = 2, RL = 150 Ω,
0.007%
Differential phase (NTSC, PAL)
G = 2, RL = 150 Ω,
0.004
_
Typ
Input voltage noise
f = 1 MHz
3
nV/√Hz
Typ
Input current noise
f = 1 MHz
3
pA√Hz
Typ
Small signal bandwidth
Slew rate
Typ
3
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SLOS397E − JULY 2002 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS VS = ±5 V (continued)
RF = 249 Ω, RL = 499 Ω, G = +2, unless otherwise noted.
TYP
PARAMETER
TEST CONDITIONS
OVER TEMPERATURE
−40°C to
85°C
MIN/
TYP/
MAX
25°C
25°C
0°C to
70°C
75
65
60
60
dB
Min
5
10
12
12
mV
Max
±10
±10
µV/°C
Typ
Max
UNITS
DC PERFORMANCE
Open-loop voltage gain (AOL)
Input offset voltage
Average offset voltage drift
Input bias current
Average bias current drift
Input offset current
Average offset current drift
VO = ± 50 mV, RL = 499 Ω
VCM = 0 V
VCM = 0 V
VCM = 0 V
6
VCM = 0 V
VCM = 0 V
1
15
6
VCM = 0 V
18
18
µA
±10
±10
nA/°C
Typ
8
8
µA
Max
±10
±10
nA/°C
Typ
INPUT CHARACTERISTICS
Common-mode input range
Input resistance
VCM = ± 2 V
Common-mode
Input capacitance
Common-mode / differential
Common-mode rejection ratio
±4
±3.6
±3.5
±3.5
V
Min
72
67
65
65
dB
Min
5
MΩ
Typ
0.4/0.8
pF
Typ
OUTPUT CHARACTERISTIC8
Output voltage swing
G = +2
±4
±3.8
±3.7
±3.7
V
Min
Output current (sourcing)
160
120
110
110
mA
Min
Output current (sinking)
RL = 10 Ω
RL = 10 Ω
80
60
50
50
mA
Min
Output impedance
f = 1 MHz
0.1
Ω
Typ
POWER SUPPLY
Specified operating voltage
±5
±7.5
±7.5
±7.5
V
Max
Maximum quiescent current
22
24
27
28
mA
Max
Minimum quiescent current
22
20
18
15
mA
Min
85
75
70
70
dB
Min
75
65
60
60
dB
Min
Power supply rejection (+PSRR)
Power supply rejection (−PSRR)
VS+ = 5.5 V to 4.5 V, VS− = 5 V
VS+ = 5 V,
VS− = −5.5 V to −4.5 V
POWER-DOWN CHARACTERISTICS (THS4275 only)
Power-down voltage level(1)
Power-down quiescent current
REF = 0 V,
or VS−
Enable
REF+1.8
V
Min
Power down
REF+1
V
Max
REF = VS+ or
Floating
Enable
REF−1
V
Min
V
Max
PD = Ref +1.0 V, Ref = 0 V
Power down
875
REF−1.7
1000
1100
1200
µA
Max
PD = Ref −1.7 V, Ref = VS+
650
800
900
1000
µA
Max
Turnon time delay(t(ON))
50% of final supply current value
4
µs
Typ
Turnoff time delay (t(OFF))
50% of final supply current value
3
µs
Typ
Input impedance
f = 1 MHz
4
GΩ
Typ
200
kΩ
Typ
Output impedance
(1) For detail information on the power-down circuit, see the powerdown section in the application information of this data sheet.
4
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SLOS397E − JULY 2002 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS VS = 5 V
RF = 249 Ω, RL = 499 Ω, G = +2, unless otherwise noted
TYP
PARAMETER
TEST CONDITIONS
25°C
OVER TEMPERATURE
25°C
0°C to
70°C
−40°C to
85°C
UNITS
MIN/
TYP/
MAX
AC PERFORMANCE
Small signal bandwidth
G = 1, VO = 100 mVPP, RL = 150 Ω
1.2
GHz
Typ
G = −1, VO = 100 mVPP
380
MHz
Typ
G = 2, VO = 100 mVPP
360
MHz
Typ
G = 5, VO = 100 mVPP
80
MHz
Typ
G = 10, VO = 100 mVPP
35
MHz
Typ
0.1-dB flat bandwidth
G = 1, VO = 100 mVPP, RL = 150 Ω
120
MHz
Typ
Gain bandwidth product
G > 10 , f = 1 MHz
350
MHz
Typ
Full-power bandwidth
G = −1, VO = 2 Vp
60
MHz
Typ
G = 1, VO = 2 V Step
700
V/µs
Typ
G = −1, VO = 2 V Step
750
V/µs
Typ
Settling time to 0.1%
G = −1, VO = 2 V Step
18
ns
Typ
Settling time to 0.01%
G = −1, VO = 2 V Step
66
ns
Typ
Harmonic distortion
G = 1, VO = 1 VPP, f = 30 MHz
Second harmonic distortion
RL = 150 Ω
RL = 499 Ω
−75
dBc
Typ
−72
dBc
Typ
Third harmonic distortion
RL = 150 Ω
RL = 499 Ω
−70
dBc
Typ
−70
dBc
Typ
Third order intermodulation (IMD3)
G = 2, VO = 1 VPP, RL = 150 Ω,
f = 70 MHz
−65
dBc
Typ
Third order output intercept (OIP3)
G = 2, VO = 1 VPP, RL = 150 Ω,
f = 70 MHz
32
dBm
Typ
Input voltage noise
f = 1 MHz
3
nV/√Hz
Typ
Input current noise
f = 10 MHz
3
pA/√Hz
Typ
VO = ± 50 mV, RL = 499 Ω
VCM = VS/2
68
63
60
60
dB
Min
5
10
12
12
mV
Max
VCM = VS/2
VCM = VS/2
±10
±10
µV/°C
Typ
6
15
18
18
µA
Max
VCM = VS/2
VCM = VS/2
±10
±10
nA/°C
Typ
1
6
8
8
µA
Max
±10
±10
nA/°C
Typ
Slew rate
DC PERFORMANCE
Open-loop voltage gain (AOL)
Input offset voltage
Average offset voltage drift
Input bias current
Average bias current drift
Input offset current
Average offset current drift
VCM = VS/2
INPUT CHARACTERISTICS
Common-mode input range
1/4
1.3/3.7
1.4/3.6
1.5/3.5
V
Min
72
67
65
65
dB
Min
Input resistance
VCM = ± 0.5 V, VO = 2.5 V
Common-mode
5
MΩ
Typ
Input capacitance
Common-mode / differential
0.4/0.8
pF
Typ
Output voltage swing
G = +2
1.2/3.8
1.4/3.6
1.5/3.5
1.5/3.5
V
Min
Output current (sourcing)
120
100
90
90
mA
Min
Output current (sinking)
RL = 10 Ω
RL = 10 Ω
65
50
40
40
mA
Min
Output impedance
f = 1 MHz
0.1
Ω
Typ
Common-mode rejection ratio
OUTPUT CHARACTERISTICS
5
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SLOS397E − JULY 2002 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS VS = 5 V (continued)
RF = 249 Ω, RL = 499 Ω, G = +2, unless otherwise noted
TYP
PARAMETER
OVER TEMPERATURE
UNITS
MIN/
TYP/
MAX
15
V
Max
27
mA
Max
16
14
mA
Min
75
62
62
dB
Min
65
60
60
dB
Min
REF+1.8
V
Min
Power-down
REF+1
V
Max
Enable
REF−1
V
Min
REF−1.7
V
Max
TEST CONDITIONS
25°C
25°C
0°C to
70°C
Specified operating voltage
5
15
15
Maximum quiescent current
20
22
25
Minimum quiescent current
20
18
85
75
−40°C to
85°C
POWER SUPPLY
Power supply rejection (+PSRR)
Power supply rejection (−PSRR)
VS+ = 5.5 V to 4.5 V, VS− = 0 V
VS+ = 5 V, VS− = −0.5 V to 0.5 V
POWER-DOWN CHARACTERISTICS (THS4275 Only)
Enable
REF = 0 V, or VS−
Power-down voltage level(1)
REF = VS+ or Floating
Power-down quiescent current
Power-down
PD = Ref +1.0 V, Ref = 0 V
650
800
900
1000
µA
Max
PD = Ref −1.7 V, Ref = VS+
650
800
900
1000
µA
Max
µs
Typ
Turnon time delay(t(ON))
50% of final value
4
Turnoff time delay (t(OFF))
50% of final value
3
µs
Typ
Input impedance
f = 1 MHz
6
GΩ
Typ
100
kΩ
Typ
Output impedance
(1) For detail information on the power-down circuit, see the powerdown section in the application information of this data sheet.
6
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SLOS397E − JULY 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS
Table of Graphs (±5 V)
FIGURE
Small signal unity gain frequency response
1
Small signal frequency response
2
0.1-dB gain flatness frequency response
3
Large signal frequency response
4
Slew rate vs Output voltage
5
Harmonic distortion vs Frequency
Harmonic distortion vs Output voltage swing
6, 7, 8, 9
10, 11, 12, 13
Third order intermodulation distortion vs Frequency
14, 16
Third order intercept point vs Frequency
15, 17
Voltage and current noise vs Frequency
18
Differential gain vs Number of loads
19
Differential phase vs Number of loads
20
Settling time
21
Quiescent current vs Supply voltage
22
Output voltage vs Load resistance
23
Frequency response vs Capacitive load
24
Open-loop gain and phase vs Frequency
25
Open-loop gain vs Case temperature
26
Rejection ratios vs Frequency
27
Rejection ratios vs Case temperature
28
Common-mode rejection ratio vs Input common-mode range
29
Input offset voltage vs Case temperature
30
Input bias and offset current vs Case temperature
31
Small signal transient response
32
Large signal transient response
33
Overdrive recovery
34
Closed-loop output impedance vs Frequency
35
Power-down quiescent current vs Supply voltage
36
Power-down output impedance vs Frequency
37
Turnon and turnoff delay times
38
7
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SLOS397E − JULY 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS
Table of Graphs (5 V)
FIGURE
Small signal unity gain frequency response
39
Small signal frequency response
40
0.1-dB gain flatness frequency response
41
Large signal frequency response
42
Slew rate vs Output voltage
43
Harmonic distortion vs Frequency
44, 45, 46, 47
Harmonic distortion vs Output voltage swing
48, 49, 50, 51
Third order intermodulation distortion vs Frequency
52, 54
Third order intercept point vs Frequency
53, 55
Voltage and current noise vs Frequency
56
Settling time
57
Quiescent current vs Supply voltage
58
Output voltage vs Load resistance
59
Frequency response vs Capacitive load
60
Open-loop gain and phase vs Frequency
61
Open-loop gain vs Case temperature
62
Rejection ratios vs Frequency
63
Rejection ratios vs Case temperature
64
Common-mode rejection ratio vs Input common-mode range
65
Input offset voltage vs Case temperature
66
Input bias and offset current vs Case temperature
67
Small signal transient response
68
Large signal transient response
69
Overdrive recovery
70
Closed-loop output impedance vs Frequency
71
Power-down quiescent current vs Supply voltage
72
Power-down output impedance vs Frequency
73
Turnon and turnoff delay times
74
8
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SLOS397E − JULY 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (±5 V GRAPHS)
SMALL SIGNAL UNITY GAIN
FREQUENCY RESPONSE
18
1
0
−1
−2
−4
100 k
1M
10 M
1G
100 M
16
Gain = 5
14
RL = 499 Ω
Rf = 249 Ω
VO = 100 mVPP
VS = ±5 V
12
10
8
6
Gain = 2
4
2
0
Gain = −1
−2
−4
100 k
1M
−3
10 G
0
Gain = 10
f − Frequency − Hz
Figure 1
10 M
100 M
f − Frequency − Hz
RL = 499 Ω
Rf = 249 Ω
VO = 1 VPP
VS = ±5 V
6
Rise
600
400
Gain = −1
RL = 499 Ω
Rf = 249 Ω
VS = ±5 V
1G
0
f − Frequency − Hz
Figure 4
Harmonic Distortion − dBc
HD3, RL = 499Ω
−80
HD3, RL = 150Ω
HD2, RL = 499Ω
0.5
1
1.5
2
2.5
3
3.5
4 4.5
Figure 7
1
5
10
f − Frequency − MHz
100
100
Figure 6
HARMONIC DISTORTION
vs
FREQUENCY
−50
Gain = 2
Rf = 249 Ω
VO = 1 VPP
VS = ±5 V
−60
−70
HD3, RL = 499Ω
HD3, RL = 150Ω
−80
HD2, RL = 499Ω
HD2, RL = 150Ω
−90
−100
−100
10
f − Frequency − MHz
HD2, RL = 150Ω
HD2, RL = 499Ω
−90
−50
HD2, RL = 150Ω
1
−80
HARMONIC DISTORTION
vs
FREQUENCY
Gain = 1
VO = 2 VPP
VS = ±5 V
−90
HD3, RL = 499Ω
HD3, RL = 150Ω
Figure 5
−50
−70
−70
VO − Output Voltage − V
HARMONIC DISTORTION
vs
FREQUENCY
1G
Gain = 1
VO = 1 VPP
VS = ±5 V
−60
Harmonic Distortion − dBc
100 M
100 M
−100
0
10 M
10 M
HARMONIC DISTORTION
vs
FREQUENCY
800
200
1M
1M
−50
2
−60
Gain = 1
RL = 150 Ω
VO = 100 mVPP
VS = ±5 V
Figure 3
Gain = 2
0
100 k
−0.7
f − Frequency − Hz
Harmonic Distortion − dBc
SR − Slew Rate − V/ µ s
14
4
−0.6
−1
100 k
1G
1000
Gain = 5
8
−0.5
Fall
Gain = 10
10
−0.4
−0.9
1200
12
−0.3
−0.8
20
16
−0.2
SLEW RATE
vs
OUTPUT VOLTAGE
22
18
−0.1
Figure 2
LARGE SIGNAL FREQUENCY RESPONSE
Large Signal Gain − dB
Small Signal Gain − dB
2
20
Small Signal Gain − dB
Small Signal Gain − dB
0.1
22
Gain = 1
RL = 150 Ω
VO = 100 mVPP
VS = ±5 V
3
Harmonic Distortion − dBc
0.1 dB GAIN FLATNESS
FREQUENCY RESPONSE
SMALL SIGNAL FREQUENCY RESPONSE
4
Gain = 2
Rf = 249 Ω
VO = 2 VPP
VS = ±5 V
HD3, RL = 499Ω
−60
−70
HD2, RL = 499Ω
HD3, RL = 150Ω
−80
HD2, RL = 150Ω
−90
−100
1
10
f − Frequency − MHz
Figure 8
100
1
10
f − Frequency − MHz
100
Figure 9
9
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SLOS397E − JULY 2002 − REVISED JANUARY 2004
−50
−50
−60
−70
Harmonic Distortion − dBc
Gain = 1
f= 8 MHz
VS = ±5 V
HD3, RL = 150Ω
HD3, RL = 499Ω
−80
HD2, RL = 499Ω
HD2, RL = 150Ω
−90
−60
Gain = 1
f= 32 MHz
VS = ±5 V
−70
HD2, RL = 150Ω
Gain = 2
Rf = 249 Ω
f = 8 MHz
VS = ±5 V
HD2, RL = 499Ω
−60
Harmonic Distortion − dBc
−50
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HD3, RL = 150Ω
−80
−90
HD3, RL = 499Ω
−70
HD2, RL = 499Ω
HD3, RL = 150Ω
−80
HD2, RL = 150Ω
−90
HD3, RL = 499Ω
−100
−100
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VO − Output Voltage Swing − VPP
1
2
3
4
VO − Output Voltage Swing − VPP
Figure 10
HD3,
RL = 150Ω
−90
HD3,
RL = 499Ω
−100
0
1
2
3
4
VO − Output Voltage Swing − VPP
5
−40
55
Gain = 1
RL = 150 Ω
VS = ±5 V
200 kHz Tone Spacing
−50
−60
−70
VO = 2 VPP
−80
−90
VO = 1 VPP
−100
10
35
30
0
20
40
60
f − Frequency − MHz
50
−60
VO = 2 VPP
−70
−80
VO = 1 VPP
−90
−100
10
100
100
VO = 2 VPP
45
40
Gain = 2
RL = 150 Ω
VS = ±5 V
200 kHz Tone Spacing
VO = 1 VPP
35
30
0
20
40
60
f − Frequency − MHz
Figure 17
80
100
Hz
Gain = 2
RL = 150 Ω
VS = ±5 V
200 kHz Tone Spacing
100
VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
Vn − Voltage Noise − nV/
−40
80
Figure 15
THIRD ORDER OUTPUT INTERCEPT
POINT
vs
FREQUENCY
Third-Order Output Intersept Point − dBm
Third-Order Intermodulation Distortion − dBc
VO = 1 VPP
40
Figure 14
f − Frequency − MHz
10
VO = 2 VPP
45
f − Frequency − MHz
THIRD ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
Figure 16
Gain = 1
RL = 150 Ω
VS = ±5 V
200 kHz Tone Spacing
50
100
Figure 13
−50
THIRD ORDER OUTPUT INTERCEPT
POINT
vs
FREQUENCY
Hz
−80
Third-Order Intermodulation Distortion − dBc
Harmonic Distortion − dBc
−70
5
Figure 12
THIRD ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
Gain = 2
Rf = 249 Ω
f = 32 MHz
HD2, RL = 499Ω
VS = ±5 V
HD2, RL = 150Ω
−60
0.5 1 1.5 2 2.5 3 3.5 4 4.5
VO − Output Voltage Swing − VPP
Figure 11
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
−50
0
5
Third-Order Output Intersept Point − dBm
0
100
Vn
10
10
In
1
100
1k
10 k
100 k
1M
f − Frequency − Hz
Figure 18
10 M
I n − Current Noise − pA/
−100
1
100 M
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SLOS397E − JULY 2002 − REVISED JANUARY 2004
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
0.015
Differential Phase −
0.020
°
NTSC
0.010
Rising Edge
Gain = 2
Rf = 1.3 kΩ
VS = ±5 V
40 IRE − NTSC and Pal
Worst Case ±100 IRE Ramp
0.09
0.08
0.07
2
VO − Output Voltage − V
Gain = 2
Rf = 1.3 kΩ
VS = ±5 V
40 IRE − NTSC and Pal
Worst Case ±100 IRE Ramp
0.025
Differential Gain − %
SETTLING TIME
3
0.10
0.030
0.06
0.05
PAL
0.04
0.03
NTSC
0.005
Gain = −1
RL = 499 Ω
Rf = 249 Ω
f= 1 MHz
VS = ±5 V
0
−1
Falling Edge
−2
0.02
PAL
1
0.01
−3
0
0
1
2
3
4
5
6
7
0
8
0
Number of Loads − 150 Ω
1
2
4
5
6
7
0
8
0.5
4
VO − Output Voltage − V
TA = 25°C
20
TA = −40°C
15
10
5
0
VS = ±5 V
TA = −40 to 85°C
3
2
Normalized Gain − dB
25
1
0
−1
−2
4
4.5
10
5
VS − Supply Voltage − ±V
100
1k
RL − Load Resistance − Ω
Figure 22
Gain
85
20
80
40
60
40
80
30
100
Phase
120
10
140
0
160
100 k
1M
10 M
f − Frequency − Hz
Figure 25
10 M
100 M
180
1G
100 M
Capacitive Load − Hz
Figure 24
REJECTION RATIOS
vs
FREQUENCY
100
VS = ±5 V
90
Phase − °
Open-Loop Gain − dB
0
50
−10
10 k
RL = 499 Ω
VS =±5 V
−3
1M
10 k
TA = −40°C
TA = 25°C
PSRR+
80
Rejection Ratios − dB
VS = ±5 V
20
−2
OPEN-LOOP GAIN
vs
CASE TEMPERATURE
Open-Loop Gain − dB
80
60
R(ISO) = 10 Ω CL = 50 pF
−1.5
Figure 23
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
70
R(ISO) = 15 Ω CL = 100 pF
−1
−2.5
−5
0
R(ISO) = 25 Ω CL = 10 pF
−0.5
−3
−4
3.5
25
FREQUENCY RESPONSE
vs
CAPACITIVE LOAD
5
TA = 85°C
3
20
Figure 21
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
30
2.5
10
15
t − Time − ns
Figure 20
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
2
5
Number of Loads − 150 Ω
Figure 19
Quiescent Current − mA
3
75
70
TA = 85°C
65
60
70
PSRR−
60
50
CMRR
40
30
20
55
50
10
0
2.5
3
3.5
4
Case Temperature − °C
Figure 26
4.5
5
10 k
100 k
1M
10 M
f − Frequency − Hz
100 M
Figure 27
11
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SLOS397E − JULY 2002 − REVISED JANUARY 2004
REJECTION RATIOS
vs
CASE TEMPERATURE
PSRR+
80
60
CMMR
40
20
0
−40−30−20−100 10 20 30 40 50 60 70 80 90
80
70
60
50
40
VS = ±5 V
TA = 25°C
30
20
−6
−4
−2
8
0
2
4
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
6
TC − Case Temperature − °C
Figure 30
SMALL SIGNAL TRANSIENT RESPONSE
1.17
LARGE SIGNAL TRANSIENT RESPONSE
0.3
1.5
0.2
1
IIB−
6
IOS
1.15
1.14
5
IIB+
4
1.13
3
1.12
2
1.11
1
1.1
0.1
0
Gain = −1
RL = 499 Ω
Rf = 249 Ω
tr/tf = 300 ps
VS = ±5 V
−0.1
−0.2
0
Gain = −1
RL = 499 Ω
Rf = 249 Ω
tr/tf = 300 ps
VS = ±5 V
−0.5
−1.5
0
2
4
TC − Case Temperature − °C
6
8
10
12
14 16
0
2
t − Time − ns
Figure 31
Figure 32
OVERDRIVE RECOVERY
3
2.5
4
2
3
1.5
2
1
1
0.5
0
0
−1
−0.5
−2
−1
−3
−1.5
−4
−2
−5
−2.5
−3
−6
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
t − Time − µs
1
100
Gain = 1
RL = 499 Ω
PIN = −1 dBm
VS = ±5 V
10
1
0.1
0.01
0.001
100 k
6 8 10 12 14
t − Time − ns
16 18
POWER-DOWN QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
1200
1000
VI − Input Voltage − V
Closed-Loop Output Impedance − Ω
VS = ±5 V
4
Figure 33
CLOSED-LOOP OUTPUT IMPEDANCE
vs
FREQUENCY
6
Figure 34
0.5
−1
−0.3
1.09
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
5
VO − Output Voltage − V
1.16
VO − Output Voltage − V
VS = ±5 V
I OS − Input Offset Current − µ A
I IB − Input Bias Current − µ A
1
Figure 29
INPUT BIAS AND OFFSET CURRENT
vs
CASE TEMPERATURE
Single-Ended Output Voltage − V
VS = ±5 V
2
Input Common-Mode Range − V
Figure 28
12
VS = 5 V
3
0
Case Temperature − °C
7
4
10
Power-down Quiescent Current − µ A
Rejection Ratios − dB
PSRR−
90
VOS − Input Offset Voltage − mV
VS = ±5 V
5
100
CMRR − Common-Mode Rejection Ratio − dB
120
100
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
TA = 85°C
1000
TA = 25°C
800
TA = −40°C
600
400
200
0
1M
10 M
100 M
f − Frequency − Hz
Figure 35
1G
2.5
3
3.5
4
4.5
VS − Supply Voltage − ±V
Figure 36
5
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SLOS397E − JULY 2002 − REVISED JANUARY 2004
TURNON AND TURNOFF TIMES DELAY TIME
Input
Gain = 1
RL = 150 Ω
VIN = 1 dBm
VS = ±5 V
I O− Output Current Level − mV
Power-down Output Impedance − Ω
100 k
6.5
45
1M
10 k
100
40
5
35
3.5
30
2
25
0.5
20
−1
15
10
0.5
Gain = −1
RL = 150 Ω
VS = ±5 V
0
1
100 k
1M
10 M
100 M
f − Frequency − Hz
Figure 37
1G
V I − Input Voltage Level − V
POWER-DOWN OUTPUT IMPEDANCE
vs
FREQUENCY
0
10
20
30
40
50
60
70
t − Time − µs
Figure 38
13
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SLOS397E − JULY 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (5 V GRAPHS)
SMALL SIGNAL UNITY GAIN
FREQUENCY RESPONSE
3
22
16
−1
−2
1M
10 M
100 M
1G
Gain = 5
14
RL = 499 Ω
Rf = 249 Ω
VO = 100 mVPP
VS = 5 V
12
10
8
6
Gain = 2
4
2
−3
−4
100 k
0
Gain = −1
−2
−4
100 k
1M
10 G
f − Frequency − Hz
Figure 39
RL = 499 Ω
Rf = 249 Ω
VO = 1 VPP
VS = 5 V
−0.6
−0.7
Gain = 2
Gain = 1
RL = 150 Ω
VO = 100 mVPP
VS = 5 V
1M
10 M
100 M
1G
f − Frequency − Hz
Figure 41
HARMONIC DISTORTION
vs
FREQUENCY
−50
800
700
600
Fall
Rise
500
400
300
200
Gain = 1
VO = 1 VPP
RL = 150 Ω
VS = 5 V
−60
−70
−80
HD3
HD2
−90
100
2
−100
0
0
100 k
1M
10 M
100 M
0
1G
f − Frequency − Hz
Figure 42
0.5
1
1.5
2
VO − Output Voltage −V
1
2.5
HARMONIC DISTORTION
vs
FREQUENCY
0
−50
−30
−40
−50
HD3
−60
−70
HD2
−80
−60
−70
−80
HD3
−90
HD2
−20
−30
−40
−50
−70
−90
−100
f − Frequency − MHz
Figure 45
100
−100
1
10
f − Frequency − MHz
Figure 46
100
HD3
−80
−100
10
HD2
−60
−90
1
Gain = 2
Rf = 249 Ω
RL = 150 Ω
VO = 2 VPP
VS = 5 V
−10
Gain = 2
Rf = 249 Ω
RL = 249 Ω
VO = 1 VPP
VS = 5 V
Harmonic Distortion − dBc
−20
Harmonic Distortion − dBc
Gain = 1
VO = 2 VPP
RL = 150 Ω
VS = 5 V
100
Figure 44
HARMONIC DISTORTION
vs
FREQUENCY
0
−10
10
f − Frequency − MHz
Figure 43
HARMONIC DISTORTION
vs
FREQUENCY
Harmonic Distortion − dBc
−0.5
−1
100 k
1G
6
4
14
10 M
100 M
f − Frequency − Hz
Harmonic Distortion − dBc
SR − Slew Rate − V/ µ s
Large Signal Gain − dB
Gain = 5
8
−0.4
−0.9
Gain = 1
RL = 499 Ω
Rf = 249 Ω
VS = 5 V
900
18
10
−0.3
−0.8
1000
Gain = 10
12
−0.2
SLEW RATE
vs
OUTPUT VOLTAGE
22
20
0
−0.1
Figure 40
LARGE SIGNAL FREQUENCY RESPONSE
14
Small Signal Gain − dB
0
0.1
Gain = 10
18
Small Signal Gain − dB
Small Signal Gain − dB
1
0.2
20
Gain = 1
RL = 150 Ω
VO = 100 mVPP
VS = 5 V
2
16
0.1 dB GAIN FLATNESS
FREQUENCY RESPONSE
SMALL SIGNAL FREQUENCY RESPONSE
1
10
f − Frequency − MHz
Figure 47
100
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SLOS397E − JULY 2002 − REVISED JANUARY 2004
−50
HD3,
RL = 499Ω
HD3,
RL = 150Ω
−80
HD2, RL
= 499Ω
−90
−60
HD3,
RL = 150Ω
−70
HD2, RL = 150Ω
−80
HD2, RL = 499Ω
−80
HD2, RL = 499Ω
−90
−100
−100
1
1.5
2
2.5
0
VO − Output Voltage Swing − VPP
0.5
1
1.5
2
VO − Output Voltage Swing − VPP
Figure 48
Third-Order Intermodulation Distortion − dBc
HD2, RL = 150Ω
HD3,
RL = 499Ω
−70
HD2, RL = 499Ω
−80
−90
−100
0
0.5
1
1.5
2
VO − Output Voltage Swing − VPP
−40
45
Gain = 1
RL = 150 Ω
VO = 1 VPP
VS = 5 V
200 kHz Tone
Spacing
−50
−60
−70
−80
−90
−100
10
2.5
100
Gain = 1
RL = 150 Ω
VO = 1 VPP
VS = 5 V
200 kHz Tone Spacing
25
20
0
20
Third-Order Output Intersept Point − dBm
−70
−80
−90
100
60
80
VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
100
Gain = 2
RL = 150 Ω
VO = 2 VPP
VS = 5 V
200 kHz Tone Spacing
40
35
30
25
0
20
40
100
Figure 53
45
Gain = 2
RL = 150 Ω
VO = 2 VPP
VS = 5 V
200 kHz Tone Spacing
40
f − Frequency − MHz
THIRD ORDER OUTPUT INTERCEPT
POINT
vs
FREQUENCY
−40
−100
10
30
Figure 52
THIRD ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
−60
35
f − Frequency − MHz
Figure 51
−50
40
60
f − Frequency − MHz
f − Frequency − MHz
Figure 54
Figure 55
80
100
Hz
−60
THIRD ORDER OUTPUT INTERCEPT
POINT
vs
FREQUENCY
Vn − Voltage Noise − nV/
−50
HD3, RL = 150Ω
2.5
Figure 50
THIRD ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
−30
−40
0.5
1
1.5
2
VO − Output Voltage Swing − VPP
Figure 49
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
Gain = 2
Rf = 249 Ω
f = 32 MHz
VS = 5 V
0
2.5
Third-Order Output Intersept Point − dBm
0.5
HD2, RL = 150Ω
−70
HD3, RL = 499Ω
−100
Harmonic Distortion − dBc
−60
HD3, RL = 150Ω
−90
HD2, RL = 150Ω
0
Gain = 2
Rf = 249 Ω
f = 8 MHz
VS = 5 V
Hz
−70
HD3,
RL = 499Ω
100
Vn
10
10
In
1
100
1k
10 k
100 k
1M
10 M
I n − Current Noise − pA/
−60
Gain = 1
f= 32 MHz
VS = 5 V
Harmonic Distortion − dBc
Gain = 1
f= 8 MHz
VS = 5 V
Harmonic Distortion − dBc
Harmonic Distortion − dBc
−50
−40
−50
Third-Order Intermodulation Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
1
100 M
f − Frequency − Hz
Figure 56
15
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SLOS397E − JULY 2002 − REVISED JANUARY 2004
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
SETTLING TIME
2
30
1.5
TA = 85°C
1.5
Rising Edge
25
Gain = −1
RL = 499 Ω
Rf = 249 Ω
f= 1 MHz
VS = 5 V
0.5
0
−0.5
Falling Edge
TA = 25°C
20
TA = −40°C
15
10
5
−1
6
8
2.5
3
Figure 57
4.5
−0.5
R(ISO) = 25 Ω, CL = 10 pF
−1
R(ISO) = 15 Ω, CL = 50 pF
−1.5
R(ISO) = 10 Ω, CL = 100 pF
−2
RL = 499 Ω
VS = 5 V
−3
10
100
80
30
100
Phase
120
TA = 85°C
65
60
0
160
55
−10
10 k
180
50
10 M
100 M
1G
2.5
3
120
VS = 5 V
PSRR+
Rejection Ratios − dB
100
PSRR−
60
CMRR
40
30
PSRR−
80
60
CMMR
40
20
20
VS = 5 V
100 k
1M
10 M
f − Frequency − Hz
100 M
0
−40−30−20−100 10 20 30 40 50 60 70 80 90
Case Temperature − °C
Figure 64
4
4.5
5
Figure 62
REJECTION RATIOS
vs
CASE TEMPERATURE
PSRR+
3.5
Case Temperature − °C
Figure 61
90
16
70
140
1M
TA = 25°C
75
10
100 k
TA = −40°C
f − Frequency − Hz
100
Figure 63
80
40
40
REJECTION RATIOS
vs
FREQUENCY
0
10 k
85
20
60
20
10 k
OPEN-LOOP GAIN
vs
CASE TEMPERATURE
50
Figure 60
10
100
1k
RL − Load Resistance − Ω
Figure 59
Gain
Capacitive Load − MHz
50
10
5
0
60
Open-Loop Gain − dB
Frequency Response − dB
4
VS = 5 V
70
0
Rejection Ratios − dB
3.5
80
70
−1
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
0.5
80
−0.5
Figure 58
FREQUENCY RESPONSE
vs
CAPACITIVE LOAD
1
0
VS − Supply Voltage − ±V
t − Time − ns
−2.5
VS = 5 V
TA = −40 to 85°C
0.5
−2
2
10 12 14 16 18 20 22 24
Phase − °
4
Open-Loop Gain − dB
0 2
1
−1.5
0
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
CMRR − Common-Mode Rejection Ratio − dB
−1.5
VO − Output Voltage − V
Quiescent Current − mA
VO − Output Voltage − V
1
100
VS = 5 V
90
80
70
60
50
40
30
20
10
0
0
1
2
3
4
5
Input Common-Mode Voltage Range − V
Figure 65
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SLOS397E − JULY 2002 − REVISED JANUARY 2004
INPUT BIAS AND OFFSET CURRENT
vs
CASE TEMPERATURE
5
8
I IB − Input Bias Current − µ A
3
VS = ±5 V
2
1
6
4
1.14
1.13
3
1.12
2
1.11
1
1.1
Gain = −1
RL = 499 Ω
Rf = 249 Ω
tr/tf = 300 ps
VS = 5 V
1.5
6
7
8 9
2
1
1
0.5
0
0
−1
−0.5
−2
−1
10 11
−1.5
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Power-down Output Impedance − Ω
TA = 25°C
TA = −40°C
600
400
200
2.5
3
3.5
4
4.5
VS − Supply Voltage − ±V
Figure 72
5
16
1
0.1
0.01
0.001
100 k
1M
10 M
100 M
1G
Figure 71
6.5
45
Gain = 1
RL = 150 Ω
PIN = −1 dBm
VS = 5 V
Input
10 k
100
40
5
35
3.5
30
2
25
0.5
20
−1
15
10
0.5
Gain = −1
RL = 150 Ω
VS = 5 V
0
0
14
f − Frequency − Hz
1M
800
12
POWER-DOWN OUTPUT IMPEDANCE
vs
TURNON AND TURNOFF TIMES DELAY TIME
FREQUENCY
1200
TA = 85°C
10
10
Figure 70
POWER-DOWN QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
8
Gain = 1
RL = 499 Ω
VIN = 1 dBm
VS = 5 V
100
t − Time − µs
Figure 69
6
1000
VS = 5 V
t − Time − ns
1000
4
CLOSED-LOOP OUTPUT IMPEDANCE
vs
FREQUENCY
−3
−1.5
5
2
1
100 k
10 M
100 M
1M
f − Frequency − Hz
Figure 73
1G
V I − Input Voltage Level − V
0
3 4
0
t − Time − ns
VI − Input Voltage − V
Closed-Loop Output Impedance − Ω
0.5
2
−0.2
OVERDRIVE RECOVERY
Single-Ended Output Voltage − V
1
1
Gain = −1
RL = 499 Ω
Rf = 249 Ω
tr/tf = 300 ps
VS = 5 V
−0.1
Figure 68
3
0
0
Figure 67
1.5
−1
0.1
TC − Case Temperature − °C
LARGE SIGNAL TRANSIENT RESPONSE
−0.5
0.2
−0.3
1.09
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Figure 66
VO − Output Voltage − V
1.15
IIB+
TC − Case Temperature − °C
Power-down Quiescent Current − µ A
IOS
5
0
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
1.16
IIB−
I O− Output Current Level − mV
VOS − Input Offset Voltage − mV
7
VS = 5 V
0.3
1.17
VS = 5 V
4
SMALL SIGNAL TRANSIENT RESPONSE
I OS − Input Offset Current − µ A
VO − Output Voltage − V
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
0
10
20
30
40
50
60
70
t − Time − µs
Figure 74
17
www.ti.com
SLOS397E − JULY 2002 − REVISED JANUARY 2004
APPLICATION INFORMATION
HIGH-SPEED OPERATIONAL AMPLIFIERS
The THS4271 and the THS4275 operational amplifiers set
new performance levels, combining low distortion, high
slew rates, low noise, and a unity-gain bandwidth in
excess of 1 GHz. To achieve the full performance of the
amplifier, careful attention must be paid to printed-circuit
board layout and component selection.
The THS4275 provides a power-down mode, providing the
ability to save power when the amplifier is inactive. A
reference pin is provided to allow the user the flexibility to
control the threshold levels of the power-down control pin.
Applications Section Contents
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Wideband, Noninverting Operation
Wideband, Inverting Gain Operation
Single Supply Operation
Saving Power With Power-Down Functionality and
Setting Threshold Levels With the Reference Pin
Power Supply Decoupling Techniques and
Recommendations
Using the THS4271 as a DAC Output Buffer
Driving an ADC With the THS4271
Active Filtering With the THS4271
Building a Low-Noise Receiver With the THS4271
Linearity: Definitions, Terminology, Circuit
Techniques and Design Tradeoffs
An Abbreviated Analysis of Noise in Amplifiers
Driving Capacitive Loads
Printed Circuit Board Layout Techniques for Optimal
Performance
Power Dissipation and Thermal Considerations
Performance vs Package Options
Evaluation Fixtures, Spice Models, and Applications
Support
Additional Reference Material
Mechanical Package Drawings
WIDEBAND, NONINVERTING OPERATION
The THS4271 and the THS4275 are unity gain stable
1.4-GHz voltage feedback operational amplifiers, with and
without power-down capability, designed to operate from
a single 5-V to 15-V power supply.
Figure 75 is the noninverting gain configuration of 2 V/V
used to demonstrate the typical performance curves. Most
of the curves were characterized using signal sources with
18
50-Ω source impedance, and with measurement
equipment presenting a 50-Ω load impedance. In
Figure 75, the 49.9-Ω shunt resistor at the VIN terminal
matches the source impedance of the test generator. The
total 499-Ω load at the output, combined with the 498-Ω
total feedback network load, presents the THS4271 and
THS4275 with an effective output load of 249 Ω for the
circuit of Figure 75.
Voltage feedback amplifiers, unlike current feedback
designs, can use a wide range of resistors values to set
their gain with minimal impact on their stability and
frequency response. Larger-valued resistors decrease the
loading effect of the feedback network on the output of the
amplifier, but this enhancement comes at the expense of
additional noise and potentially lower bandwidth.
Feedback resistor values between 249 Ω and 1 kΩ are
recommended for most situations.
5 V +V
S
+
100 pF
50 Ω Source
0.1 µF 6.8 µF
+
VI
VO
THS4271
49.9 Ω
_
Rf
249 Ω
499 Ω
249 Ω
Rg
0.1 µF 6.8 µF
100 pF
−5 V
+
−VS
Figure 75. Wideband, Noninverting Gain
Configuration
WIDEBAND, INVERTING GAIN OPERATION
Since the THS4271 and THS4275 are general-purpose,
wideband voltage-feedback amplifiers, several familiar
operational amplifier applications circuits are available to
the designer. Figure 76 shows a typical inverting
configuration where the input and output impedances and
noise gain from Figure 75 are retained in an inverting
circuit configuration. Inverting operation is one of the more
common requirements and offers several performance
benefits. The inverting configuration shows improved slew
rates and distortion due to the pseudo-static voltage
maintained on the inverting input.
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SLOS397E − JULY 2002 − REVISED JANUARY 2004
5 V +V
S
+
100 pF
0.1 µF
6.8 µF
+
RT
130 Ω
CT
0.1 µF
50 Ω Source
VI
VO
THS4271
_
499 Ω
Rg
Rf
249 Ω
RM
61.9 Ω
249 Ω
0.1 µF
100 pF
−5 V
The last major consideration in inverting amplifier design
is setting the bias current cancellation resistor on the
noninverting input. If the resistance is set equal to the total
dc resistance looking out of the inverting terminal, the
output dc error, due to the input bias currents, is reduced
to (input offset current) multiplied by Rf in Figure 76, the dc
source impedance looking out of the inverting terminal is
249 Ω || (249 Ω + 27.7 Ω) = 130 Ω. To reduce the additional
high-frequency noise introduced by the resistor at the
noninverting input, and power-supply feedback, RT is
bypassed with a capacitor to ground.
6.8 µF
+
−VS
Figure 76. Wideband, Inverting Gain
Configuration
In the inverting configuration, some key design
considerations must be noted. One is that the gain resistor
(Rg) becomes part of the signal channel input impedance.
If the input impedance matching is desired (which is
beneficial whenever the signal is coupled through a cable,
twisted pair, long PC board trace, or other transmission
line conductors), Rg may be set equal to the required
termination value and Rf adjusted to give the desired gain.
However, care must be taken when dealing with low
inverting gains, as the resultant feedback resistor value
can present a significant load to the amplifier output. For
an inverting gain of 2, setting Rg to 49.9 Ω for input
matching eliminates the need for RM but requires a 100-Ω
feedback resistor. This has an advantage of the noise gain
becoming equal to 2 for a 50-Ω source impedance—the
same as the noninverting circuit in Figure 75. However, the
amplifier output now sees the 100-Ω feedback resistor in
parallel with the external load. To eliminate this excessive
loading, it is preferable to increase both Rg and Rf, values,
as shown in Figure 76, and then achieve the input
matching impedance with a third resistor (RM) to ground.
The total input impedance becomes the parallel
combination of Rg and RM.
The next major consideration is that the signal source
impedance becomes part of the noise gain equation and
hence influences the bandwidth. For example, the RM
value combines in parallel with the external 50-Ω source
impedance (at high frequencies), yielding an effective
source impedance of 50 Ω || 61.9 Ω = 27.7 Ω. This
impedance is then added in series with Rg for calculating
the noise gain. The result is 1.9 for Figure 76, as opposed
to the 1.8 if RM is eliminated. The bandwidth is lower for the
gain of –2 circuit, Figure 76, (NG=+1.9) than for the gain
of +2 circuit in Figure 75.
SINGLE SUPPLY OPERATION
The THS4271 is designed to operate from a single 5-V to
15-V power supply. When operating from a single power
supply, care must be taken to ensure the input signal and
amplifier are biased appropriately to allow for the
maximum output voltage swing. The circuits shown in
Figure 77 demonstrate methods to configure an amplifier
in a manner conducive for single supply operation.
+VS
50 Ω Source
+
VI
49.9 Ω
RT
THS4271
VO
_
499 Ω
+VS
2
Rf
Rg
249 Ω
+VS
2
249 Ω
Rf
249 Ω
50 Ω Source
VI
61.9 Ω
+VS
2
VS
Rg
249 Ω
RT
_
THS4271
+
VO
499 Ω
+VS
2
Figure 77. DC-Coupled Single Supply Operation
Saving Power With Power-Down Functionality
and Setting Threshold Levels With the Reference
Pin
The THS4275 features a power-down pin (PD) which
lowers the quiescent current from 22 mA down to 700 µA,
ideal for reducing system power.
The power-down pin of the amplifiers defaults to the
positive supply voltage in the absence of an applied
voltage, putting the amplifier in the power-on mode of
operation. To turn off the amplifier in an effort to conserve
power, the power-down pin can be driven towards the
19
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SLOS397E − JULY 2002 − REVISED JANUARY 2004
negative rail. The threshold voltages for power-on and
power-down are relative to the supply rails and given in the
specification tables. Above the Enable Threshold Voltage,
the device is on. Below the Disable Threshold Voltage, the
device is off. Behavior in between these threshold voltages
is not specified.
Note that this power-down functionality is just that; the
amplifier consumes less power in power-down mode. The
power-down mode is not intended to provide a highimpedance output. In other words, the power-down
functionality is not intended to allow use as a 3-state bus
driver. When in power-down mode, the impedance looking
back into the output of the amplifier is dominated by the
feedback and gain setting resistors, but the output
impedance of the device itself varies depending on the
voltage applied to the outputs.
The time delays associated with turning the device on and
off are specified as the time it takes for the amplifier to
reach 50% of the nominal quiescent current. The time
delays are on the order of microseconds because the
amplifier moves in and out of the linear mode of operation
in these transitions.
Power-Down Reference Pin Operation
In addition to the power-down pin, the THS4275 also
features a reference pin (REF) which allows the user to
control the enable or disable power-down voltage levels
applied to the PD pin. Operation of the reference pin as it
relates to the power-down pin is described below.
In most split-supply applications, the reference pin is
connected to ground. In some cases, the user may want
to connect it to the negative or positive supply rail. In either
case, the user needs to be aware of the voltage level
thresholds that apply to the power-down pin. The tables
below show examples and illustrate the relationship
between the reference voltage and the power-down
thresholds.
Note that in order to maintain these threshold levels, the
reference pin can be any voltage between Vs− or GND up
to Vs/2 (midrail).
POWER-DOWN THRESHOLD VOLTAGE LEVELS (REF > MIDRAIL)
SUPPLY
VOLTAGE
(V)
±5
5
REFERENCE PIN
VOLTAGE (V)
ENABLE
LEVEL (V)
DISABLE
LEVEL (V)
GND
≥ 1.8
≤1
−2.5
≥ −0.7
≤ −1.5
−5
≥ −3.2
≤ −4
GND
≥ 1.8
≤1
1
≥ 2.8
≤2
2.5
≥ 4.3
≤ 3.5
In the above table, the threshold levels are derived by the
following equations:
REF + 1.8 V for enable
REF + 1 V for disable
20
ENABLE
LEVEL (V)
DISABLE
LEVEL (V)
Floating or 5
≥4
≤ 3.3
2.5
≥ 1.5
≤ 0.8
±5
1
≥0
≤ −0.7
Floating or 5
≥ 3.3
≤ 3.3
4
≥3
≤ 2.3
3.5
≥ 2.5
≤ 1.8
5
In the above table, the threshold levels are derived by the
following equations:
REF − 1 V for enable
REF − 1.7 V for disable
Note that in order to maintain these threshold levels, the
reference pin can be any voltage between (Vs+/2) + 1 V to
Vs+.
The recommended mode of operation is to tie the
reference pin to midrail, thus setting the threshold levels to
midrail +1 V and midrail +1.8 V.
NO. OF CHANNELS
PACKAGES
Single (8-pin)
THS4275D, THS4275DGN, and
THS4275DRB
Power Supply Decoupling Techniques and
Recommendations
Power supply decoupling is a critical aspect of any
high-performance amplifier design process. Careful
decoupling provides higher quality ac performance (most
notably improved distortion performance). The following
guidelines ensure the highest level of performance.
1.
Place decoupling capacitors as close to the power
supply inputs as possible, with the goal of minimizing
the inductance of the path from ground to the power
supply.
2.
Placement priority should put the smallest valued
capacitors closest to the device.
3.
Use of solid power and ground planes is
recommended to reduce the inductance along power
supply return current paths, with the exception of the
areas underneath the input and output pins.
4.
Recommended values for power supply decoupling
include a bulk decoupling capacitor (6.8 to 22 µF), a
mid-range decoupling capacitor (0.1 µF) and a high
frequency decoupling capacitor (1000 pF) for each
supply. A 100-pF capacitor can be used across the
supplies as well for extremely high frequency return
currents, but often is not required.
POWER-DOWN THRESHOLD VOLTAGE LEVELS (REF ≤ MIDRAIL)
SUPPLY
VOLTAGE
(V)
REFERENCE PIN
VOLTAGE (V)
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SLOS397E − JULY 2002 − REVISED JANUARY 2004
APPLICATION CIRCUITS
Driving an Analog-to-Digital Converter With the
THS4271
The THS4271 can be used to drive high-performance
analog-to-digital converters. Two example circuits are
presented below.
The first circuit uses a wideband transformer to convert a
single-ended input signal into a differential signal. The
differential signal is then amplified and filtered by two
THS4271 amplifiers. This circuit provides low
intermodulation distortion, suppressed even-order
distortion, 14 dB of voltage gain, a 50-Ω input impedance,
and a single-pole filter at 100 MHz. For applications
without signal content at dc, this method of driving ADCs
can be very useful. Where dc information content is
required, the THS4500 family of fully differential amplifiers
may be applicable.
_
−5 V
249 Ω
24.9 Ω
ADS5422
22 pF
49.9 Ω
RT
RISO 0.1 µF
THS4271
_
−5 V
IN
68 pf
16.5 Ω
ADS807
12-Bit,
CM 53 Msps
IN
Rf
1.82 kΩ
249 Ω
0.1 µF
249 Ω
Rg
NOTE: For best performance, high-speed ADCs should be driven
differentially. See the THS4500 family of devices for more
information.
Figure 79. Driving an ADC With a
Single-Ended Input
100 Ω
3.3 V 3.3 V
14-Bit, 62 Msps
22 pF
249 Ω
100 Ω
100 Ω
24.9 Ω
249 Ω
_
THS4271
VCM
+
VI
Two example circuits are presented here showing the
THS4271 buffering the output of a digital-to-analog
converter. The first circuit performs a differential to
single-ended conversion with the THS4271 configured as
a difference amplifier. The difference amplifier can double
as the termination mechanism for the DAC outputs as well.
+
THS4271
50 Ω
(1:4 Ω)
Source 1:2
100 Ω
+5 V
Using the THS4271 as a DAC Output Buffer
5V
VCM
50 Ω
Source
+
+5 V
DAC5675
14-Bit,
400 MSps
249 Ω
124 Ω
_
49.9 Ω
RF
THS4271
+
249 Ω
−5 V
249 Ω
LO
Figure 78. A Linear, Low Noise, High Gain ADC
Preamplifier
The second circuit depicts single-ended ADC drive. While
not recommended for optimum performance using
converters
with differential
inputs,
satisfactory
performance can sometimes be achieved with
single-ended input drive. An example circuit is shown here
for reference.
Figure 80. Differential to Single-Ended
Conversion of a High-Speed DAC Output
For cases where a differential signaling path is desirable,
a pair of THS4271 amplifiers can be used as output
buffers. The circuit depicts differential drive into a mixer’s
IF inputs, coupled with additional signal gain and filtering.
21
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SLOS397E − JULY 2002 − REVISED JANUARY 2004
100 Ω
THS4271
VI+
+
3.3 V 3.3 V
+
49.9 Ω
VO+
_
_
100 Ω
100 Ω
CF
1 nF
249 Ω
499 Ω
1 nF
IF+
DAC5675
249 Ω
100 Ω
249 Ω
14-Bit,
400 MSps
249 Ω
49.9 Ω
249 Ω
49.9 Ω
100 Ω
249 Ω
RF(out)
_
49.9 Ω
IF−
1 nF
1 nF
_
VI−
CF
VO−
100 Ω
+
Figure 83. A High Input Impedance, Low
Noise, Differential Receiver
+
THS4271
Figure 81. Differential Mixer Drive Circuit Using
the DAC5675 and the THS4271
A modification on this circuit to include a difference
amplifier turns this circuit into a high-speed instrumentation amplifier, as shown in Figure 84.
100 Ω
Active Filtering With the THS4271
+
VI−
Rg2
Rf2
Rg2
THS4271
THS4271
_
High-frequency active filtering with the THS4271 is
achievable due to the amplifier’s high slew-rate, wide
bandwidth, and voltage feedback architecture. Several
options are available for high-pass, low-pass, bandpass,
and bandstop filters of varying orders. A simple two-pole
low pass filter is presented here as an example, with two
poles at 100 MHz.
Rf1
Rg1
_
THS4271
100 Ω
6.8
pF
_
Rf1
49.9 Ω
VO
+
49.9 Ω
+
Rf2
VI+
50 Ω Source
249 Ω
VI
249 Ω
61.9 Ω
Figure 84. A High-Speed Instrumentation
Amplifier
5V
_
49.9 Ω
THS4271
+
VO
33 pF
ǒ
Ǔ
ǒ Ǔ
R f2
2R f1 ǒ
VO + 1 1 )
V i)–V i–Ǔ
2
Rg1
Rg2
(1)
−5 V
Figure 82. A Two-Pole Active Filter With Two
Poles Between 90 MHz and 100 MHz
A Low-Noise Receiver With the THS4271
A combination of two THS4271 amplifiers can create a
high-speed, low-distortion, low-noise differential receiver
circuit as depicted in Figure 83. With both amplifiers
operating in the noninverting mode of operation, the circuit
presents a high load impedance to the source. The
designer has the option of controlling the impedance
through termination resistors if a matched termination
impedance is desired.
22
THEORY AND GUIDELINES
Distortion Performance
The THS4271 provides excellent distortion performance
into a 150-Ω load. Relative to alternative solutions, it
provides exceptional performance into lighter loads, as
well as exceptional performance on a single 5-V supply.
Generally, until the fundamental signal reaches very high
frequency or power levels, the 2nd harmonic dominates the
total harmonic distortion with a negligible 3rd harmonic
component. Focusing then on the 2nd harmonic,
increasing the load impedance improves distortion
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SLOS397E − JULY 2002 − REVISED JANUARY 2004
directly. The total load includes the feedback network; in
the noninverting configuration (Figure 75) this is the sum
of Rf and Rg, while in the inverting configuration
(Figure 76), only Rf needs to be included in parallel with
the actual load.
LINEARITY: DEFINITIONS, TERMINOLOGY,
CIRCUIT TECHNIQUES, AND DESIGN
TRADEOFFS
The THS4271 features excellent distortion performance
for monolithic operational amplifiers. This section focuses
on the fundamentals of distortion, circuit techniques for
reducing nonlinearity, and methods for equating distortion
of operational amplifiers to desired linearity specifications
in RF receiver chains.
Amplifiers are generally thought of as linear devices. The
output of an amplifier is a linearly scaled version of the
input signal applied to it. However, amplifier transfer
functions are nonlinear. Minimizing amplifier nonlinearity
is a primary design goal in many applications.
Intercept points are specifications long used as key design
criteria in the RF communications world as a metric for the
intermodulation distortion performance of a device in the
signal chain (e.g., amplifiers, mixers, etc.). Use of the
intercept point, rather than strictly the intermodulation
distortion, allows simpler system-level calculations.
Intercept points, like noise figures, can be easily cascaded
back and forth through a signal chain to determine the
overall receiver chain’s intermodulation distortion
performance. The relationship between intermodulation
distortion and intercept point is depicted in Figure 85 and
Figure 86.
Power
PO
1X
OIP3
PO
IMD3
∆fc = fc − f1
∆fc = f2 − fc
3X
IMD3 = PS − PO
Figure 86
Due to the intercept point’s ease of use in system level
calculations for receiver chains, it has become the
specification of choice for guiding distortion-related design
decisions. Traditionally, these systems use primarily
class-A, single-ended RF amplifiers as gain blocks. These
RF amplifiers are typically designed to operate in a 50-Ω
environment. Giving intercept points in dBm, implies an
associated impedance (50 Ω).
However, with an operational amplifier, the output does not
require termination as an RF amplifier would. Because
closed-loop amplifiers deliver signals to their outputs
regardless of the impedance present, it is important to
comprehend this when evaluating the intercept point of an
operational amplifier. The THS4271 yields optimum
distortion performance when loaded with 150 Ω to 1 kΩ,
very similar to the input impedance of an analog-to-digital
converter over its input frequency band.
The discontinuity between open-loop, class-A amplifiers
and closed-loop, class-AB amplifiers becomes apparent
when comparing the intercept points of the two types of
devices. Equations 1 and 2 gives the definition of an
intercept point, relative to the intermodulation distortion.
PS
f1 fc
f2
PIN
(dBm)
PS
OIP 3 + P O )
fc − 3∆f
IIP3
As a result, terminating the input of the ADC to 50 Ω can
actually be detrimental to systems performance.
PO
PS
POUT
(dBm)
fc + 3∆f
f − Frequency − MHz
Figure 85
ǒ
P O + 10 log
ǒŤIMD2 ŤǓ where
3
Ǔ
V 2P
2RL 0.001
(2)
(3)
NOTE: PO is the output power of a single tone, RL is the load
resistance, and VP is the peak voltage for a single tone.
23
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SLOS397E − JULY 2002 − REVISED JANUARY 2004
NOISE ANALYSIS
Driving Capacitive Loads
High slew rate, unity gain stable, voltage-feedback
operational amplifiers usually achieve their slew rate at the
expense of a higher input noise voltage. The 3 nV/√Hz
input voltage noise for the THS4271 and THS4275 is,
however, much lower than comparable amplifiers. The
input-referred voltage noise, and the two input-referred
current noise terms (3 pA/√Hz), combine to give low output
noise under a wide variety of operating conditions.
Figure 87 shows the amplifier noise analysis model with all
the noise terms included. In this model, all noise terms are
taken to be noise voltage or current density terms in either
nV/√Hz or pA/√Hz.
One of the most demanding, and yet very common, load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an A/D converter, including
additional external capacitance, which may be
recommended to improve A/D linearity. A high-speed, high
open-loop gain amplifier like the THS4271 can be very
susceptible to decreased stability and closed-loop
response peaking when a capacitive load is placed directly
on the output pin. When the amplifier’s open-loop output
resistance is considered, this capacitive load introduces
an additional pole in the signal path that can decrease the
phase margin. When the primary considerations are
frequency response flatness, pulse response fidelity, or
distortion, the simplest and most effective solution is to
isolate the capacitive load from the feedback loop by
inserting a series isolation resistor between the amplifier
output and the capacitive load. This does not eliminate the
pole from the loop response, but rather shifts it and adds
a zero at a higher frequency. The additional zero acts to
cancel the phase lag from the capacitive load pole, thus
increasing the phase margin and improving stability.
THS4271/THS4275
ENI
+
RS
IBN
ERS
4kTRS
4kT
Rg
EO
_
Rf
Rg
IBI
ERF
4kTRf
The Typical Characteristics show the recommended
isolation resistor vs capacitive load and the resulting
frequency response at the load. Parasitic capacitive loads
Figure 87. Noise Analysis Model
greater than 2 pF can begin to degrade the performance
of the THS4271. Long PC board traces, unmatched
The total output shot noise voltage can be computed as the
cables, and connections to multiple devices can easily
square of all square output noise voltage contributors.
cause this value to be exceeded. Always consider this
Equation 3 shows the general form for the output noise
effect carefully, and add the recommended series resistor
voltage using the terms shown in Figure 87:
as close as possible to the THS4271 output pin (see Board
(4)
2
2
Layout Guidelines).
EO +
ENI 2 ) ǒIBNRSǓ ) 4kTR S NG 2 ) ǒIBIRfǓ ) 4kTRfNG
4kT = 1.6E−20J
at 290K
Ǹǒ
Ǔ
Dividing this expression by the noise gain (NG=(1+ Rf/Rg))
gives the equivalent input-referred spot noise voltage at
the noninverting input, as shown in Equation 4:
EO +
Ǹ
E NI
2
ǒ Ǔ ) 4kTR
NG
2
I R
) ǒI BNRSǓ ) 4kTR S ) BI f
NG
2
f
Evaluation of these two equations for the circuit and
component values shown in Figure 75 will give a total
output spot noise voltage of 12.2 nV/√Hz and a total
equivalent input spot noise voltage of 6.2 nV/√Hz. This
includes the noise added by the resistors. This total
input-referred spot noise voltage is not much higher than
the 3 nV/√Hz specification for the amplifier voltage noise
alone.
24
The criterion for setting this R(ISO) resistor is a maximum
bandwidth, flat frequency response at the load. For a gain
of +2, the frequency response at the output pin is already
slightly peaked without the capacitive load, requiring
(5) relatively high values of R(ISO) to flatten the response at
the load. Increasing the noise gain also reduces the
peaking.
www.ti.com
SLOS397E − JULY 2002 − REVISED JANUARY 2004
FREQUENCY RESPONSE
vs
CAPACITIVE LOAD
Again, keep their leads and PC board trace length as
short as possible. Never use wire-wound type
resistors in a high frequency application. Since the
output pin and inverting input pin are the most
sensitive to parasitic capacitance, always position the
feedback and series output resistor, if any, as close as
possible to the output pin. Other network components,
such as noninverting input-termination resistors,
should also be placed close to the package. Where
double-side component mounting is allowed, place
the feedback resistor directly under the package on
the other side of the board between the output and
inverting input pins. Even with a low parasitic
capacitance shunting the external resistors,
excessively high resistor values can create significant
time constants that can degrade performance. Good
axial metal-film or surface-mount resistors have
approximately 0.2 pF in shunt with the resistor. For
resistor values > 2 kΩ, this parasitic capacitance can
add a pole and/or a zero below 400-MHz that can
effect circuit operation. Keep resistor values as low as
possible, consistent with load driving considerations.
A good starting point for design is to set the Rf to 249-Ω
for low-gain, noninverting applications. Doing this
automatically keeps the resistor noise terms low, and
minimizes the effect of their parasitic capacitance.
0.5
Normalized Gain − dB
0
−0.5
−1
−1.5
R(ISO) = 25 Ω CL = 10 pF
R(ISO) = 15 Ω CL = 100 pF
R(ISO) = 10 Ω CL = 50 pF
−2
−2.5
RL = 499 Ω
VS =±5 V
−3
1M
10 M
100 M
f − Frequency − Hz
Figure 88. Isolation Resistor Diagram
BOARD LAYOUT
Achieving optimum performance with a high frequency
amplifier like the THS4271 requires careful attention to
board layout parasitics and external component types.
Recommendations that optimize performance include:
1.
Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance on
the output and inverting input pins can cause
instability: on the noninverting input, it can react with
the source impedance to cause unintentional band
limiting. To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all of
the ground and power planes around those pins.
Otherwise, ground and power planes should be
unbroken elsewhere on the board.
2.
Minimize the distance (< 0.25”) from the power
supply pins to high frequency 0.1-µF de-coupling
capacitors. At the device pins, the ground and power
plane layout should not be in close proximity to the
signal I/O pins. Avoid narrow power and ground traces
to minimize inductance between the pins and the
decoupling capacitors. The power supply connections
should always be decoupled with these capacitors.
Larger (2.2-µF to 6.8-µF) decoupling capacitors,
effective at lower frequency, should also be used on
the main supply pins. These may be placed somewhat
farther from the device and may be shared among
several devices in the same area of the PC board.
3.
Careful selection and placement of external
components preserves the high frequency
performance of the THS4271. Resistors should be
a very low reactance type. Surface-mount resistors
work best and allow a tighter overall layout. Metal-film
and carbon composition, axially-leaded resistors can
also provide good high frequency performance.
4.
Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to the
next device as a lumped capacitive load. Relatively
wide traces (50 mils to 100 mils) should be used,
preferably with ground and power planes opened up
around them. Estimate the total capacitive load and
set RISO from the plot of recommended RISO vs
capacitive load. Low parasitic capacitive loads
(<4 pF) may not need an R(ISO), since the THS4271
is nominally compensated to operate with a 2-pF
parasitic load. Higher parasitic capacitive loads
without an R(ISO) are allowed as the signal gain
increases (increasing the unloaded phase margin). If
a long trace is required, and the 6-dB signal loss
intrinsic to a doubly-terminated transmission line is
acceptable, implement a matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50-Ω
environment is normally not necessary onboard, and
in fact, a higher impedance environment improves
distortion as shown in the distortion versus load plots.
With a characteristic board trace impedance defined
based on board material and trace dimensions, a
matching series resistor into the trace from the output
of the THS4271 is used as well as a terminating shunt
resistor at the input of the destination device.
Remember also that the terminating impedance is the
25
www.ti.com
SLOS397E − JULY 2002 − REVISED JANUARY 2004
parallel combination of the shunt resistor and the input
impedance of the destination device: this total
effective impedance should be set to match the trace
impedance. If the 6-dB attenuation of a doubly
terminated transmission line is unacceptable, a long
trace can be series-terminated at the source end only.
Treat the trace as a capacitive load in this case and set
the series resistor value as shown in the plot of R(ISO)
vs capacitive load. This does not preserve signal
integrity or a doubly-terminated line. If the input
impedance of the destination device is low, there is
some signal attenuation due to the voltage divider
formed by the series output into the terminating
impedance.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
Figure 89. Views of Thermally Enhanced
Package
Although there are many ways to properly heatsink the
PowerPAD package, the following steps illustrate the
recommended approach.
ÓÓÓ
ÓÓÓ
ÓÓ
ÓÓÓ
ÓÓÓÓÓÓ
ÓÓ
ÓÓÓÓÓ
ÓÓÓ ÓÓ
Single or Dual
5.
Socketing a high speed part like the THS4271 is
not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can
create a troublesome parasitic network which can
make it almost impossible to achieve a smooth, stable
frequency response. Best results are obtained by
soldering the THS4271 onto the board.
68 Mils x 70 Mils
(Via diameter = 13mils)
Figure 90. PowerPAD PCB Etch and Via
Pattern
PowerPAD PCB LAYOUT CONSIDERATIONS
PowerPAD DESIGN CONSIDERATIONS
1.
Prepare the PCB with a top side etch pattern as shown
in Figure 90. There should be etch for the leads as well
as etch for the thermal pad.
The THS4271 and THS4275 are available in a
thermally-enhanced PowerPAD family of packages.
These packages are constructed using a downset
leadframe upon which the die is mounted [see
Figure 89(a) and Figure 89(b)]. This arrangement results
in the lead frame being exposed as a thermal pad on the
underside of the package [see Figure 89(c)]. Because this
thermal pad has direct thermal contact with the die,
excellent thermal performance can be achieved by
providing a good thermal path away from the thermal pad.
2.
Place five holes in the area of the thermal pad. The
holes should be 13 mils in diameter. Keep them small
so that solder wicking through the holes is not a
problem during reflow.
3.
Additional vias may be placed anywhere along the
thermal plane outside of the thermal pad area. They
help dissipate the heat generated by the THS4271
and THS4275 IC. These additional vias may be larger
than the 13-mil diameter vias directly under the
thermal pad. They can be larger because they are not
in the thermal pad area to be soldered, so that wicking
is not a problem.
4.
Connect all holes to the internal ground plane.
5.
When connecting these holes to the ground plane, do
not use the typical web or spoke via connection
methodology. Web connections have a high thermal
resistance connection that is useful for slowing the
heat transfer during soldering operations. This
resistance makes the soldering of vias that have plane
connections easier. In this application, however, low
thermal resistance is desired for the most efficient
heat transfer. Therefore, the holes under the THS4271
and THS4275 PowerPAD package should make their
connection to the internal ground plane, with a
complete connection around the entire circumference
of the plated-through hole.
The PowerPAD package allows both assembly and
thermal management in one manufacturing operation.
During the surface-mount solder operation (when the
leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package.
Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either
a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in
combining the small area and ease of assembly of surface
mount with the heretofore awkward mechanical methods
of heatsinking.
26
www.ti.com
SLOS397E − JULY 2002 − REVISED JANUARY 2004
7.
8.
The top-side solder mask should leave the terminals
of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should
cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the
thermal pad area during the reflow process.
Apply solder paste to the exposed thermal pad area
and all of the IC terminals.
With these preparatory steps in place, the IC is simply
placed in position and run through the solder reflow
operation as any standard surface-mount
component. This results in a part that is properly
installed.
For a given θJA , the maximum power dissipation is shown
in Figure 91 and is calculated by the equation 5:
PD +
Tmax * T A
q JA
(6)
where:
PD = Maximum power dissipation of THS4271 (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA = Free-ambient temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to the case
θCA = Thermal coefficient from the case to ambient air
(°C/W).
The next consideration is the package constraints. The
two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget
about the quiescent heat generated within the device,
especially multi-amplifier devices. Because these devices
have linear output stages (Class AB), most of the heat
dissipation is at low output voltages with high output
currents.
The other key factor when dealing with power dissipation
is how the devices are mounted on the PCB. The
PowerPAD devices are extremely useful for heat
dissipation. But, the device should always be soldered to
a copper plane to fully use the heat dissipation properties
of the PowerPAD. The SOIC package, on the other hand,
is highly dependent on how it is mounted on the PCB. As
more trace and copper area is placed around the device,
θJA decreases and the heat dissipation capability
increases. For a single package, the sum of the RMS
output currents and voltages should be used to choose the
proper package.
THERMAL ANALYSIS
The THS4271 device does not incorporate automatic
thermal shutoff protection, so the designer must take care
to ensure that the design does not violate the absolute
maximum junction temperature of the device. Failure may
result if the absolute maximum junction temperature of
150_ C is exceeded.
The thermal characteristics of the device are dictated by
the package and the PC board. Maximum power
dissipation for a given package can be calculated using the
following formula.
P Dmax +
(7)
Tmax–T A
q JA
where:
PDmax is the maximum power dissipation in the amplifier (W).
Tmax is the absolute maximum junction temperature (°C).
TA is the ambient temperature (°C).
θJA = θJC + θCA
θJC is the thermal coefficient from the silicon junctions to the
case (°C/W).
θCA is the thermal coefficient from the case to ambient air
(°C/W).
For systems where heat dissipation is more critical, the
THS4271 is offered in an 8-pin MSOP with PowerPAD.
The thermal coefficient for the MSOP PowerPAD package
is substantially improved over the traditional SOIC.
Maximum power dissipation levels are depicted in the
graph for the two packages. The data for the DGN
package assumes a board layout that follows the
PowerPAD layout guidelines referenced above and
detailed in the PowerPAD application notes in the
Additional Reference Material section at the end of the
data sheet.
3.5
PD − Maximum Power Dissipation − W
6.
8-Pin DGN Package
3
2.5
2
8-Pin D Package
1.5
1
0.5
0
−40
−20
0
20
40
60
TA − Ambient Temperature − °C
80
θJA = 170°C/W for 8-Pin SOIC (D)
θJA = 58.4°C/W for 8-Pin MSOP (DGN)
TJ = 150°C, No Airflow
Figure 91. Maximum Power Dissipation vs
Ambient Temperature
When determining whether or not the device satisfies the
maximum power dissipation requirement, it is important to
consider not only quiescent power dissipation, but also
dynamic power dissipation. Often maximum power is
difficult to quantify because the signal pattern is
inconsistent, but an estimate of the RMS power dissipation
can provide visibility into a possible problem.
27
www.ti.com
SLOS397E − JULY 2002 − REVISED JANUARY 2004
Performance vs Package Options
The THS4271 and THS4275 are offered in different
package options. However, performance may be limited
due to package parasitics and lead inductance in some
packages. In order to achieve maximum performance of
the THS4271 and THS4275, Texas Instruments
recommends using the leadless MSOP (DRB) or MSOP
(DGN) packages, in addition to proper high-speed PCB
layout. Figure 92 shows the unity gain frequency response
of the THS4271 using the leadless MSOP, MSOP, and
SOIC package for comparison. Using the THS4271 and
THS4275 in a unity gain with the SOIC package may result
in the device becoming unstable. In higher gain
configurations, this effect is mitigated by the reduced
bandwidth. As such, the SOIC is suitable for application
with gains equal to or higher than +2 V/V or (−1 V/V).
20
18
_
Normalized Gain − dB
16
15
13
SOIC, Rf = 0 Ω
Rf
Rf = 50 Ω
Rf
+
150 Ω
49.9 Ω
9
Rf = 0 Ω
Rf = 100 Ω
7
Rf = 150 Ω
5
3
1
−1
VIN = 100 mVPP
VS = ±5 V
−5
10M
100M
f − Frequency − Hz
SOIC,
Rf = 100 Ω
1G
Figure 93. Frequency Response vs Feedback
Resistor Using the EDGE #6439527 EVM
10
SOIC, Rf = 200 Ω
8
11
_
−3
150 Ω
49.9 Ω
12
4
17
+
14
6
The THS4271/THS4275 EVM board shown in Figure 96
through Figure 99 is designed to accommodate different
gain configurations. Its default component values are set
to give a gain of 2. The EVM can be configured in a gain
of +1; however, it is strongly not recommended. Evaluating
the THS4271/THS4275 in a gain of 1 using this EVM may
cause the part to become unstable. The stability of the
device can be controlled by adding a large resistor in the
feedback path, the performance is sacrificed. Figure 93
shows the small signal frequency response of the
THS4271 with different feedback resistors in the feedback
path. Figure 94 is the small frequency response of the
THS4271 using the gain of 1 EVM.
Small Signal Gain − dB
DESIGN TOOLS
Leadless MSOP, &
MSOP Rf = 0 Ω
2
4
0
−4
VIN = 100 mVPP
VS =±5 V
10 M
3
100 M
1G
f − Frequency − Hz
Figure 92. Effects of Unity Gain Frequency
Response for Differential Packages
Evaluation Fixtures, Spice Models, and
Applications Support
Small Signal Gain − dB
−2
2
28
150 Ω
49.9 Ω
1
0
−1
−2
−3
Texas Instruments is committed to providing its customers
with the highest quality of applications support. To support
this goal, evaluation boards have been developed for the
THS4271 operational amplifier. Three evaluation boards
are available: one THS4271 and one THS4275, both are
configurable for different gains, and a third for a gain of +1
(THS4271 only). These boards are easy to use, allowing
for straightforward evaluation of the device. These
evaluation boards can be ordered through the Texas
Instruments web site, www.ti.com, or through your local
Texas Instruments sales representative. Schematics for
the evaluation boards are shown below.
_
+
Gain = 1
RL = 150 Ω
VO = 100 mVPP
VS = ±5 V
−4
100 k
1M
10 M
100 M
f − Frequency − Hz
1G
10 G
Figure 94. Frequency Response Using the
EDGE # 6443547 G = +1 EVM
The peaking in the frequency response is due to the lead
inductance in the feedback path. Each pad and trace on a
PCB has an inductance associated with it, which in
conjunction with the inductance associated with the
package may cause peaking in the frequency response,
causing the device to become unstable.
www.ti.com
SLOS397E − JULY 2002 − REVISED JANUARY 2004
In order to achieve the maximum performance of the
device, PCB layout is very critical. Texas Instruments has
developed an EVM for the evaluation of the THS4271 in a
gain of 1. The EVM is shown in Figure 101 through
Figure 104. This EVM is designed to minimize peaking in
the unity gain configuration.
Minimizing the inductance in the feedback path is critical
for reducing the peaking of the frequency response in unity
gain. The recommended maximum inductance allowed in
the feedback path is 4 nH. This can be calculated by using
Equation 8.
ƪ
L(nH) + Kȏ ln
ƫ
(8)
2ȏ ) 0.223 W ) T ) 0.5
ȏ
W)T
where:
W = Width of trace in inches.
ȏ = Length of the trace in inches.
T = Thickness of the trace in inches.
K = 5.08 for dimensions in inches, and K = 2 for dimensions
in cm.
Vs+
J9
Power Down
R8
Figure 96. THS4271/THS4275 EVM Board
Layout (Top Layer)
C8
R9
R5
Vs −
Vs+
7 8
2 _
R3
J1
Vin −
U1
R6
6
J4
Vout
3 +
R2
R7
4 1
Vs −
J2
Vin+
J8
Power Down Ref
C7
R1
R4
J7
VS−
J6
GND
J5
VS+
TP1
FB1
FB2
VS−
C5
C6
VS+
C1
+
C2
+
C3
Figure 95. THS4271/THS4275 EVM Circuit
Configuration
C4
Figure 97. THS4271/THS4275 EVM Board
Layout (Second Layer, Ground)
29
www.ti.com
SLOS397E − JULY 2002 − REVISED JANUARY 2004
Vs+
7 8
2 _
U1
R6
6
J4
Vout
3 +
R7
4 1
J2
Vin+
Vs −
R4
J7
VS−
J6
GND
J5
VS+
TP1
FB1
FB2
VS−
C5
30
C6
VS+
C1
+
C2
+
C3
Figure 98. THS4271/THS4275 EVM Board
Layout (Third Layer, Power)
Figure 100. THS4271 Unity Gain EVM Circuit
Configuration
Figure 99. THS4271/THS4275 EVM Board
Layout (Bottom Layer)
Figure 101. THS4271 Unity Gain EVM Board
Layout (Top Layer)
C4
www.ti.com
SLOS397E − JULY 2002 − REVISED JANUARY 2004
Figure 104. THS4271 Unity Gain EVM Board
Layout (Bottom Layer)
Figure 102. THS4271 Unity Gain EVM Board
Layout (Second Layer, Ground)
Computer simulation of circuit performance using SPICE
is often useful when analyzing the performance of analog
circuits and systems. This is particularly true for video and
RF amplifier circuits where parasitic capacitance and
inductance can have a major effect on circuit performance.
A SPICE model for the THS4271 is available through
either the Texas Instruments web site (www.ti.com). The
PIC is also available for design assistance and detailed
product information. These models do a good job of
predicting small-signal ac and transient performance
under a wide variety of operating conditions. They are not
intended to model the distortion characteristics of the
amplifier, nor do they attempt to distinguish between the
package types in their small-signal ac performance.
Detailed information about what is and is not modeled is
contained in the model file itself.
ADDITIONAL REFERENCE MATERIAL
Figure 103. THS4271 Unity Gain EVM Board
Layout (Third Layer, Power)
D
PowerPAD Made Easy, application brief (SLMA004)
D
PowerPAD Thermally Enhanced Package, technical
brief (SLMA002)
31
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
THS4271D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4271DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4271DGK
ACTIVE
MSOP
DGK
8
100
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4271DGKR
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4271DGKRG4
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4271DGN
ACTIVE
MSOPPower
PAD
DGN
8
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4271DGNR
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4271DGNRG4
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4271DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4271DRBR
ACTIVE
SON
DRB
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
THS4271DRBT
ACTIVE
SON
DRB
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
THS4275D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4275DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4275DGK
ACTIVE
MSOP
DGK
8
100
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4275DGKR
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4275DGKRG4
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4275DGN
ACTIVE
MSOPPower
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4275DGNG4
ACTIVE
MSOPPower
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4275DGNR
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4275DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4275DRBR
ACTIVE
SON
DRB
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
THS4275DRBT
ACTIVE
SON
DRB
8
250
CU NIPDAU
Level-2-260C-1 YEAR
80
Addendum-Page 1
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2005
Orderable Device
Status (1)
Package
Type
Package
Drawing
THS4275DRG4
ACTIVE
SOIC
D
Pins Package Eco Plan (2)
Qty
8
2500 Green (RoHS &
no Sb/Br)
Lead/Ball Finish
CU NIPDAU
MSL Peak Temp (3)
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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Addendum-Page 2
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