HT95L100/10P Preliminary 8-Bit LCD Type Phone Controller MCU Features · Provide MASK type and OTP type version · Up to 1.117ms instruction cycle with 3.58MHz system · Operating voltage range: 2.4V~5.5V clock · Program ROM: 4K´16 bits · Built-in 3.58MHz DTMF Generator · Data RAM: 1152´8 bits · LCD driver: - 20 seg.´8 com. - 4 segments can per nibble option to bidirectional · Up to 20 bidirectional I/O lines · 16-bit table read instructions I/O lines · Eight-level subroutine nesting - LCD contrast can be adjusted by software or exter- · Timer: nal resistor - Two 16-bit programmable Timer/Event Counter - Real time clock (RTC) - Watchdog Timer (WDT) - Fixed frame frequency 64Hz · Built-in Low Battery detector · All instructions in one or two machine cycles · Programmable frequency divider (PFD) · Built-in dialer I/O · Dual system clock: 32768Hz, 3.58MHz · 64-pin QFP package · Four operating modes: Idle mode, Sleep mode, Green mode and Normal mode Applications · Deluxe Feature Phone · Fax and answering machines · Caller ID Phone · Other communication system · Cordless Phone General Description can also operate with high speed system clock rate of 3.58MHz in normal mode for high performance operation. To ensure smooth dialer function and to avoid MCU shut-down in extreme low voltage situation, the dialer I/O circuit is built-in to generate hardware dialer signals such as on-hook, hold-line and hand-free. Built-in real time clock and programmable frequency divider are provided for additional fancy features in product developments. The device is best suitable for feature phone products that comply with versatile dialer specification requirements of different areas or countries. The HT95L100/10P are 8-bit high performance RISC-like microcontrollers with built-in DTMF generator and dialer I/O which provide MCU dialer implementation or system control features for telecom product application. The phone controller has a built-in program ROM, data RAM, LCD driver and a maximum of 20 I/O lines for high end products design. In addition, for power management purpose, it has a built-in frequency up conversion circuit (32768Hz to 3.58MHz) which provides dual system clock and four types of operation modes. For example it can operate with low speed system clock rate of 32768Hz in green mode with little power consumption. It Rev. 0.10 1 October 1, 2002 Preliminary HT95L100/10P Selection Table Part No. Operating Program Data Normal Dialer Voltage Memory Memory I/O I/O LCD Timer Stack External Interrupt DTMF Generator FSK Receiver Package HT95A200 HT95A20P 2.4V~5.5V 4K´16 1152´8 28 8 ¾ 16-bit´2 8 4 Ö ¾ 48SSOP HT95A300 HT95A30P 2.4V~5.5V 8K´16 2112´8 28 8 ¾ 16-bit´2 8 4 Ö ¾ 48SSOP HT95L100 HT95L10P 2.4V~5.5V 4K´16 1152´8 16~20 8 16´8~20´8 16-bit´2 8 4 Ö ¾ 64QFP HT95L200 HT95L20P 2.4V~5.5V 8K´16 1152´8 20~28 8 24´8~24´16 16-bit´2 8 4 Ö ¾ 100QFP HT95L300 HT95L30P 2.4V~5.5V 8K´16 2112´8 16~28 8 36´16~48´16 16-bit´2 8 4 Ö ¾ 100QFP HT95C200 HT95C20P 2.4V~5.5V 8K´16 1152´8 20~28 8 24´8~24´16 16-bit´2 8 4 Ö Ö 128QFP HT95C300 HT95C30P 2.4V~5.5V 8K´16 2112´8 16~28 8 36´16~48´16 16-bit´2 8 4 Ö Ö 128QFP Note: Part numbers suffixed with ²P² are OTP devices, all others are mask version devices. Block Diagram R E S P o w e r D o w n D e te c to r & R e s e t C ir c u it P ro g ra m C o u n te r P ro g ra m R O M S T S T S T S T S T S T S T S T A C A C A C A C A C A C A C A C K 0 K 1 K 2 K 3 K 4 K 5 K 6 K 7 3 2 7 6 8 H z R T C M P 0 M P 1 M U A L U H F I H F O H D I H D O H K S P O D N P O X M U T E V D D V S S O S C C ir c u it A C C 3 2 7 6 8 H z M T M R 0 U X S y s te m c lo c k /4 P A P A C P A 0 ~ P A 7 S T A T U S P B P B C P B 0 ~ P B 7 P E P E C P E 0 ~ P E 3 S h ifte r 3 2 7 6 8 H z W D T O S C S y s te m C lo c k /4 M W D T S U X W D T P r e s c a le r D T M F G e n e ra to r D T M F 3 .5 8 M H z D ia le r I/O 3 2 7 6 8 H z o r 3 .5 8 M H z /4 P o w e r S u p p ly P F D L o w B a tte ry D e te c to r L B IN Rev. 0.10 X M U X In s tr u c tio n D e c o d e r X 1 X 2 X C U IN T C 0 IN T C 1 D A T A M e m o ry X IN T /T M R 1 M T M R 1 T M R 1 C T M R 0 T M R 0 C In s tr u c tio n R e g is te r T im in g G e n e ra to r In te rru p t C ir c u it M U S IC L C D D r iv e r 2 0 (1 6 )´ 8 C O M 0 ~ C O M 7 S E G 0 ~ S E G 1 9 2 V L C D October 1, 2002 Preliminary HT95L100/10P Pin Assignment S E G 5 S E G 4 S E G 3 S E G 2 S E G 1 S E G 0 C O M 7 C O M 6 C O M 5 C O M 4 C O M 3 C O M 2 C O M 1 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 C O M 0 1 5 1 S E G 6 P A 7 2 5 0 S E G 7 P A 6 3 4 9 S E G 8 P A 5 4 4 8 S E G 9 P A 4 5 4 7 S E G 1 0 P A 3 6 4 6 S E G 1 1 P A 2 7 4 5 S E G 1 2 P A 1 8 4 4 S E G 1 3 P A 0 9 4 3 S E G 1 4 P B 7 1 0 4 2 S E G 1 5 P B 6 1 1 4 1 S E G 1 6 /P E 0 P B 5 1 2 4 0 S E G 1 7 /P E 1 P B 4 1 3 3 9 S E G 1 8 /P E 2 P B 3 1 4 3 8 S E G 1 9 /P E 3 P B 2 1 5 3 7 V L C D P B 1 1 6 3 6 M U S IC P B 0 1 7 3 5 R E S X M U T E 1 8 3 4 T M R 0 D N P O 1 9 3 3 D T M F H T 9 5 L 1 0 0 /1 0 P 6 4 Q F P -A 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 X C L B IN X 2 X 1 IN T /T M R 1 V D D V S S H F I H F O H D I H D O H K S P O Pin Description Pin Name I/O Description CPU VDD ¾ Positive power supply VSS ¾ Negative power supply, ground X1 I A 32768Hz crystal (or resonator) should be connected to this pin and X2. X2 O A 32768Hz crystal (or resonator) should be connected to this pin and X1. XC I External low pass filter used for frequency up conversion circuit. RES I Schmitt trigger reset input, active low. INT/TMR1 I Schmitt trigger input for external interrupt or Timer/Event Counter 1. No internal pull-high resistor. For INT: Edge trigger activated on a falling edge. For TMR1: Activated on falling or rising transition edge, selected by software. TMR0 I Schmitt trigger input for Timer/Event Counter 0. No internal pull-high resistor. Activated on falling or rising transition edge, selected by software. SEG0~SEG15 O LCD panel segment outputs. SEG16~SEG19 (PE0~PE3) O or I/O LCD panel segment outputs. SEG16~SEG19 can be nibble optioned to PE0~PE3 by software. COM0~COM7 O LCD panel common outputs. VLCD I LCD driver power source. LCD Driver Rev. 0.10 3 October 1, 2002 Preliminary Pin Name I/O HT95L100/10P Description Normal I/O PA0~PA7 I/O Bidirectional 8-bit input/output ports. Schmitt trigger input or CMOS output. See mask option table for pull-high and wake-up function PB0~PB7 I/O Bidirectional 8-bit input/output ports. Schmitt trigger input or CMOS output. See mask option table for pull-high function PE0~PE3 O or I/O Bidirectional 4-bit input/output ports. Schmitt trigger input and CMOS output. PE0~PE3 can be per nibble optioned to SEG16~SEG19 by software. See mask option table for pull-high function Dialer I/O (See the ²Dialer I/O function²) HFI I Schmitt trigger input structure. An external RC network is recommended for input debouncing. This pin is pulled low with internal resistance of 200kW typ. HFO O CMOS output structure. HDI I Schmitt trigger input structure. An external RC network is recommended for input debouncing. This pin is pulled high with internal resistance of 200kW typ. HDO O CMOS output structure. HKS I This pin detects the status of the hook-switch and its combination with HFI/HDI can control the PO pin output to make or break the line. PO O CMOS output structure controlled by HKS and HFI/HDI pins and which determines whether the dialer connects or disconnects the telephone line. DNPO O NMOS output structure. O NMOS output structure. Usually, XMUTE is used to mute the speech circuit when transmitting the dialer signal. DTMF O This pin outputs dual tone signals to dial out the phone number. The load resistor should not be less than 5kW. MUSIC O This pin outputs the single tone that generated by the PFD generator. LBIN I This pin detects battery low through external R1/R2 to determine threshold voltage. XMUTE Peripherals Absolute Maximum Ratings Supply Voltage ........................................-0.3V to 5.5V Storage Temperature ...........................-50°C to 125°C Input Voltage .............................. VSS-0.3 to VDD+0.3V Operating Temperature ..........................-25°C to 70°C Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 0.10 4 October 1, 2002 Preliminary HT95L100/10P Electrical Characteristics Symbol Parameter Ta=25°C Test Conditions VDD Conditions Min. Typ. Max. Unit CPU IIDL Idle Mode Current 5V 32768Hz off, 3.58MHz off, CPU off, LCD off, WDT off, no load ¾ ¾ 2 mA ISLP Sleep Mode Current 5V 32768Hz on, 3.58MHz off, CPU off, LCD off, WDT off, no load ¾ ¾ 30 mA IGRN Green Mode Current 5V 32768Hz on, 3.58MHz off, CPU on, LCD off, WDT off, no load ¾ ¾ 50 mA INOR Normal Mode Current 5V 32768Hz on, 3.58MHz on, CPU on, LCD on, WDT on, DTMF generator off, no load ¾ ¾ 3 mA VIL I/O Port Input Low Voltage 5V ¾ 0 ¾ 1 V VIH I/O Port Input High Voltage 5V ¾ 4 ¾ 5 V IOL I/O Port Sink Current 5V ¾ 4 6 ¾ mA IOH I/O Port Source Current 5V ¾ -2 -3 ¾ mA RPH Pull-high Resistor 5V ¾ 10 30 ¾ kW LBIN Low Battery Detection Reference Voltage 5V ¾ 1.10 1.15 1.20 V ¾ ¾ 3 5 V ¾ ¾ 100 mA ¾ ¾ 1 mA LCD Driver VLCD LCD Panel Power Supply ¾ ILCD LCD Operation Current ¾ VLCD=5V, 32768Hz, no load Dialer I/O IXMO XMUTE Leakage Current IOLXM XMUTE Sink Current 2.5V XMUTE pin=0.5V 1 ¾ ¾ mA IHKS HKS Input Current 2.5V HKS pin=2.5V ¾ ¾ 0.1 mA RHFI HFI Pull-low Resistance 2.5V VHFI=2.5V ¾ 200 ¾ kW RHDI HDI Pull-high Resistance 2.5V VHDI=0V ¾ 200 ¾ kW IOH2 HFO Source Current 2.5V VOH=2V -1 ¾ ¾ mA IOL2 ¾ ¾ mA 2.5V XMUTE pin=2.5V HFO Sink Current 2.5V VOL=0.5V 1 IOH3 HDO Source Current 2.5V VOH=2V -1 ¾ ¾ mA IOL3 HDO Sink Current 2.5V VOL=0.5V 1 ¾ ¾ mA IOH4 PO Source Current 2.5V VOH=2V -1 ¾ ¾ mA IOL4 PO Sink Current 2.5V VOL=0.5V 1 ¾ ¾ mA IOL5 DNPO Sink Current 2.5V VOL=0.5V 1 ¾ ¾ mA 0.45VDD ¾ 0.7VDD V DTMF Generator VTDC DTMF Output DC Level ¾ VDTMF=0.5V 0.1 ¾ ¾ mA ¾ Row group, RL=5kW 120 155 180 mVrms ¾ THD£-23dB 5 ¾ ¾ kW Column Pre-emphasis ¾ Row group=0dB 1 2 3 dB Tone Signal Distortion ¾ RL=5kW ¾ -30 -23 dB VTOL DTMF Sink Current ¾ VTAC DTMF Output AC Level RL DTMF Output Load ACR THD Rev. 0.10 ¾ 5 October 1, 2002 Preliminary HT95L100/10P Functional Description to fetch an instruction code, the contents of the program counter are incremented by 1. The program counter then points to the memory word containing the next instruction code. Execution flow The system clock for the telephone controller is derived from a 32768Hz crystal oscillator. A built-in frequency up conversion circuit provides dual system clock, namely; 32768Hz and 3.58MHz. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. The pipelining scheme causes each instruction to be effectively executed in a instruction cycle. If an instruction changes the program counter, two instruction cycles are required to complete the instruction. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the program counter manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed to the next instruction. Program counter - PC The program counter lower order byte register (PCL:06H) is a readable and write-able register. Moving data into the PCL performs a short jump. The destination will be within 256 locations. When a control transfer takes place, an additional dummy cycle is required. The program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a full range of program memory. After accessing a program memory word S y s te m C lo c k T 1 T 2 T 3 T 4 T 1 T 2 P C P C T 3 T 4 T 1 T 2 P C + 1 F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 ) T 3 T 4 P C + 2 F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C ) F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 ) Execution flow Program Counter Mode *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 Initial reset 0 0 0 0 0 0 0 0 0 0 0 0 External interrupt 0 0 0 0 0 0 0 0 0 1 0 0 Timer/Event Counter 0 overflow 0 0 0 0 0 0 0 0 1 0 0 0 Timer/Event Counter 1 overflow 0 0 0 0 0 0 0 0 1 1 0 0 RTC interrupt 0 0 0 0 0 0 0 1 0 1 0 0 Dialer I/O interrupt 0 0 0 0 0 0 0 1 1 0 0 0 Loading PCL *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 Jump, call branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 Return from subroutine S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Skip Program Counter+2 Note: *11~*0: Program counter bits S11~S0: Stack register bits #11~#0: Instruction code bits Rev. 0.10 @7~@0: PCL bits 6 October 1, 2002 Preliminary · Location 000CH Program memory - ROM This location is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, the Timer/Event Counter 1 interrupt is enabled and the stack is not full, the program begins execution at location 000CH. The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 4096´16 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage: · Location 0014H · Location 0000H This location is reserved for real time clock (RTC) interrupt service program. When RTC generator is enabled and time-out occurs, the RTC interrupt is enabled and the stack is not full, the program begins execution at location 0014H. This area is reserved for the initialization program. After chip power-on reset or external reset or WDT time-out reset, the program always begins execution at location 0000H. · Location 0004H · Location 0018H This area is reserved for the external interrupt service program. If the INT/TMR1 input pin is activated, the external interrupt is enabled and the stack is not full, the program begins execution at location 0004H. This location is reserved for the HKS pin edge transition or HDI pin falling edge transition or HFI pin rising edge transition. If this condition occurs, the dialer I/O interrupt is enabled and the stack is not full, the program begins execution at location 18H. · Location 0008H This area is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, the Timer/Event Counter 0 interrupt is enabled and the stack is not full, the program begins execution at location 0008H. 0 0 0 H 0 0 8 H 0 0 C H Table location Any location in the ROM space can be used as look-up tables. The instructions ²TABRDC [m]² (the current page, one page=256 words) and ²TABRDL [m]² (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, and the higher-order byte of the table word is transferred to TBLH. The table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in the TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors will then occur. Hence, simultaneously using the table read instruction in the main routine and the ISR should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed-up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending on the requirements. D e v ic e in itia liz a tio n p r o g r a m 0 0 4 H E x te r n a l in te r r u p t s u b r o u tin e T im e r /e v e n t c o u n te r 0 in te r r u p t s u b r o u tin e T im e r /e v e n t c o u n te r 1 in te r r u p t s u b r o u tin e 0 1 4 H R T C in te r r u p t s u b r o u tin e 0 1 8 H D ia le r I/O n 0 0 H P ro g ra m R O M in te r r u p t s u b r o u tin e L o o k - u p ta b le ( 2 5 6 w o r d s ) n F F H L o o k - u p ta b le ( 2 5 6 w o r d s ) 0 F F F H HT95L100/10P 1 6 b its N o te : n ra n g e s fro m 0 to 0 E H Program memory Instruction(s) Table Location *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 TABRDC [m] P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0 TABRDL [m] 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 Note: *11~*0: Table location bits P11~P8: Current program counter bits @7~@0: Table pointer bits Rev. 0.10 7 October 1, 2002 Preliminary HT95L100/10P LCD display memory and general purpose memory. Most are read/write, but some are read only. Stack register This is a special part of the memory which is used to save the contents of the program counter only. The stack is organized into 8 levels and is neither part of the data nor part of the program space, and is neither readable nor write-able. The activated level is indexed by the stack pointer (SP) and is neither readable nor write-able. At a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and an interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited even if this interrupt is enabled. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. If the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent eight return addresses are stored). The special function registers is located from 00H to 1FH. The embedded control register are located in the memory areas from 20H to 3FH. The remaining space which are not specified on the following table before the 40H are reserved for future expanded usage and reading these locations will get ²00H². The general purpose data memory is divided into 6 banks. The banks in the RAM are all addressed from 40H to 0FFH and they are selected by setting the value of the bank pointer (BP). All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by ²SET [m].i² and ²CLR [m].i². They are also indirectly accessible through memory pointer registers (MP0 or MP1). The bank1~bank10 are only indirectly accessible through memory pointer 1 register (MP1). The LCD display memory is located at bank 1BH. They can be read and written to by the indirect addressing mode using memory pointer 1 (MP1). To turn the display On or Off, a ²1² or ²0² is written to the corresponding bit of the memory area. Data memory The data memory is divided into four functional groups: special function registers, embedded control register, Special register, embedded control register, LCD display memory and general purpose RAM BP Address Function Description Special function register 00 00 IAR0 Indirect addressing register 0 00 01 MP0 Memory pointer register 0 00 02 IAR1 Indirect addressing register 1 00 03 MP1 Memory pointer register 1 00 04 BP 00 05 ACC Accumulator 00 06 PCL Program counter lower-order byte register 00 07 TBLP Table pointer 00 08 TBLH Table higher-order byte register Watchdog Timer option setting register Bank pointer register 00 09 WDTS 00 0A STATUS 00 0B INTC0 Interrupt control register 0 00 0C TMR0H Timer/Event Counter 0 high-order byte register 00 0D TMR0L Timer/Event Counter 0 low-order byte register 00 0E TMR0C Timer/Event Counter 0 control register 00 0F TMR1H Timer/Event Counter 1 high-order byte register 00 10 TMR1L Timer/Event Counter 1 low-order byte register Rev. 0.10 Status register 8 October 1, 2002 Preliminary BP Address Function 00 11 TMR1C 00 12 PA 00 13 PAC 00 14 PB 00 15 PBC 00 16 DIALERIO 00 1A PE 00 1B PEC 00 1E INTC1 HT95L100/10P Description Timer/Event Counter 1 control register Port A data register Port A control register Port B data register Port B control register Dialer I/O register Port E data register (bit3~bit0) Port E control register (bit3~bit0) Interrupt control register 1 Embedded control register 00 20 DTMFC DTMF generator control register 00 21 DTMFD DTMF generator data register 00 22 LINE Line control register 00 24 RTCC Real time clock control register 00 26 MODE Operation mode control register 00 28 LCDIO LCD segment and I/O option register 00 2D LCDC LCD driver control register 00 2E PFDC PFD control register 00 2F PFDD PFD data register General purpose RAM 00 40~FF BANK0 RAM General purpose RAM space 01 40~FF BANK1 RAM General purpose RAM space 02 40~FF BANK2 RAM General purpose RAM space 03 40~FF BANK3 RAM General purpose RAM space 04 40~FF BANK4 RAM General purpose RAM space 05 40~FF BANK5 RAM General purpose RAM space LCD RAM display memory 1B 8C~9F LCD RAM LCD RAM mapping space for COM0~COM7 Indirect addressing register Accumulator Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] will access the memory pointed to by MP0 and MP1, respectively. Reading location [00H] or [02H] indirectly returns the result 00H, while writing it leads to no operation. MP0 is indirectly addressable in bank0, but MP1 is available for all banks by switch BP [04H]. If BP is unequal to 00H, the indirect addressing mode to read/write operation from 00H~3FH will return the result as same as the value of bank0. The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can operate with immediate data. All data movement between two data memory locations must pass through the accumulator. The memory pointer registers MP0 and MP1 are 8-bits registers, and the bank pointer register BP is 5-bits register. · Logic operations (AND, OR, XOR, CPL) Rev. 0.10 Arithmetic and logic unit - ALU This circuit performs 8-bit arithmetic and logic operations and provides the following functions: · Arithmetic operations (ADD, ADC, SUB, SBC, DAA) · Rotation (RL, RR, RLC, RRC) · Increment and Decrement (INC, DEC) 9 October 1, 2002 Preliminary · Branch decision (SZ, SNZ, SIZ, SDZ, etc.) Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by hardware clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC0 (INTC1) may be set to allow interrupt nesting. The ALU not only saves the results of a data operation but also changes the status register. Status register - STATUS This status register contains the carry flag (C), auxiliary carry flag (AC), zero flag (Z), overflow flag (OV), power down flag (PD), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. If the stack is full, any other interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. Except for the TO and PD flags, bits in the status register can be altered by instructions, similar to the other registers. Data written into the status register will not change the TO or PD flag. Operations related to the status register may yield different results from those intended. The TO flag can be affected only by system power-up, a WDT time-out or executing the ²CLR WDT² or ²HALT² instruction. The PD flag can be affected only by executing the ²HALT² or ²CLR WDT² instruction or during a system power-up. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. The Z, OV, AC and C flags generally reflect the status of the latest operations. External interrupt is triggered by a high to low transition of the INT/TMR1 pin and the interrupt request flag EIF will be set. When the external interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag EIF and EMI bits will be cleared to disable other interrupts. On entering the interrupt sequence or executing the subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it . The Timer/Event Counter 0 interrupt is generated by a timeout overflow and the interrupt request flag T0F will be set. When the Timer/Event Counter 0 interrupt is enabled, the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The interrupt request flag T0F and EMI bits will be cleared to disable further interrupts. Interrupt The telephone controller provides an external interrupt, internal timer/event counter interrupt, an internal real time clock interrupt and internal dialer I/O interrupt. The Interrupt Control Registers 0 and Interrupt Control Register 1 both contains the interrupt control bits that set the enable/disable and the interrupt request flags. Register STATUS (0AH) Label Bits Function C 0 C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. Also it is affected by a rotate through carry instruction. AC 1 AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z 2 Z is set if the result of an arithmetic or logic operation is 0; otherwise Z is cleared. OV 3 OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PD 4 PD is cleared when either a system power-up or executing the CLR WDT instruction. PD is set by executing the HALT instruction. TO 5 TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. ¾ Rev. 0.10 HT95L100/10P 6, 7 Unused bit, read as ²0² 10 October 1, 2002 Preliminary Register INTC0 (0BH) INTC1 (1EH) HT95L100/10P Bits Label R/W Function 0 EMI RW Controls the master (global) interrupt (1=enabled; 0=disabled) 1 EEI RW Controls the external interrupt (1=enabled; 0=disabled) 2 ET0I RW Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled) 3 ET1I RW Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled) 4 EIF RW External interrupt request flag (1=active; 0=inactive) 5 T0F RW Timer/Event Counter 0 request flag (1=active; 0=inactive) 6 T1F RW Timer/Event Counter 1 request flag (1=active; 0=inactive) 7 ¾ RO Unused bit, read as ²0² 0 ¾ RO Unused bit, read as ²0² 1 ERTCI RW Control the real time clock interrupt (1=enable; 0=disable) 2 EDRI RW Control the dialer I/O interrupt (1=enable; 0=disable) 3 ¾ RO Unused bit, read as ²0² 4 ¾ RO Unused bit, read as ²0² 5 RTCF RW Internal real time clock interrupt request flag (1=active; 0=inactive) 6 DRF RW Internal dialer I/O interrupt request flag (1=active: 0=inactive) 7 ¾ RO Unused bit, read as ²0² the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. The Timer/Event Counter 1 interrupt is generated by a timeout overflow and the interrupt request flag T1F will be set. When the Timer/Event Counter 1 interrupt is enabled, the stack is not full and the T1F bit is set, a subroutine call to location 0CH will occur. The interrupt request flag T1F and EMI bits will be cleared to disable further interrupts. Interrupt Source The real time clock interrupt is generated by a 1Hz RTC generator. When the RTC time-out occurs, the interrupt request flag RTCF will be set. When the RTC interrupt is enabled, the stack is not full and the RTCF is set, a subroutine call to location 14H will occur. The interrupt request flag RTCF and EMI bits will be cleared to disable other interrupts. Priority Vector External interrupt 1 04H Timer/Event Counter 0 interrupt 2 08H Timer/Event Counter 1 interrupt 3 0CH Real time clock interrupt 4 14H Dialer I/O interrupt 5 18H Priority of the interrupt The dialer I/O interrupt is triggered by any edge transition onto HKS pin or a falling edge transition onto HDI pin or a rising edge transition onto HFI pin, the interrupt request flag DRF will be set. When the dialer I/O interrupt is enabled, the stack is not full and the DRF is set, a subroutine call to location 18H will occur. The interrupt request flag DRF and EMI bits will be cleared to disable other interrupts. EMI, EEI, ET0I, ET1I, ERTCI and EDRI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (EIF, T0F, T1F, RTCF, DRF) are set by hardware or software, they will remain in the INTC0 or INTC1 registers until the interrupts are serviced or cleared by a software instruction. It is recommended that a program should not use the ²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the ²CALL² operates in the interrupt subroutine. During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, ²RET² or ²RETI² may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on Rev. 0.10 11 October 1, 2002 Preliminary Oscillator configuration period. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 can give different time-out periods. There are two oscillator circuits in the controller, the external 32768Hz crystal oscillator and internal WDT OSC. The WDT OSC period is 78ms. This time-out period may vary with temperature, VDD and process variations. The WDT OSC always works for any operation mode. The 32768Hz crystal oscillator and frequency-up conversion circuit (32768Hz to 3.58MHz) are designed for dual system clock source. It is necessary for frequency conversion circuit to add external RC components to make up the low pass filter that stabilize the output frequency 3.58MHz (see the oscillator circuit). If the instruction clock is selected as the WDT clock source, the WDT operates in the same manner except in the Sleep mode or Idle mode. In these two modes, the WDT stops counting and lose its protecting purpose. In this situation the logic can only be re-started by external logic. The WDT OSC is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the Idle mode (the system clock is stopped), the WDT OSC still works within a period of 78ms normally. When the WDT is disabled or the WDT source is not this RC oscillator, the WDT OSC will be disabled. If the WDT clock source is the 32768Hz, the WDT also operates in the same manner except in the Idle mode. When in the Idle mode, the 32768Hz stops, the WDT stops counting and lose its protecting purpose. In this situation the logic can only be re-started by external logic. X 1 X 2 The high nibble and bit3 of the WDTS are reserved for user defined flags, which can be used to indicate some specified status. 1 5 k W X C 3 n The WDT time-out under Normal mode or Green mode will initialize ²chip reset² and set the status bit ²TO². But in the Sleep mode or Idle mode, the time-out will initialize a ²warm reset² and only the program counter and stack pointer are reset to 0. To clear the WDT contents (including the WDT prescaler), three methods are adopted; external reset (a low level to RES pin), software instruction and a ²HALT² instruction. 5 0 n System oscillator circuit Watchdog Timer - WDT The WDT clock source is implemented by a WDT OSC or external 32768Hz or an instruction clock (system clock divided by 4), determined by the mask option. This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by mask option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. The software instruction include ²CLR WDT² and the other set ²CLR WDT1² and ²CLR WDT2². Of these two types of instruction, only one can be active depending on the mask option ²WDT instr². If the ²CLR WDT² is selected (i.e. One clear instruction), any execution of the 3 2 7 6 8 H z W D T O S C S y s te m If the device operates in a noisy environment, using the on-chip WDT OSC or 32768Hz crystal oscillator is strongly recommended. WDTS (09H) Rev. 0.10 Label Bits C lo c k /4 W D T P r e s c a le r M a s k O p tio n S e le c t 9 - b it C o u n te r W S 0 ~ W S 2 When the WDT clock source is selected, it will be first divided by 512 (9-stage) to get the n o m i nal t i m e - o u t Register HT95L100/10P 7 - b it C o u n te r 8 -to -1 M U X W D T T im e - o u t Watchdog Timer R/W Function WS0 WS1 WS2 0 1 2 RW Watchdog Timer division ratio selection bits Bit 2, 1, 0=000, Division ratio=1:1 Bit 2, 1, 0=001, Division ratio=1:2 Bit 2, 1, 0=010, Division ratio=1:4 Bit 2, 1, 0=011, Division ratio=1:8 Bit 2, 1, 0=100, Division ratio=1:16 Bit 2, 1, 0=101, Division ratio=1:32 Bit 2, 1, 0=110, Division ratio=1:64 Bit 2, 1, 0=111, Division ratio=1:128 ¾ 7~3 RW Unused bit. These bits are read/write-able. 12 October 1, 2002 Preliminary · Green mode to Normal mode: CLR WDT instruction will clear the WDT. In the case that ²CLR WDT1² and ²CLR WDT2² are chosen (i.e. Two clear instructions), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip as a result of time-out. Step 1: Set UPEN to 1 Step 2: Software delay 20ms at least Step 3: Set MODE1 to 1 After Step 3, operation mode is changed to Normal mode. Controller operation mode · Sleep mode or Idle mode to Green mode: Holtek¢s telephone controllers support two system clock and four operation modes. The system clock could be 32768Hz or 3.58MHz and operation mode could be Normal, Green, Sleep or Idle mode. These are all selected by the software. Method 1: Any reset condition occurred Method 2: Any interrupt is active Method 3: Port A wake-up Note: The Timer 0, Timer 1, RTC and dialer I/O interrupt function will not work at the Idle mode because the 32768Hz crystal is stopped. The following conditions will force the operation mode to change to Green mode: · Any reset condition from any operation mode The reset conditions include power on reset, external reset, WDT time-out reset. By examining the processor status flag, PD and TO, the program can distinguish between different ²reset conditions². Refer to the Reset function for detailed description. · Any interrupt from Sleep mode or Idle mode · Port A wake-up from Sleep mode or Idle mode How to change the Operation Mode · Normal mode to Green mode: Clear MODE1 to 0, then operation mode is changed to Green mode but the UPEN status is not changed. However, UPEN can be cleared by software. The port A wake-up and interrupt can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake-up the device by mask option. Awakening from Port A stimulus, the program will resume execution of the next instruction. · Normal mode or Green mode to Sleep mode: Any valid interrupts from Sleep mode or Idle mode may cause two sequences. One is if the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. The other is if the interrupt is enabled and the stack is not full, the regular interrupt response takes place. It is necessary to mention that if an interrupt request flag is set to ²1² before entering the Sleep mode or Idle mode, the wake-up function of the related interrupt will be disabled. Step 1: Clear MODE0 to 0 Step 2: Execute HALT instruction After Step 2, operation mode is changed to Sleep mode, the UPEN and MODE1 are cleared to 0 by hardware. · Normal mode or Green mode to Idle mode: Step 1: Set MODE0 to 1 Step 2: Execute HALT instruction After Step 2, operation mode is changed to Idle mode, the UPEN and MODE1 are cleared to 0 by hardware. Register MODE (26H) HT95L100/10P Label Bits R/W Function ¾ 4~0 RO Unused bit, read as ²0² UPEN 5 RW 1: Enable frequency up conversion function to generate 3.58MHz 0: Disable frequency up conversion function to generate 3.58MHz MODE0 6 RW 1: Disable 32768Hz oscillator while the HALT instruction is executed (Idle mode) 0: Enable 32768Hz oscillator while the HALT instruction is executed (Sleep mode) MODE1 7 RW 1: Select 3.58MHz as CPU system clock 0: Select 32768Hz as CPU system clock Operation mode description HALT Instruction MODE1 MODE0 UPEN Operation Mode 32768Hz 3.58MHz System Clock Not execute 1 X 1 Normal Not execute 0 X 0 Green ON ON 3.58MHz ON OFF 32768Hz Be executed 0 0 0 Sleep ON OFF HALT Be executed 0 1 0 Idle OFF OFF HALT Note: ²X² means don¢t care Rev. 0.10 13 October 1, 2002 Preliminary Once a Sleep mode or Idle mode wake-up event occurs, it will take SST delay time (1024 system clock period) to resume to Green mode. In other words, a dummy period is inserted after a wake-up. If the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. HT95L100/10P H A L T W D T E x te rn a l W a rm W D T tim e - o u t C o ld R e s e t R E S S S T 1 0 - b it R ip p le C o u n te r S Y S C L K S y s te m To minimize power consumption, all the I/O pins should be carefully managed before entering the Sleep mode or Idle mode. R e s e t R e s e t Reset configuration V D D The Sleep mode or Idle mode is initialized by the HALT instruction and results in the following. · The system clock will be turned off. R E S tS S T S S T T im e - o u t · The WDT function will be disabled if the WDT clock source is the instruction clock. C h ip · The WDT function will be disabled if the WDT clock R e s e t Reset timing chart source is the 32768Hz in Idle mode. · The WDT will still function if the WDT clock source is By examining the processor status flags PD and TO, the software program can distinguish between the different ²chip resets². the WDT OSC. · If the WDT function is still enabled, the WDT counter and WDT prescaler will be cleared and recounted again. · The contents of the on chip RAM and registers remain unchanged. · All the I/O ports maintain their original status. · The flag PD is set and the flag TO is cleared by hard- TO PD 0 0 Power on reset u u External reset during Normal mode or Green mode 0 1 External reset during Sleep mode or Idle mode 1 u WDT time-out during Normal mode or Green mode 1 1 WDT time-out during Sleep mode or Idle mode ware. Reset There are three ways in which a reset can occur. · Power on reset. · A low pulse onto RES pin. · WDT time-out. Note: ²u² means ²unchanged² After these reset conditions, the Program Counter and Stack Pointer will be cleared to 0. The functional units chip reset status are shown below: To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system is reset or awakes from the Sleep or Idle operation mode. V Reset Condition D D Program Counter 000H Interrupt Disabled Prescaler Cleared WDT Cleared After a master reset, WDT begins counting. (If WDT function is enabled by mask option) 1 0 0 k W Timer/Event Counter 0/1 Off R E S 0 .1 m F Input/output Port Input mode Stack Pointer Points to the top of the stack Reset circuit Rev. 0.10 14 October 1, 2002 Preliminary HT95L100/10P When the reset conditions occurred, some registers may be changed or unchanged. Reset Conditions Register Addr. IAR0 MP0 Power On RES Pin RES Pin (Sleep/Idle) WDT WDT (Sleep/Idle) 00H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 01H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu IAR1 02H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu MP1 03H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu BP 04H ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---u uuuu ACC 05H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu PCL 06H 0000H 0000H 0000H 0000H 0000H TBLP 07H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH 08H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu WDTS 09H 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu STATUS 0AH --00 xxxx --uu uuuu --01 uuuu --1u uuuu --11 uuuu INTC0 0BH -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu TMR0H 0CH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TMR0L 0DH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TMR0C 0EH 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u---- TMR1H 0FH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TMR1L 10H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TMR1C 11H 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u---- PA 12H 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 13H 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PB 14H 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 15H 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu DialerIO 16H 111x xxxx 111x xxxx 111x xxxx 111x xxxx uuuu uuuu PE 1AH ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu PEC 1BH ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu INTC1 1EH -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu DTMFC 20H ---- -0-1 ---- -0-1 ---- -0-1 ---- -0-1 ---- -u-u DTMFD 21H 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu LINE 22H 0--- ---- u--- ---- u--- ---- u--- ---- u--- ---- RTCC 24H 0-0- ---- u-u- ---- u-u- ---- u-u- ---- u-u- ---- MODE 26H 000- ---- 00u- ---- 000- ---- 00u- ---- 000- ---- LCDIO 28H --0- ---- --u- ---- --u- ---- --u- ---- --u- ---- LCDC 2DH 0000 -0-- uuuu -u-- uuuu -u-- uuuu -u-- uuuu -u-- PFDC 2EH 0000 ---- 0000 ---- 0000 ---- 0000 ---- uuuu ---- PFDD 2FH 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu x u u u u RAM (Data & LCD) Note: ²u² means ²unchanged² ²x² means ²unknown² ²-² means ²unused² Rev. 0.10 15 October 1, 2002 Preliminary register (16-bit). The Timer/Event Counter 0 preload register is changed by writing TMR0H operations. Writing TMR0L will keep the Timer/Event Counter 0 preload register unchanged. Timer/Event Counter Two timer/event counters (TMR0, TMR1) are implemented in the telephone controller series. The Timer/Event Counter 0 and Timer/Event Counter 1 contain 16-bits programmable count-up counter and the clock may come from an external source or internal source. For TMR0 internal source is instruction clock (system clock/4). For TMR1 internal source is 32768Hz. Reading TMR0H latches the TMR0L into the low byte buffer to avoid a false timing problem. Reading TMR0L returns the contents of the low byte buffer. In other words, the low byte of the Timer/Event Counter 0 can not be read directly. It must read the TMR0H first to make the low byte contents of Timer/Event Counter 0 be latched into the buffer. Using the 32768Hz clock or instruction clock, there is only one reference time-base. The external clock input allows the user to count external events, measure time intervals or pulse width, or generate an accurate time base. There are 3 registers related to the Timer/Event Counter 1; TMR1H, TMR1L, TMR1C. The Timer/Event Counter 1 operates in the same manner as the Timer/Event Counter 0. There are 3 registers related to Timer/Event Counter 0; TMR0H, TMR0L, TMR0C. Writing TMR0L only writes the data into a low byte buffer, but writing TMR0H simultaneously writes the data along with the contents of the low byte buffer into the Timer/Event Counter 0 preload T im e r 0 : In s tr u c tio n c lo c k ( s y s te m T im e r 1 : 3 2 7 6 8 H z The TMR0C is the Timer/Event Counter 0 control register, which defines the Timer/Event Counter 0 options. The Timer/Event Counter 1 has the same options as the c lo c k /4 ) D a ta B u s T M 1 T M 0 IN T /T M R 1 T M R 0 T im e r /E v e n t C o u n te r 0 /1 P r e lo a d R e g is te r T E R e lo a d T im e r /e v e n t C o u n te r 0 /1 P u ls e W id th M e a s u re m e n t M o d e C o n tro l T M 1 T M 0 T O N HT95L100/10P L o w O v e r flo w to In te rru p t B y te B u ffe r Timer/Event Counter 0/1 Register Label Bits R/W ¾ 0~2 RO Unused bit, read as ²0² TE 3 RW To define the TMR0/TMR1 active edge of timer For event count or Timer mode (0=active on low to high; 1=active on high to low) For pulse width measurement mode (0=measures low pulse width; 1=measures high pulse width) TON 4 RW To enable/disable timer counting (0=disabled; 1=enabled) ¾ 5 RO Unused bit, read as ²0² RW To define the operating mode Bit 7, 6=01, Event count mode (external clock) Bit 7, 6=10, Timer mode Bit 7, 6=11, Pulse width measurement mode Bit 7, 6=00, Unused TMR0C (0EH) TMR1C (11H) Function TM0 TM1 6 7 Register Bits R/W TMR0H (0CH) 0~7 RW Function Timer/Event Counter 0 higher-order byte register TMR0L (0DH) 0~7 RW Timer/Event Counter 0 lower-order byte register TMR1H (0FH) 0~7 RW Timer/Event Counter 1 higher-order byte register TMR1L (10H) 0~7 RW Timer/Event Counter 1 lower-order byte register Rev. 0.10 16 October 1, 2002 Preliminary For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction ²MOV A,[m]² (m=12H, 14H or 1AH). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Timer/Event Counter 0 and is defined by TMR1C. The timer/event counter control registers define the operating mode, counting enable or disable and active edge. The TM0, TM1 bits define the operating mode. The event count mode is used to count external events, which means the clock source comes from an external (TMR0 or INT/TMR1) pin. The timer mode functions as a normal timer with the clock source coming from instruction clock (TMR0) or 32768Hz (TMR1). The pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR0 or INT/TMR1). The counting is based on the 32768Hz clock for TMR1 or instruction clock for TMR0. Each I/O line has its own control register (PAC,PBC, PEC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input can be reconfigured dynamically under software control. To make one I/O line to function as an input line, the corresponding latch of the control register must be written with a ²1². The pull-high resistance shows itself automatically if the pull-high option is selected. The input source also depends on the control register. If the control register bit is ²1², the input will read the pad state. If the control register bit is ²0², the contents of the latches will move to the internal bus. The latter is possible in the ²read-modify-write² instruction. For output function, CMOS is the only configuration. Each bit of these input/output latches can be set or cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H or 1AH) instructions. In the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to FFFFH. If an overflow occurs, the counter is reloaded from the timer/event counter preload register and generates the corresponding interrupt request flag (T0F/T1F) at the same time. In pulse width measurement mode with the TON and TE bits equal to 1, once the TMR0/TMR1 pin has received a transient from low to high (or high to low; if the TE bit is 0) it will start counting until the TMR0/TMR1 pin returns to the original level and resets the TON. The measured result will remain in the timer/event counter even if the activated transient occurs again. In other words, only 1 cycle measurement can be done. Until setting the TON, the cycle measurement will function again as long as it receives further transient pulse. Note that, in this operating mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter preload register and continue to measure the width and issues the interrupt request just like the other two modes. Some instructions first input data and then follow the output operations. For example, ²SET [m].i², ²CLR [m].i², ²CPL [m]², ²CPLA [m]² read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. They are selected by mask option per bit. There is a pull-high option available for all I/O lines. Once the pull-high option of an I/O line is selected, the I/O lines have pull-high resistor. Otherwise, the pull-high resistor is absent. It should be noted that a non-pull-high I/O line operating in input mode may cause a floating state. To enable the counting operation, the timer on bit (TON) should be set to 1. In the pulse width measurement mode, the TON will be cleared automatically after the measurement cycle is completed. But in the other two modes the TON can only be reset by instruction. The overflow of the timer/event counter is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I/ET1I can disable the corresponding interrupt service. I/O port pull-high, wake-up function are selected by mask option In the case of timer/event counter off condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the timer/event counter is turned on, data written to the timer/event counter is reserved only in the timer/event counter preload register. The timer/event counter will go on operating until an overflow occurs. Input I/O Port Output PA CMOS Selected per bit Selected per bit PB CMOS Selected per bit X PE CMOS Selected per nibble X Pull-high Resistor Wake-up Function Note: X: unavailable The PE0~PE3 and SEG16~SEG19 share the same pads. They can be selected per nibble by software option at any time. When the PE0~PE3 are not selected, the I/O port control register, PEC (1BH) could be read/write-able and be used as a general user RAM, but this function is not available for register PE (1AH). Input/output ports There are 20 bidirectional input/output lines in the telephone controller, labeled as PA, PB and PE. All of these I/O ports can be used for input and output operations. Rev. 0.10 HT95L100/10P 17 October 1, 2002 Preliminary Register Label Bits R/W ¾ 0~4 6~7 RO Unused bit, read as ²0² SPE0 5 RW 0: SEG16~ SEG19 pins are LCD segment output 1: SEG16~ SEG19 pins are PE0~PE3 pins LCDIO (28H) Function DTMF generator The power down mode (D_PWDN=1) will terminate all the DTMF generator function, however, the registers DTMFC and DTMFD are accessible at this power down mode. The DTMF (Dual Tone Multiple-Frequency) signal generator is implemented in the telephone controller. It can generate 16 dual tones and 8 single tones from the DTMF pin. This generators also support power down, tone on/off function. The DTMF generator clock source is 3.58MHz, before using this function, the system operation mode must be at Normal mode. Register DTMFC (20H) DTMFD (21H) HT95L100/10P The duration of DTMF output should be handled by the software. DTMFD register value could be changed as desired, the DTMF pin will output the new dual-tone simultaneously. Label Bits R/W Function D_PWDN 0 RW DTMF generator power down 1: DTMF generator is at power down mode. 0: DTMF generator is at operation mode. ¾ 1 RO Unused bit, read as ²0² TONE 2 RW Tone output enable 1: DTMF signal output is enabled. 0: DTMF signal output is disabled. ¾ 7~3 RO Unused bit, read as ²0² TC4~TC1 3~0 RW To set high group frequency TR4~TR1 7~4 RW To set low group frequency The DTMF pin output is controlled by the combination of the D_PWDN, TONE, TR~TC value. Control Register Bits D_PWDN DTMF Pin Output Status TONE TR4~TR1/TC4~TC1 1 x x 0 0 0 x 1/2 VDD 0 1 0 1/2 VDD 0 1 Any valid value 16 dual tones or 8 signal tones, bias with 1/2 VDD D _ P D W N = 0 D _ P D W N = 1 1 /2 V D D T O N E = 1 T O N E = 0 T O N E = 1 T O N E = 0 T O N E = 1 T O N E = 0 A ll th e tim in g o f th e T O N E = 1 a n d T O N E = 0 a r e d e te r m in e d b y s o ftw a r e DTMF output Rev. 0.10 18 October 1, 2002 Preliminary HT95L100/10P Tone frequency Output Frequency (Hz) % Error Specified Actual 697 699 +0.29% 770 766 -0.52% 852 847 -0.59% 941 948 +0.74% 1209 1215 +0.50% 1336 1332 -0.30% 1477 1472 -0.34% % Error does not contain the crystal frequency shift DTMF frequency selection table: register DTMFD[21H] Low Group High Group DTMF Output TR4 TR3 TR2 TR1 TC4 TC3 TC2 TC1 Low High DTMF Code 0 0 0 1 0 0 0 1 697 1209 1 0 0 0 1 0 0 1 0 697 1336 2 0 0 0 1 0 1 0 0 697 1477 3 0 0 0 1 1 0 0 0 697 1633 A 0 0 1 0 0 0 0 1 770 1209 4 0 0 1 0 0 0 1 0 770 1336 5 0 0 1 0 0 1 0 0 770 1477 6 0 0 1 0 1 0 0 0 770 1633 B 0 1 0 0 0 0 0 1 852 1209 7 0 1 0 0 0 0 1 0 852 1336 8 0 1 0 0 0 1 0 0 852 1477 9 0 1 0 0 1 0 0 0 852 1633 C 1 0 0 0 0 0 0 1 941 1209 * 1 0 0 0 0 0 1 0 941 1336 0 1 0 0 0 0 1 0 0 941 1477 # 1 0 0 0 1 0 0 0 941 1633 D 0 0 0 1 0 0 0 0 697 0 0 1 0 0 0 0 0 770 0 1 0 0 0 0 0 0 852 1 0 0 0 0 0 0 0 941 Single tone for testing only 0 0 0 0 0 0 0 1 1209 0 0 0 0 0 0 1 0 1336 0 0 0 0 0 1 0 0 1477 0 0 0 0 1 0 0 0 1633 Writing other values to TR4~TR1, TC4~TC1 may generate an unpredictable tone. Rev. 0.10 19 October 1, 2002 Preliminary HT95L100/10P Dialer I/O function A special dialer I/O circuit is built into the telephone controller for dialing application. These specially designed I/O cells allows the controller to work under a low voltage condition that usually happens when the subscriber¢s loop is long. Dialer I/O pin function: Name I/O Description XMUTE NMOS Output XMUTE pin output is controlled by software. This is an NMOS open drain structure pulled to VSS during dialing signal transmission. Otherwise, it is an open circuit. XMUTE is used to mute the speech circuit when transmitting the dialer signal. DNPO NMOS Output DNPO pin is an NMOS output, usually by means of software to make/break the line. This pin is only controlled by software. PO CMOS Output This pin is controlled by the HKS, HFI and HDI pins. When PO pin is high, the telephone line is make. When PO pin is low, the telephone line is break. HKS Schmitt Trigger Input This pin controls the PO pin directly. This pin is used to monitor the status of the hook-switch and its combination with HFI/HDI can control the PO pin output to make or break the line. A rising edge to HKS pin will cause the dialer I/O to be on-hook status and generate an interrupt, its vector is 18H. A falling edge to HKS pin will cause the dialer I/O to be off-hook status and clear HFO and HDO flags to 0. This falling edge will also generate an interrupt, its vector is 18H. HDO CMOS Output This pin is controlled directly by HDI, HKS and HFI pin. When HDO pin is high, the hold-line function is enabled and PO outputs a high signal to make the line. HDI Schmitt Trigger Input A low pulse to HDI pin (hold-line function request) will clear HFO to 0 and toggle HDO and generates an interrupt, its vector is 18H. This pin controls the HFO and HDO pins directly. This pin is functional only when the line is made, that is, off-hook or hand-free (PO output high signal). HFO CMOS Output This pin is controlled directly by HFI, HDI and HKS pins. When HFO pin is high, the hand-free function is enabled and PO outputs a high signal to make the line. HFI Schmitt Trigger Input A high pulse to HFI pin (hand-free function request) will clear HDO to 0 and toggle HFO and generates an interrupt, its vector is 18H. This pin controls the PO, HFO and HDO pins directly. The following are the recommended circuit for HFI and HDI pins. V D D V 1 0 k W H D I P in H F I P in 0 .1 m F Rev. 0.10 In te r n a l P u ll- lo w 2 0 0 k W 1 0 k W 20 D D In te r n a l P u ll- h ig h 2 0 0 k W 0 .1 m F October 1, 2002 Preliminary HT95L100/10P Phone controller also supports the dialer I/O flag to monitor the dialer status. Register DIALERIO (16H) Label Bits R/W Function HFI 0 RO 1: The HFI pin level is 1. 0: The HFI pin level is 0. HFO 1 RO 1: The HFO pin level is 1. 0: The HFO pin level is 0. HDI 2 RO 1: The HDI pin level is 1. 0: The HDI pin level is 0. HDO 3 RO 1: The HDO pin level is 1. 0: The HDO pin level is 0. HKS 4 RO 1: The HKS pin level is 1. 0: The HKS pin level is 0. SPO 5 RW 1: The PO pin is controlled by the combination of the HKS, HFI and HDI pin. 0: The PO pin level is set to 0 by software. SDNPO 6 RW 1: The DNPO pin level is set to floating by software. 0: The DNPO pin level is set to 0 by software. XMUTE 7 RW 1: The XMUTE pin is set to floating by software. 0: The XMUTE pin is set to 0 by software. The SPO flag is special designed to control the PO. When the flag SPO is set to 1, the PO pin is controlled by the combination of the HKS pin, HFI pin and HDI pin. The PO pin will always be 0 if the flag SPO=0. The relation between the Dialer I/O function (SPO=1) Dialer I/O Pin (Flag) Status Dialer Function Result HKS HFO HDO PO DNPO Telephone Line On-hook 1 0 0 0 floating break On-hook & Hand-free 1 1 0 1 floating make On-hook & Hold-line 1 0 1 1 floating make Off-hook 0 0 0 1 floating make Off-hook & Hand-free 0 1 0 1 floating make Off-hook & Hold-line 0 0 1 1 floating make The following describes the dialer I/O function status machine figure: Off-hook: A falling edge to HKS pin On-hook: A rising edge to HKS pin H D I HFI: A high pulse to HFI pin (Hand-free request is generated.) O n -h o o k H F I O ff-h o o k H a n d -fre e O n -h o o k HDI: A low pulse to HDI pin (Hold-line request is generated.) O ff-h o o k O n -h o o k O ff-h o o k O n -h o o k H a n d -fre e H F I H F I H D I Rev. 0.10 H F I H D I O ff-h o o k H D I O ff-h o o k H o ld - lin e H D I O ff-h o o k O n -h o o k O n -h o o k H o ld - lin e 21 October 1, 2002 Preliminary HT95L100/10P Line control function Register LINE (22H) Label Bits R/W Function ¾ 6~0 RO Unused bit, read as ²0² LINEC 7 RW 1: Enable the line control function 0: Disable the line control function The line control function is enabled by the flag LINEC Conditions LINEC Operation Mode Source to Enable Line Control Function 1 Normal or Green mode RTC time out interrupt 1 Sleep mode Port A wake-up RTC time out interrupt 1 Idle mode Port A wake-up When the line control source is activated, the PO pin will be set to high signal. Clearing LINEC to 0 will terminate the line control function and drive PO pin outputs low signal. R T C In te rru p t L in e C o n tr o l C ir c u it P o r t A W a k e - u p fu n c tio n L IN E C P O = 1 E n a b le /D is a b le RTC function Register RTCC (24H) Label Bits R/W Function ¾ 6, 4~0 RO Unused bit, read as ²0² RTCEN 5 RW 1: Enable RTC function 0: Disable RTC function RTCTO 7 RW 1: RTC time-out occurs 0: RTC time-out not occurs The real time clock (RTC) is used to supply a regular internal interrupt. Its time-out period is 1000ms. If the RTC time-out occurs, the interrupt request flag RTCF and the RTCTO flag will be set to 1. The interrupt vector for the RTC is 14H. When the interrupt subroutine is serviced, the interrupt request flag (RTCF) will be cleared to 0, but the flag RTCTO remain in its original value. If the RTCTO flag is not cleared, next RTC time-out interrupt will occur. V R 1 .1 5 V R e fe r e n c e V o lta g e 1 R 2 L B F G L B IN L B E N The battery low threshold is determined by external R1 and R2 resistors. Low battery detection 1.15= The phone controller provides a circuit that detects the LBIN pin voltage level. To enable this detection function, the LBEN should be written as 1. Once this function is enabled, the detection circuit needs 50ms to be stable. After that, the user could read the result from LBFG. The low battery detect function will consume power. For power saving, write 0 to LBEN if the low battery detection function is unnecessary. Rev. 0.10 D E T VDET ´ R2 1.15 ´ (R1+ R2) ® VDET= R1+ R2 R2 If we want to detect VDET=2.4V then 2.4V= 22 1.15 ´ (R1+ R2) ® R1=1.087R2 R2 October 1, 2002 Preliminary HT95L100/10P provides 4 pins to be selected to SEGMENT output pins or I/O pins. LCD driver The LCD driver can directly drive an LCD panel with 1/8 duty and 1/4 bias. The frame of this LCD driver is fixed for 64Hz. LCD display memory The phone controller provides an area on embedded data memory for LCD display. The LCD display memory are located at bank 1BH and can be read and written to, only by indirect addressing mode using MP1. When data is written into the display data area it is automatically read by the LCD driver which then generates the corresponding LCD driving signals, to turn the display On or Off, a ²1² or ²0² is written to the corresponding bit of the display memory, respectively. All of the LCD display memories are with random values after the power on reset and unchanged after other reset conditions. LCD driver uses the voltage of the VLCD pin as the power source. To adjust the view angle, the programmer can select the real LCD power by the flags VCON0 and VCON1. The flag LCDON is used to turn On/Off the LCD display. Note that the VLCD voltage must equal or be less than VDD. Segment/Common to I/O selection For the flexible purpose, some of the LCD SEGMENT p in s a r e s h a r ed w i t h t h e i nput / out p u t p o r t . Register Label Bits R/W LBEN 2 RW Low battery detection switch 0: disable the low battery detection 1: enable the low battery detection ¾ 3,1,0 RO Unused bit, read as ²0² LBFG 4 RO Low battery detection flag 1: LBIN pin voltage is less than 1.25V 0: LBIN pin voltage is not less than 1.25V LCDC (2DH) LCDIO (28H) HT95L100/10P Function VCON0 VCON1 5 6 RW LCD contrast adjusting Bit6,5=00: LCD voltage supply is 0.66´VLCD Bit6,5=10: LCD voltage supply is 0.82´VLCD Bit6,5=01: LCD voltage supply is 0.93´VLCD Bit6,5=11: LCD voltage supply is 1.00´VLCD LCDON 7 RW 1: Turn on the LCD display 0: Turn off the LCD display ¾ 4~0 7~6 RO Unused bit, read as ²0² SPE0 5 RW 0: SEG16~SEG19 pins are LCD segment output 1: SEG16~SEG19 pins are PE0~PE3 pins COM7 to COM0 for HT95L100/10P Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 8CH SEG0 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 8DH SEG1 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 ¾ ¾ COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 9EH SEG18 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 9FH SEG19 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 Rev. 0.10 23 October 1, 2002 Preliminary HT95L100/10P PFD generator Register PFDC (2EH) Label Bits R/W ¾ 3~0 RO Unused bit, read as ²0² PFDEN 4 RW 1: Enable PFD output 0: Disable PFD output, the MUSIC pin output low level. PRES0 PRES1 5 6 RW Bit6, 5=00: Prescaler output= PFD frequency source/1 Bit6, 5=01: Prescaler output= PFD frequency source/2 Bit6, 5=10: Prescaler output= PFD frequency source/4 Bit6, 5=11: Prescaler output= PFD frequency source/8 FPFD 7 RW 1: The PFD frequency source is 3.58MHz/4 0: The PFD frequency source is 32768Hz ¾ 7~0 RW PFD data register PFDD (2FH) Function The PFD (programmable frequency divider) is implemented in the phone controller. It is composed of two portions: a prescaler and a general counter. The prescaler is controlled by the register bits, PRES0 and PRES1. The general counter is programmed by an 8-bit register PFDD. The source for this generator can be selected from 3.58MHz/4 or 32768Hz. To enable the PFD output, write 1 to the PFDEN bit. The PFDD is inhibited to write while the PFD is disabled. To modify the PFDD contents, the PFD must be enabled. When the generator is disabled, the PFDD is cleared by hardware. 3 2 7 6 8 H z 3 .5 8 M H z /4 P r e s c a le r P r e s c a le r O u tp u t P F D D M U S IC P F D E N P R E S 1 , P R E S 0 PFD output frequency= P F D O u tp u t Prescaler output , where N=the value of the PFDD 2 ´ (N + 1) Mask option table The following shows many kinds of mask options in the telephone controller. All these options should be defined in order to ensure proper system functions. Name Mask Option WDT WDT source selection RC®Select the WDT OSC to be the WDT source. T1®Select the instruction clock to be the WDT source. 32kHz®Select the external 32768Hz to be the WDT source. Disable®Disable WDT function. WDTinstr This option defines how to clear the WDT by instruction. One clear instruction®The ²CLR WDT² can clear the WDT. Two clear instructions®Only when both of the ²CLR WDT1² and ²CLR WDT2² have been executed, then WDT can be cleared. Wake-up PA Port A wake-up selection. Define the activity of wake-up function. All port A have the capability to wake-up the chip from a HALT. This wake-up function is selected per bit. Pull-high Port A Pull-high Port B Pull-high Port E Pull-high option. This option determines whether the pull-high resistance is viable or not. Port A pull-high option is selected per bit. Port B pull-high option is selected per bit. Port E pull-high option is selected per nibble. Rev. 0.10 24 October 1, 2002 Preliminary HT95L100/10P Application Circuits 2 2 M W 1 0 0 k W O ff-h o o k T ip O n -h o o k A 9 2 R in g 3 .3 k W 3 3 0 k W 2 2 0 k W 3 3 k W 1 0 m F 1 N 4 1 4 8 2 .2 k W 1 .5 k W 1 N 4 1 4 8 4 7 k W 1 N 4 1 4 8 1 m F 1 0 0 k W A 4 2 1 N 4 1 4 8 1 0 0 k W H a n d fre e 2 2 0 k W 1 5 0 k W 1 m F B a tte ry 1 .5 ´ 3 = 4 .5 V 1 0 k W 0 .0 2 m F 2 7 0 k W V D D S p e e c h N e tw o rk 5 .1 V 1 0 0 k W 0 .1 m F 0 .1 m F 1 0 0 m F V D D H F I P O H D I V D D H K S H F O 0 .1 m F D T M F X M U T E I/O M U S IC V D D V L C D 1 0 0 k W R E S 0 .1 m F H T 9 5 L 1 0 0 /1 0 P V D D L B IN M E M O R Y S T O R E A M D IA L IN G H O L D P M A B R M O N T U E W E D T H R F R I S A T S U N C O M M O N S E G M E N T L C D P a n n e l I/O I/O X 1 X 2 X C V S S 1 5 k W 1 2 3 K e y 1 K e y 5 K e y 9 4 5 6 K e y 2 K e y 6 K e y 1 0 7 8 9 K e y 3 K e y 7 K e y 1 1 * /T 0 # K e y 4 K e y 8 K e y 1 2 3 2 7 6 8 H z 3 n F 5 0 n F K e y M a tr ix Rev. 0.10 25 October 1, 2002 Preliminary HT95L100/10P Instruction Set Summary Description Instruction Cycle Flag Affected Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Rev. 0.10 26 October 1, 2002 Preliminary HT95L100/10P Instruction Cycle Flag Affected Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PD TO(4),PD(4) TO(4),PD(4) None None TO,PD Mnemonic Description Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Ö: Flag is affected -: Flag is not affected (1) : If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). (2) : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. (3) (1) : (4) Rev. 0.10 and (2) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PD are cleared. Otherwise the TO and PD flags remain unchanged. 27 October 1, 2002 Preliminary HT95L100/10P Instruction Definition ADC A,[m] Add data memory and carry to the accumulator Description The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. Operation ACC ¬ ACC+[m]+C Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ Ö Ö Ö Ö ADCM A,[m] Add the accumulator and carry to data memory Description The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. Operation [m] ¬ ACC+[m]+C Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ Ö Ö Ö Ö ADD A,[m] Add data memory to the accumulator Description The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. Operation ACC ¬ ACC+[m] Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ Ö Ö Ö Ö ADD A,x Add immediate data to the accumulator Description The contents of the accumulator and the specified data are added, leaving the result in the accumulator. Operation ACC ¬ ACC+x Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ Ö Ö Ö Ö ADDM A,[m] Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ¬ ACC+[m] Affected flag(s) Rev. 0.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ Ö Ö Ö Ö 28 October 1, 2002 Preliminary HT95L100/10P AND A,[m] Logical AND accumulator with data memory Description Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²AND² [m] Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ AND A,x Logical AND immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²AND² x Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ANDM A,[m] Logical AND data memory with the accumulator Description Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. Operation [m] ¬ ACC ²AND² [m] Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ CALL addr Subroutine call Description The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Operation Stack ¬ PC+1 PC ¬ addr Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] ¬ 00H Affected flag(s) Rev. 0.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 29 October 1, 2002 Preliminary HT95L100/10P CLR [m].i Clear bit of data memory Description The bit i of the specified data memory is cleared to 0. Operation [m].i ¬ 0 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ CLR WDT Clear Watchdog Timer Description The WDT is cleared (clears the WDT). The power down bit (PD) and time-out bit (TO) are cleared. Operation WDT ¬ 00H PD and TO ¬ 0 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ 0 0 ¾ ¾ ¾ ¾ CLR WDT1 Preclear Watchdog Timer Description Together with CLR WDT2, clears the WDT. PD and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PD flags remain unchanged. Operation WDT ¬ 00H* PD and TO ¬ 0* Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ 0* 0* ¾ ¾ ¾ ¾ CLR WDT2 Preclear Watchdog Timer Description Together with CLR WDT1, clears the WDT. PD and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PD flags remain unchanged. Operation WDT ¬ 00H* PD and TO ¬ 0* Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ 0* 0* ¾ ¾ ¾ ¾ CPL [m] Complement data memory Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] ¬ [m] Affected flag(s) Rev. 0.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ 30 October 1, 2002 Preliminary HT95L100/10P CPLA [m] Complement data memory and place result in the accumulator Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. Operation ACC ¬ [m] Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ DAA [m] Decimal-Adjust accumulator for addition Description The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. Operation If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö DEC [m] Decrement data memory Description Data in the specified data memory is decremented by 1. Operation [m] ¬ [m]-1 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ DECA [m] Decrement data memory and place result in the accumulator Description Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. Operation ACC ¬ [m]-1 Affected flag(s) Rev. 0.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ 31 October 1, 2002 Preliminary HT95L100/10P HALT Enter power down mode Description This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is cleared. Operation PC ¬ PC+1 PD ¬ 1 TO ¬ 0 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ 0 1 ¾ ¾ ¾ ¾ INC [m] Increment data memory Description Data in the specified data memory is incremented by 1 Operation [m] ¬ [m]+1 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ INCA [m] Increment data memory and place result in the accumulator Description Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. Operation ACC ¬ [m]+1 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ JMP addr Directly jump Description The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Operation PC ¬addr Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC ¬ [m] Affected flag(s) Rev. 0.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 32 October 1, 2002 Preliminary HT95L100/10P MOV A,x Move immediate data to the accumulator Description The 8-bit data specified by the code is loaded into the accumulator. Operation ACC ¬ x Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ MOV [m],A Move the accumulator to data memory Description The contents of the accumulator are copied to the specified data memory (one of the data memories). Operation [m] ¬ACC Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ NOP No operation Description No operation is performed. Execution continues with the next instruction. Operation PC ¬ PC+1 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ OR A,[m] Logical OR accumulator with data memory Description Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²OR² [m] Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ OR A,x Logical OR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²OR² x Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ORM A,[m] Logical OR data memory with the accumulator Description Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ¬ACC ²OR² [m] Affected flag(s) Rev. 0.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ 33 October 1, 2002 Preliminary HT95L100/10P RET Return from subroutine Description The program counter is restored from the stack. This is a 2-cycle instruction. Operation PC ¬ Stack Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ RET A,x Return and place immediate data in the accumulator Description The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Operation PC ¬ Stack ACC ¬ x Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ RETI Return from interrupt Description The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Operation PC ¬ Stack EMI ¬ 1 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ RL [m] Rotate data memory left Description The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. Operation [m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 ¬ [m].7 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ RLA [m] Rotate data memory left and place result in the accumulator Description Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 ¬ [m].7 Affected flag(s) Rev. 0.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 34 October 1, 2002 Preliminary HT95L100/10P RLC [m] Rotate data memory left through carry Description The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. Operation [m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 ¬ C C ¬ [m].7 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö RLCA [m] Rotate left through carry and place result in the accumulator Description Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. Operation ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 ¬ C C ¬ [m].7 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö RR [m] Rotate data memory right Description The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. Operation [m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 ¬ [m].0 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ RRA [m] Rotate right and place result in the accumulator Description Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 ¬ [m].0 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ RRC [m] Rotate data memory right through carry Description The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 ¬ C C ¬ [m].0 Affected flag(s) Rev. 0.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö 35 October 1, 2002 Preliminary HT95L100/10P RRCA [m] Rotate right through carry and place result in the accumulator Description Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. Operation ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 ¬ C C ¬ [m].0 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö SBC A,[m] Subtract data memory and carry from the accumulator Description The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. Operation ACC ¬ ACC+[m]+C Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ Ö Ö Ö Ö SBCM A,[m] Subtract data memory and carry from the accumulator Description The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. Operation [m] ¬ ACC+[m]+C Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ Ö Ö Ö Ö SDZ [m] Skip if decrement data memory is 0 Description The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m]-1)=0, [m] ¬ ([m]-1) Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ SDZA [m] Decrement data memory and place result in ACC, skip if 0 Description The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m]-1)=0, ACC ¬ ([m]-1) Affected flag(s) Rev. 0.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 36 October 1, 2002 Preliminary HT95L100/10P SET [m] Set data memory Description Each bit of the specified data memory is set to 1. Operation [m] ¬ FFH Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ SET [m]. i Set bit of data memory Description Bit i of the specified data memory is set to 1. Operation [m].i ¬ 1 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ SIZ [m] Skip if increment data memory is 0 Description The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m]+1)=0, [m] ¬ ([m]+1) Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ SIZA [m] Increment data memory and place result in ACC, skip if 0 Description The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m]+1)=0, ACC ¬ ([m]+1) Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ SNZ [m].i Skip if bit i of the data memory is not 0 Description If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if [m].i¹0 Affected flag(s) Rev. 0.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 37 October 1, 2002 Preliminary HT95L100/10P SUB A,[m] Subtract data memory from the accumulator Description The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. Operation ACC ¬ ACC+[m]+1 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ Ö Ö Ö Ö SUBM A,[m] Subtract data memory from the accumulator Description The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. Operation [m] ¬ ACC+[m]+1 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ Ö Ö Ö Ö SUB A,x Subtract immediate data from the accumulator Description The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. Operation ACC ¬ ACC+x+1 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ Ö Ö Ö Ö SWAP [m] Swap nibbles within the data memory Description The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. Operation [m].3~[m].0 « [m].7~[m].4 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ SWAPA [m] Swap data memory and place result in the accumulator Description The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ¬ [m].7~[m].4 ACC.7~ACC.4 ¬ [m].3~[m].0 Affected flag(s) Rev. 0.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 38 October 1, 2002 Preliminary HT95L100/10P SZ [m] Skip if data memory is 0 Description If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if [m]=0 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ SZA [m] Move data memory to ACC, skip if 0 Description The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if [m]=0 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ SZ [m].i Skip if bit i of the data memory is 0 Description If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if [m].i=0 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ TABRDC [m] Move the ROM code (current page) to TBLH and data memory Description The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. Operation [m] ¬ ROM code (low byte) TBLH ¬ ROM code (high byte) Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ TABRDL [m] Move the ROM code (last page) to TBLH and data memory Description The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ¬ ROM code (low byte) TBLH ¬ ROM code (high byte) Affected flag(s) Rev. 0.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 39 October 1, 2002 Preliminary HT95L100/10P XOR A,[m] Logical XOR accumulator with data memory Description Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. Operation ACC ¬ ACC ²XOR² [m] Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ XORM A,[m] Logical XOR data memory with the accumulator Description Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. Operation [m] ¬ ACC ²XOR² [m] Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ XOR A,x Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ¬ ACC ²XOR² x Affected flag(s) Rev. 0.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ 40 October 1, 2002 Preliminary HT95L100/10P Package Information 64-pin QFP (14´20) outline dimensions C H D 5 1 G 3 3 I 5 2 3 2 F A B E 2 0 6 4 K a J 1 Symbol A Rev. 0.10 1 9 Dimensions in mm Min. Nom. Max. 18.80 ¾ 19.20 B 13.90 ¾ 14.10 C 24.80 ¾ 25.20 D 19.90 ¾ 20.10 E ¾ 1 ¾ F ¾ 0.40 ¾ G 2.50 ¾ 3.10 H ¾ ¾ 3.40 I ¾ 0.10 ¾ J 1.15 ¾ 1.45 K 0.10 ¾ 0.20 a 0° ¾ 7° 41 October 1, 2002 Preliminary HT95L100/10P Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Sales Office) 11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Shanghai) Inc. 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Holmate Semiconductor, Inc. 48531 Warm Springs Boulevard, Suite 413, Fremont, CA 94539 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright Ó 2002 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 0.10 42 October 1, 2002