HOLTEK HT82J30R

HT82J30R/HT82J30A
16 Channel A/D MCU with SPI Interface
Technical Document
· Tools Information
· FAQs
· Application Note
Features
· Operating voltage:
· 6-level subroutine nesting
fSYS=4MHz: 2.2V~5.5V crystal clock mode
· 16 channel 8-bit resolution A/D converter
· fSYS=12MHz: 2.7V~3.7V RC clock mode
· 1 channel (6+2)-bit PWM output shared with an I/O
· 35 bidirectional I/O lines (max.)
line
· 2 interrupt inputs shared with I/O lines
· Bit manipulation instruction
· 8-bit programmable timer/event counter with overflow
· 15-bit table read instruction
interrupt and 7-stage prescaler
· 63 powerful instructions
· On-chip crystal and RC oscillator
· LVR reset voltage of 3V±0.3V
· Watchdog Timer
· All instructions executed in one or two machine
· 4096´15 program memory ROM
cycles
· PB2, PB3, PD4, PD7 can be optioned as either
· 216´8 data memory RAM
CMOS or NMOS outputs
· PFD function for sound generation
· Integrated dual SPI interfaces
· HALT function and wake-up feature reduces power
· 28-pin SKDIP/SOP and 44-pin QFP packages
consumption
· Up to 0.5ms instruction cycle with 8MHz system clock
at VDD=5V
General Description
interfaces, Power Down and wake-up functions, enhance the versatility of these devices to suit a wide
range of A/D application possibilities such as sensor
signal processing, motor driving, industrial control, consumer products, subsystem controllers, etc. With the
provision of dual SPI interfaces the devices are especially suitable for Joystick Encoder applications.
The HT82J30R/HT82J30A are 8-bit high performance,
RISC architecture microcontroller devices specifically
designed for A/D applications that interface directly to
analog signals, such as those from sensors.
The mask version HT82J30A is fully pin and functionally
compatible with the OTP version HT82J30R device.
The advantages of low power consumption, I/O flexibility, programmable frequency divider, timer functions,
oscillator options, multi-channel A/D Converter, Pulse
Width Modulation function, Watchdog timer, SPI
Rev. 1.00
The HT82J30A is under development and will be available soon.
1
December 20, 2006
HT82J30R/HT82J30A
Block Diagram
P A 5 /IN T 0 , P A 6 /IN T 1
T M R C
In te rru p t
C ir c u it
S T A C K
P ro g ra m
R O M
M
T M R
P ro g ra m
C o u n te r
IN T C
P A 3 /P F D
U
P r e s c a le r
M
M P
U
X
D a ta
M e m o ry
M
P W M
P D C
P O R T D , F
P D
M U X
In s tr u c tio n
D e c o d e r
P C C
S T A T U S
A L U
O S
R E
V D
V S
C 1
S
D
S
P O R T B
P B
L V R
A C C
U
fS
Y S
/4
W D T O S C
X
P D 0
P D 1
P D 2
P D 3
P D 4
P D 5
P D 7
P F 0
P F 1
P F 2
/P W
/S C
/S C
/S D
/S D
~ P
/S D
/S D
/S C
/S C
M
S _ A
K _ A
I_ A
O _ A
D 6
O _ B
I_ B
K _ B
S _ B
P C 0 /A N 8 ~ P C 7 /A N 1 5
1 6 -C h a n n e l
A /D C o n v e rte r
P A 3 , P A 5
P B C
O S C 2
P O R T C
P C
S h ifte r
T im in g
G e n e ra to r
Y S
P A 4
W D T
In s tr u c tio n
R e g is te r
fS
P A 4 /T M R
X
P A C
P O R T A
P A
P B 0 /A N 0 ~ P B 7 /A N 7
P A 0
P A 3
P A 4
P A 5
P A 6
P A 7
~ P
/P
/T
/IN
/IN
A 2
F D
M R
T 0
T 1
Pin Assignment
P F 2 /S C S
P F 1 /S C K
P F 0 /S D
P D 7 /S D O
P B 7 /A
P B 6 /A
P B 5 /A
P B 4 /A
P C 7 /A N
P C 6 /A N
P A 3 /P
1
2 8
P F 1 /S C K _ B
2
2 7
P F 2 /S C S _ B
P A 3 /P F D
3
2 6
P A 4 /T M R
P A 2
4
2 5
P A 5 /IN T 0
P A 1
5
2 4
P A 6 /IN T 1
P A 0
6
2 3
P A 7
P B 3
7
2 2
O S C 2
P B 2
8
2 1
O S C 1
P B 1
A V D D
V D D
9
2 0
& V R E F
1 0
1 9
R E S
V S S
1 1
1 8
P D 1
P B 0
1 2
1 7
P D 2
P C 2
1 3
1 6
P D 3
P C 1
1 4
1 5
P D 4
_ B
_ B
I_ B
_ B
N 7
N 6
N 5
N 4
1 5
1 4
F D
P F 0 /S D I_ B
P D 7 /S D O _ B
P B
P B
P B
P B
P C 5
P A
P A
P A
3 /A N
2 /A N
1 /A N
V R E
A V D
A V S
0 /A N
/A N 1
4 4 4 3 4 2 4 1
1
2
4 0 3 9 3 8 3 7 3 6 3 5 3 4
3 3
2
3 2
3
3 1
3
4
3 0
2
5
1
6
1
0
H T 8 2 J 3 0 R /H T 8 2 J 3 0 A
4 4 Q F P -A
7
F
D
S
2 6
2 5
2 4
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
2 3
4 /T M R
5 /IN T 0
6 /IN T 1
7
5
6
O S C 2
O S C 1
V D D
V S S
R E
P D
P D
P D
P D
P D
P C
P C
P C
P C
P C
H T 8 2 J 3 0 R /H T 8 2 J 3 0 A
2 7
9
1 1
3
2 8
8
1 0
0
2 9
N C
P A
P A
P A
P A
P D
P D
S
0 /P
1 /S
2 /S
3 /S
4 /S
0 /A
1 /A
2 /A
3 /A
4 /A
2 8 S K D IP -A /S O P -A
W M 0
C S _ A
C K _ A
D I_ A
D O _ A
N 8
N 9
N 1 0
N 1 1
N 1 2
Rev. 1.00
2
December 20, 2006
HT82J30R/HT82J30A
Pin Description
Pin Name
PA0~PA2
PA3/PFD
PA4/TMR
PA5/INT0
PA6/INT1
PA7
PB0/AN0~
PB7/AN7
I/O
Options
Description
I/O
Bidirectional 8-bit input/output port. Each individual pin on this port can be configPull-high* ured as a wake-up input by a configuration option. Software instructions deterWake-up mine if the pin is a CMOS output or Schmitt trigger input. Configuration options
PA3 or PFD determine which pin on this port have pull-high resistors. The PFD, TMR and external interrupt input are pin-shared with PA3, PA4, and PA5 , PA6, respectively.
I/O
Pull-high*
Bidirectional 8-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt trigger input. Configuration options determine which pin
on this port have pull-high resistors. PB is pin-shared with the A/D input pins. The
A/D inputs are selected via software instructions Once selected as an A/D input,
the I/O function and pull-high resistor functions are disable automatically.
PB2, PB3 has CMOS or NMOS output option.
Pull-high*
Bidirectional 8-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt trigger input. Configuration options determine which pin
on this port have pull-high resistors. PB is pin-shared with the A/D input pins. The
A/D inputs are selected via software instructions Once selected as an A/D input,
the I/O function and pull-high resistor functions are disabled automatically.
PC0/AN8~
PC7/AN15
I/O
PD0/PWM0
PD1/SCS_A
PD2/SCK_A
PD3/SDI_A
PD4/SDO_A
PD5~PD6
PD7/SDO_B
Bi-directional 8-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt trigger input. Configuration options determine which pin
on this port have pull-high resistors. PD0 is pin-shared with the PWM output sePull-high*
I/O
lected via configuration option.
PD0 or PWM
PD1~PD4 are pin-shared with SPI interface A.
PD4, PD7 have CMOS or NMOS output options.
PD7 is pin-shared with the SPI interface B.
PF0/SDI_B
PF1/SCK_B
PF2/SCS_B
I/O
Pull-high*
Bidirectional 3-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt trigger input. Configuration options determine which pin
on this port have pull-high resistors. PF0~PF2 is pin-shared with the SPI interface
B.
OSC1
OSC2
I
O
Crystal
or RC
OSC1 and OSC2 are connected to an external RC network or external crystal, determined by configuration option, for the internal system clock. If the RC system
clock is selected, pin OSC2 can be used to measure the system clock at 1/4 system frequency.
RES
I
¾
Schmitt trigger reset input. Active low
VDD
¾
¾
Positive power supply
VSS
¾
¾
Negative power supply, ground
AVDD
¾
¾
Analog positive power supply
AVSS
¾
¾
Analog negative power supply
VREF
¾
¾
8-bit A/D reference voltage input pin
Note: * The pull-high resistors of each I/O port are controlled by options.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...............................0°C to 70°C
IOL Total ..............................................................150mA
IOH Total............................................................-100mA
Total Power Dissipation .....................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.00
3
December 20, 2006
HT82J30R/HT82J30A
D.C. Characteristics
Symbol
VDD
IDD
Parameter
Operating Voltage
Operating Current
(Crystal OSC, RC OSC)
Ta=25°C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
¾
fSYS=4MHz
2.2
¾
5.5
V
¾
fSYS=12MHz at 56kW
RC mode
2.7
¾
3.7
V
3V
No load, fSYS=12MHz
ADC disable
¾
1
2
mA
¾
4
6
mA
¾
¾
5
mA
mA
5V
Standby Current
(WDT Enabled)
3V
5V
¾
¾
10
Standby Current
(WDT Disabled)
3V
¾
¾
1
mA
¾
¾
2
mA
VIL1
Input Low Voltage for I/O Ports,
TMR and INT
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports,
TMR and INT
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VLVR
Low Voltage Reset
¾
Configuration option: 3V
¾
¾
2.1
V
IOL
4
8
¾
mA
I/O Port Sink Current
10
20
¾
mA
-2
-4
¾
mA
-5
-10
¾
mA
ISTB1
ISTB2
No load, system HALT
No load, system HALT
5V
3V
VOL=0.1VDD
5V
IOH
3V
I/O Port Source Current
VOH=0.9VDD
5V
RPH
VAD
A/D Input Voltage
EAD
A/D Conversion Error
IADC
3V
¾
20
60
100
kW
5V
¾
10
30
50
kW
¾
¾
0
¾
VDD
V
3V
¾
¾
±0.5
±1
LSB
5V
¾
¾
±0.5
±1
LSB
¾
0.5
1
mA
¾
1.5
3
mA
Pull-high Resistance
3V
Only ADC Enable, Others Disable
No load
5V
Rev. 1.00
4
December 20, 2006
HT82J30R/HT82J30A
A.C. Characteristics
Symbol
fSYS1
fSYS2
fTIMER
Parameter
System Clock
(Crystal OSC)
System Clock
(RC OSC)
Timer I/P Frequency
(TMR)
tWDTOSC Watchdog Oscillator Period
Ta=25°C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
¾
2.2V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
¾
2.2V~2.6V
1000
¾
4000
kHz
¾
2.7V~5.5V
1000
12000
14000
kHz
¾
2.2V~5.5V
0
¾
4000
kHz
¾
3.3V~5.5V
0
¾
8000
kHz
3V
¾
45
90
180
ms
5V
¾
32
65
130
ms
tWDT1
Watchdog Time-out Period
(WDT OSC)
¾
¾
215
¾
216
tWDTOSC
tWDT2
Watchdog Time-out Period
(System Clock)
¾
¾
217
¾
218
*tSYS
tRES
External Reset Low Pulse
Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
¾
1024
¾
tSYS
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tAD
A/D Clock Period
¾
¾
1
¾
¾
ms
tADC
A/D Conversion Time
¾
¾
¾
76
¾
tAD
tADCS
A/D Sample Time
¾
¾
¾
32
¾
tAD
tCS_SK
SPI SCS to SCK Time
¾
¾
50
¾
¾
ns
tSPICK
SPI Clock Time
¾
¾
400
¾
¾
ns
Wake-up from HALT
Note: *tSYS= 1/fSYS1 or 1/fSYS2
Rev. 1.00
5
December 20, 2006
HT82J30R/HT82J30A
Functional Description
Execution Flow
incremented by one. The program counter then points to
the memory word containing the next instruction code.
When executing a jump instruction, a conditional skip
execution, loading the PCL register, a subroutine call,
an initial reset, an internal interrupt, an external interrupt
or a return from a subroutine, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute within one cycle. If an instruction changes the program counter, two cycles are
required to complete the instruction.
The conditional skip is activated by instructions. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle replaces it to get the proper instruction. Otherwise
the program proceeds with the next instruction.
Program Counter - PC
The lower byte of the program counter is a readable and
writeable register. Moving data into the PCL performs a
short jump. The destination will be within 256 locations.
The program counter controls the sequence in which the
instructions stored in the program memory are executed
and its contents specify a full range of program memory.
When a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
O S C 2 ( R C o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
INT0 External Interrupt
0
0
0
0
0
0
0
0
0
1
0
0
INT1 External Interrupt
0
0
0
0
0
0
0
1
1
0
0
0
Timer/Event Counter Overflow
0
0
0
0
0
0
0
0
1
0
0
0
Reserved
0
0
0
0
0
0
0
0
1
1
0
0
SPI_A Interrupt
0
0
0
0
0
0
0
1
0
0
0
0
SPI_B Interrupt
0
0
0
0
0
0
0
1
0
1
0
0
Skip
Program Counter+2
Loading PCL
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *11~*0: Program counter bits
S11~S0: Stack register bits
#11~#0: Instruction code bits
Rev. 1.00
@7~@0: PCL bits
6
December 20, 2006
HT82J30R/HT82J30A
· Location 00CH
Program Memory - ROM
This location is reserved for the A/D converter interrupt service program. If the interrupt is activated,
when the A/D conversion is completed, if the interrupt
is enabled and the stack is not full, the program begins
execution at this location.
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
4K´15 bits, addressed by the program counter and table
pointer.
· Location 010H
Certain locations in the program memory are reserved
for special usage:
Location 010H is reserved for when 8 bits of data have
been received or transmitted successfully from serial
interface A. When the related interrupts are enabled,
and the stack is not full, the program begins execution
at location 010H.
· Location 000H
This area is reserved for program initialization. After
chip reset, the program always begins execution at location 000H.
· Location 014H
· Location 004H
Location 014H is reserved for when 8 bits of data have
been received or transmitted successfully from serial
interface B. When the related interrupts are enabled,
and the stack is not full, the program begins execution
at location 014H.
This area is reserved for the external interrupt service
program. If the INT0 input pin is activated, the interrupt is enabled and the stack is not full, the program
begins execution at location 004H.
· Location 008H
· Location 018H
This area is reserved for the timer/event counter interrupt service program. If a timer interrupt results from a
timer/event counter overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
0 0 0 H
0 0 4 H
0 0 8 H
0 0 C H
· Table location
D e v ic e In itia liz a tio n P r o g r a m
Any location in the Program Memory space can be
used as a look-up table. The instructions ²TABRDC
[m]² (the current page, one page=256 words) and
²TABRDL [m]² (the last page) transfers the contents of
the lower-order byte to the specified data memory, and
the higher-order byte to the TBLH register. Only the
destination of the lower-order byte in the table is
well-defined, the other bits of the table word are transferred to the lower portion of TBLH. Any unused bits
are read as ²0². The Table Higher-order byte register,
TBLH, is read only. The table pointer, TBLP, is a
read/write register, which indicates the table location.
Before accessing the table, the location must be placed
in TBLP. The TBLH register is read only and cannot be
restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction,
the contents of TBLH in the main routine are likely to be
changed by the table read instruction used in the ISR
and errors can occur. In other words, using the table
read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table
IN T 0 E x te r n a l In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e
A /D
0 1 0 H
C o n v e r te r In te r r r u p t S u b r o u tin e
S P I_ A In te r r u p t S u b r o u tin e
0 1 4 H
0 1 8 H
This location is reserved for the external interrupt service program. If the INT1 input pin is activated, the interrupt is enabled and the stack is not full, the program
begins execution at this location.
P ro g ra m
M e m o ry
S P I_ B In te r r u p t S u b r o u tin e
IN T 1 E x te r n a l In te r r u p t S u b r o u tin e
n 0 0 H
L o o k - u p T a b le ( 2 5 6 W o r d s )
n F F H
L o o k - u p T a b le ( 2 5 6 W o r d s )
F F F H
1 5 b its
N o te : n ra n g e s fro m 0 to F
Program Memory
Instruction
Table Location
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *11~*0: Table location bits
P11~P8: Current program counter bits
@7~@0: Table pointer bits
Rev. 1.00
7
December 20, 2006
HT82J30R/HT82J30A
read instruction has to be applied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It should not be
enabled until TBLH has been backed up. All table related instructions require two cycles to complete the
operation. These areas may function as normal program memory depending upon the requirements.
In d ir e c t A d d r e s s in g R e g is te r
0 1 H
M P
0 2 H
0 3 H
0 4 H
0 5 H
Stack Register - STACK
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack is organized into 6 levels and is neither part of the
data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction, RET or RETI, the program counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
0 A H
S T A T U S
0 B H
IN T C
0 C H
0 D H
T M R
0 E H
T M R C
0 F H
1 0 H
1 1 H
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first
entry will be lost as only the most recent 6 return addresses are stored.
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
P D
1 9 H
P D C
1 A H
P W M
S p e c ia l P u r p o s e
D a ta M e m o ry
1 B H
1 C H
P F
1 D H
P F C
1 E H
IN T C 1
1 F H
2 0 H
Data Memory - RAM
The data memory is designed with 226´8 bits. The data
memory is divided into 2 functional groups: special function registers and general purpose data memory. Most
of them are read/write, but some are read only.
2 1 H
A D R
2 2 H
A D C R
2 3 H
A C S R
2 4 H
S B C R _ A
2 5 H
S B D R _ A
2 6 H
S B C R _ B
2 7 H
2 8 H
Reading any unused locations will return the result
²00H². The general purpose data memory, addressed
from 28H to FFH, is used for data and control information under instruction commands.
F F H
S B D R _ B
G e n e ra l P u rp o s e
D a ta M e m o ry
(2 1 6 B y te s )
: U n u s e d
R e a d a s "0 0 "
RAM Mapping
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
the memory pointer registers MP.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
Indirect Addressing Register
Location 00H is an indirect addressing register that is
not physically implemented. Any read/write operation of
[00H] accesses data memory pointed to by MP. Reading
location 00H itself indirectly will return the result 00H.
Writing indirectly results in no operation.
Rev. 1.00
0 0 H
Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic operations.
The ALU provides the following functions:
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
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December 20, 2006
HT82J30R/HT82J30A
· Logic operations (AND, OR, XOR, CPL)
converter end-of-conversion interrupt and two SPI interrupts. The interrupt control registers INTC and INTC1
both contains the interrupt control bits to set the enable/disable and the interrupt request flags.
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
Once an interrupt subroutine is serviced, all the other interrupts will be blocked by clearing the EMI bit. This
scheme may prevent any further interrupt nesting. Other
interrupt requests may happen during this interval but
only the interrupt request flags are recorded. If a certain
interrupt requires servicing within the service routine,
the programmer may set the EMI bit and the corresponding bit of INTC or INTC1 to allow interrupt nesting.
If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decreased. If immediate service is desired,
the stack has to be prevented from becoming full.
The ALU not only saves the results of a data operation but
also changes the status register.
Status Register - STATUS
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO). It
also records the status information and controls the operation sequence.
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PDF flags. In addition, operations related to the status register may
give different results from those intended. The TO
flag can be affected only by system power-up, a WDT
time-out or executing the ²CLR WDT² or ²HALT² instruction. The PDF flag can be affected only by executing the ²HALT² or ²CLR WDT² instruction or
during a system power-up.
All interrupts have a wake-up capability. As an interrupt
is serviced, a control transfer occurs by pushing the program counter onto the stack and then branching to subroutines at a specified location in the program memory.
Only the program counter is pushed onto the stack. If
the contents of the register or status register are altered
by the interrupt service program, which corrupts the desired control sequence, the programmer should save
these contents first.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
External interrupts are triggered by a high to low transition on pins INT0 or INT1 which will in turn set the related interrupt request flag, which is bit 4 of INTC or bit 6
of INTC1. When the respective interrupt is enabled, the
stack is not full and the external interrupt is active, a subroutine call to location 004H or 018H will occur. The external interrupt request flag and EMI bits will cleared to
disable other interrupts.
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
The internal timer/event counter interrupt is initialized by
setting the timer/event counter interrupt request flag (bit
5 of INTC), caused by a timer overflow. When the interrupt is enabled, the stack is not full and the timer/event
Interrupt
The microcontroller provides two external interrupts, an
internal timer/event counter overflow interrupt, an A/D
Bit No.
Label
Function
0
C
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
1
AC
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
3
OV
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing the ²HALT² instruction.
5
TO
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
6~7
¾
Unused bit, read as ²0²
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
Status (0AH) Register
Rev. 1.00
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December 20, 2006
HT82J30R/HT82J30A
Bit No.
Label
0
EMI
1
EEI_A
2
ETI
Function
Controls the master (global) interrupt (1= enabled; 0= disabled)
Controls the external interrupt (1= enabled; 0= disabled)
Controls the Timer/Event Counter interrupt (1= enabled; 0= disabled)
3
EADI
Controls the A/D converter interrupt (1= enabled; 0= disabled)
4
EIF_A
External interrupt request flag (1= active; 0= inactive)
5
TF
6
ADF
7
¾
Internal Timer/Event Counter request flag (1= active; 0= inactive)
End of A/D conversion interrupt request flag (1= active; 0= inactive)
Unused bit, read as ²0²
INTC (0BH) Register
Bit No.
Label
Function
0
ESII_A
Controls the serial interface interrupt (1= enabled; 0= disabled)
1
ESII_B
Controls the serial interface interrupt (1= enabled; 0= disabled)
2
EEI_B
Controls the INT1 external interrupt (1= enabled; 0= disabled)
3, 7
¾
4
SIF_A
Serial interface interrupt request flag (1= active; 0= inactive)
5
SIF_B
Serial interface interrupt request flag (1= active; 0= inactive)
6
EIF_B
INT1 External interrupt request flag (1= active; 0= inactive)
Unused bits, read as ²0²
INTC1 (1EH) Register
counter interrupt request flag is set, a subroutine call to
location 00CH will occur. The related interrupt request
flag will be reset and the EMI bit cleared to disable further interrupts.
interrupt control bits are set to ²1² (if the stack is not full).
To return from the interrupt subroutine, a ²RET² or
²RETI² instruction may be executed. RETI will set the
EMI bit to enable further interrupts, but RET will not.
The A/D converter end-of-conversion interrupt is initialized by setting the A/D end-of-conversion interrupt request flag (bit 6 of INTC), caused by an end of A/D
conversion. When the interrupt is enabled, the stack is
not full and the end of A/D conversion interrupt request
flag is set, a subroutine call to location 0CH will occur.
The related interrupt request flag will be reset and the
EMI bit cleared to disable further interrupts.
Interrupts, occurring in the interval between rising edge
of two consecutive T2 pulses, will be serviced on the
later of the two T2 pulses, if the corresponding interrupts
are enabled. In the case of simultaneous requests the
priorities in the follow table apply.
These can be masked by clearing the EMI bit.
Interrupt Source
There are two serial interface interrupts, which will be
generated when the interface receives or transmits
8-bits of data. These interrupts are indicated by the interrupt flags, SIF_A; bit 4 of INTC1, and SIF_B; bit 5 of
INTC1. The serial interface interrupts are enabled by
setting the serial interface interrupt control bits, ESII_A;
bit 0 of INTC1 and ESII_B; bit 1 of INTC1. After the res p e c t iv e i n t e r f ac e i s e n a b l ed by s et t i n g t h e
corresponding SBEN bit, which is bit 4 of either
SBCR_A or SBCR_B, if the stack is not full and the
corresponding SIF_A or SIF_B bit is set, a subroutine
call to location 10H or 14H occurs.
Vector
INT0 External Interrupt
1
04H
Timer/Event Counter Overflow
2
08H
End of A/D Conversion Interrupt
3
0CH
SPI_A Interrupt
4
10H
SPI_B Interrupt
5
14H
INT1 External Interrupt
6
18H
The timer/event counter interrupt request flag (TF), external interrupt request flag (EIF), A/D converter request flag
(ADF), enable timer/event counter bit (ETI), enable external interrupt bit (EEI), enable A/D converter interrupt bit
(EADI) and enable master interrupt bit (EMI) constitute
an interrupt control register (INTC) which is located at
0BH in the data memory. EMI, EEI, ETI, EADI are used to
control the enabling/disabling of interrupts. These bits
During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related
Rev. 1.00
Priority
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December 20, 2006
HT82J30R/HT82J30A
and no external components are required. Even if the system enters the power down mode, the system clock is
stopped, but the WDT oscillator still works within a period
of 65ms at 5V. The WDT oscillator can be disabled by options to conserve power.
prevent the requested interrupt from being serviced.
Once the interrupt request flags (TF, EIF, ADF) are set,
they will remain in the INTC register until the interrupts
are serviced or cleared by a software instruction.
It is recommended that a program does not use the CALL
subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack
is left and enabling the interrupt is not well controlled, the
original control sequence will be damaged if a ²CALL² instruction is executed in the interrupt subroutine.
Watchdog Timer - WDT
The clock source of WDT is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), chosen via a configuration option. This timer is designed to prevent software
malfunctions or the program jumping to unknown locations. The Watchdog Timer can be disabled by a configuration option. If the Watchdog Timer is disabled, all the
executions related to the WDT result in no operation.
Oscillator configuration
There are 2 oscillator circuits in the microcontroller.
V
R
C 1
D D
If the internal oscillator, which is an RC oscillator with a
nominal period of 65ms at 5V, is selected, it is first divided by 32768~65536 to get a time-out period of approximately 2.1s~4.3s. This time-out period may vary
with temperature, VDD and process variations. If the
WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operate in the same
manner except that in the HALT state the WDT may stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by external logic.
O S C
O S C 1
O S C 1
C 2
R 1
O S C 2
C r y s ta l O s c illa to r
fS Y S /4
N M O S o p e n d r a in
O S C 2
R C
O s c illa to r
System Oscillator
Both of them are designed for system clocks, namely
the external RC oscillator, the external Crystal oscillator
and the internal RC oscillator, the choice of which is determined by configuration options. The Power Down
mode stops the system oscillator to conserve power.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT instruction will stop the system
clock.
If an RC oscillator is used, an external resistor between
OSC1 and VDD is required and the resistance must
range from 47kW to 750kW. The system clock, divided
by 4, is available on OSC2, which can be used to synchronize external logic. The RC oscillator provides the
most cost effective solution. However, the oscillation
frequency may vary with VDD, temperature and process variations. It is, therefore, not suitable for timing
sensitive operations where an accurate oscillator frequency is desired.
The WDT overflow under normal operation will initialize
a ²chip reset² and set the status bit ²TO². But in the
Power-down mode, the overflow will initialize a ²warm
reset², and only the program counter and the SP are reset to zero. To clear the contents of the WDT, three
methods are adopted; an external reset (a low level on
the RES pin), a software instruction or a HALT instruction. The software instructions include ²CLR WDT² and
the other set - ²CLR WDT1² and ²CLR WDT2². Of these
two types of instruction, only one can be active depending on the configuration option - ²CLR WDT times selection option². If the ²CLR WDT² is selected (i.e. CLR
WDT times equal one), any execution of the ²CLR
WDT² instruction will clear the WDT. In the case that
²CLR WDT1² and ²CLR WDT2² are chosen (i.e. CLR
WDT times equal two), these two instructions must be
executed to clear the WDT; otherwise, the WDT may reset the chip as a result of a time-out.
If the Crystal oscillator is used, a crystal across OSC1 and
OSC2 is needed to provide the feedback and phase shift
required for the oscillator. No other external components
are required. Instead of a crystal, a resonator can also be
connected between OSC1 and OSC2 to obtain a frequency reference, but two external capacitors connected
between OSC1 and OSC2 and ground are required.
The WDT oscillator is a free running on-chip RC oscillator,
S y s te m
C lo c k /4
O p tio n
S e le c t
fS
8 - b it C o u n te r
7 - b it C o u n te r
W D T
O S C
T
T
W D T T im e - o u t
fS /2 15~ fS /2 16
C L R
W D T
Watchdog Timer
Rev. 1.00
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HT82J30R/HT82J30A
Power Down Operation - HALT
To minimize power consumption, all the I/O pins should
be carefully managed before entering the Power-down
mode.
The HALT mode is initialized by the ²HALT² instruction
and results in the following...
· The system oscillator will be turned off but the WDT
Reset
oscillator remains running (if the WDT oscillator is selected).
There are three ways in which a reset can occur:
· RES reset during normal operation
· The contents of the on chip RAM and registers remain
· RES reset during HALT
unchanged.
· WDT time-out reset during normal operation
· The WDT and WDT prescaler will be cleared and re-
sume counting again (if the WDT clock comes from
the WDT oscillator).
The WDT time-out during Power-down is different from
other chip reset conditions, since it can perform a ²warm
reset² that resets only the Program Counter and SP,
leaving the other circuits in their original state. Some
registers remain unchanged during other reset conditions. Most registers are reset to their ²initial condition²
when the reset conditions are met. By examining the
PDF and TO flags, the program can distinguish between different ²chip resets².
· All of the I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
The system can leave the Power-down mode by means
of an external reset, an interrupt, an external falling
edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow
performs a ²warm reset². After the TO and PDF flags
are examined, the reason for chip reset can be determined. The PDF flag is cleared by a system power-up or
executing the ²CLR WDT² instruction and is set when
executing the ²HALT² instruction. The TO flag is set if
the WDT time-out occurs, and causes a wake-up that
only resets the Program Counter and SP; the others remain in their original status.
The port A wake-up and interrupt methods of wake-up
can be considered as a continuation of normal execution. Each bit in port A can be independently selected to
wake-up the device using configuration options. Awakening from an I/O port stimulus, the program will resume
execution of the next instruction. If it awakens from an
interrupt, two sequences may occur. If the related interrupt is disabled or the interrupt is enabled but the stack
is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not
full, the regular interrupt response takes place. If an interrupt request flag is set to ²1² before entering the
Power-down mode, the wake-up function of the related
interrupt will be disabled. Once a wake-up event occurs,
it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period will be inserted after a wake-up. If the wake-up results from an
interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles.
If the wake-up results in the next instruction execution,
this will be executed immediately after the dummy period has finished.
Rev. 1.00
TO
PDF
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: ²u² stands for ²unchanged²
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the
system awakes from the Power-down mode.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from Power-down
will enable the SST delay.
An extra option load time delay is added during a system
reset (power-up, WDT time-out at normal mode or RES
reset).
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HT82J30R/HT82J30A
V D D
The functional unit chip reset status is shown below.
R E S
Program Counter
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After a master reset,
WDT begins counting
Timer/Event Counter
Off
Input/Output Ports
Input mode
Stack Pointer
C h ip
S T
R e s e t
Reset Timing Chart
H A L T
W a rm
R e s e t
W D T
Points to the top of the stack
V
tS
S S T T im e - o u t
R E S
D D
C o ld
R e s e t
0 .0 1 m F *
1 0 0 k W
S S T
1 0 - b it R ip p le
C o u n te r
O S C 1
R E S
1 0 k W
S y s te m
0 .1 m F *
R e s e t
Reset Configuration
Reset Circuit
Note:
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to
avoid noise interference.
The register states is summarized in the table.
Register
Reset
(Power-on)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
MP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
000H
000H
000H
000H
000H
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
INTC1
-000 -000
-000 -000
-000 -000
-000 -000
-uuu -uuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PD
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PDC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
---- -111
---- -111
---- -111
---- -111
--- -uuu
Program
Counter
PF
Rev. 1.00
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HT82J30R/HT82J30A
Register
PFC
Reset
(Power-on)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
---- -111
---- -111
---- -111
---- -111
--- -uuu
INTC1
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
PWM
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADR
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
0100 0000
uuuu uuuu
ACSR
1--- --00
1--- --00
1--- --00
1--- --00
u--- --uu
SBCR_A
0110 0000
0110 0000
0110 0000
0110 0000
uuuu uuuu
SBDR_A
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
SBCR_B
0110 0000
0110 0000
0110 0000
0110 0000
uuuu uuuu
SBDR_B
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
Note:
²*² stands for ²warm reset²
²u² stands for ²unchanged²
²x² stands for ²unknown²
In the pulse width measurement mode with the TON
and TE bits equal to one, once the TMR pin has received a transient from low to high (or high to low if the
TE bit is ²0²) it will start counting until the TMR pin returns to its original level and resets the TON bit. The
measured result will remain in the timer/event counter
even if the activated transient occurs again. In other
words, only a one cycle measurement can be implemented. Until the TON bit is again set, the cycle measurement will not function even if it receives further
transient pulses. Note that, in this operating mode, the
timer/event counter starts counting not according to the
logic level but according to the transient edges. In the
case of a counter overflow, the counter is reloaded from
the timer/event counter preload register and issues an
interrupt request just like the other two modes. To enable the counting operation, the timer ON bit (TON; bit 4
of TMRC) should be set to 1. In the pulse width measurement mode, the TON bit will be cleared automatically after the measurement cycle is completed. But in
the other two modes the TON bit can only be reset by instructions. The overflow of the timer/event counter is
one of the wake-up sources. No matter what the operation mode is, writing a 0 to ETI can disable the interrupt
service.
Timer/Event Counter
A timer/event counter (TMR) is implemented in the
microcontroller. The timer/event counter contains an
8-bit programmable count-up counter whose clock may
come from an external source or the system clock.
Using an external clock input allows the user to count
external events, measure time internals or pulse widths,
or generate an accurate time base. While using the internal clock allows the user to generate an accurate time
base.
The timer/event counter can generate PFD signal by using an external or internal clock. The PFD frequency is
determined by the equation fINT/[2´(256-N)].
There are 2 registers related to the timer/event counter;
TMR and TMRC. Two physical registers are mapped to
the TMR location; writing to TMR places the start value
into the timer/event counter preload register. Reading
TMR retrieves the contents of the timer/event counter.
The TMRC register is a timer/event counter control register, which defines some options.
The TM0, TM1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source comes from the external
TMR pin. The timer mode functions as a normal timer
with the clock source coming from the fINT clock. The
pulse width measurement mode can be used to measure a
high or low level duration of the external TMR pin. The
counting is based on fINT.
In the case of a timer/event counter OFF condition, writing data to the timer/event counter preload register will
also reload that data to the timer/event counter. But if the
timer/event counter is turned on, data written to it will
only be kept in the timer/event counter preload register.
The timer/event counter will still operate until an overflow occurs. When the timer/event counter is read, the
clock will be blocked to avoid errors. As clock blocking
may results in a counting error, this must be taken into
consideration by the programmer.
In the event count or timer mode, once the timer/event
counter starts counting, it will count from the current contents in the timer/event counter to FFH. Once an overflow
occurs, the counter is reloaded from the timer/event
counter preload register and generates an interrupt request flag (TF; bit 5 of INTC) at the same time.
Rev. 1.00
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HT82J30R/HT82J30A
The bit0~bit2 of the TMRC can be used to define the
pre-scaling stages of the internal clock sources of
timer/event counter. The overflow signal of the
timer/event counter can be used to generate the PFD
signal.
operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction
²MOV A,[m]² (m=12H, 14H, 16H, 18H or 22H). For output
operation, all the data is latched and remains unchanged
until the output latch is rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC, PFC) to control the input/output configuration. With this control register, a CMOS output or
Schmitt trigger input with or without pull-high resistor
structures can be reconfigured dynamically (i.e.
on-the-fly) under software control. To function as an input, the corresponding latch of the control register must
Input/Output Ports
There are 35 bidirectional input/output lines in the
microcontroller, labeled as PA, PB, PC, PD and PF,
which are mapped to the data memory of [12H], [14H],
[16H], [18H] and [22H] respectively. All of these I/O ports
can be used for input and output operations. For input
Bit No.
Label
Function
Defines the prescaler stages, PSC2, PSC1, PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
PSC0
PSC1
PSC2
0
1
2
3
TE
4
TON
5
¾
6
7
Defines the TMR active edge of the timer/event counter:
In Event Counter Mode (TM1,TM0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (TM1,TM0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
Enable or disable the timer counting
(0=disable; 1=enable)
Unused bits, read as ²0²
Defines the operating mode (TM1, TM0)=
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TM0
TM1
TMRC (0EH) Register
P W M
(6 + 2 ) C o m p a re
fS
Y S
T o P D 0 C ir c u it
8 - s ta g e P r e s c a le r
f IN
8 -1 M U X
P S C 2 ~ P S C 0
D a ta B u s
T
T M 1
T M 0
T M R
8 - B it T im e r /E v e n t
C o u n te r P r e lo a d
R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
8 - B it T im e r /E v e n t
C o u n te r
O v e r flo w
to In te rru p t
1 /2
P F D
Timer/Event Counter
Rev. 1.00
15
December 20, 2006
HT82J30R/HT82J30A
write ²1². The input source also depends on the control
register. If the control register bit is ²1², the input will
read the pad state. If the control register bit is ²0², the
contents of the latches will move to the internal bus. The
latter is possible in the ²read-modify-write² instruction.
ated by the timer/event counter overflow signal. If setup
as an input then the pin will retain its input function.
Once the PFD configuration option is selected, the PFD
output signal is controlled by the PA3 data register. Writing a ²1² to the PA3 data register will enable the PFD
output function and writing ²0² will force pin PA3 to remain at ²0². The I/O functions of PA3 are shown below.
For output function, all I/Os except PB2, PB3, PD2, PD7
are CMOS types. There are options to define PB2, PB3,
PD2, PD7 as either CMOS or NMOS types. These control registers are mapped to locations 13H, 15H,
17H,19H and 23H.
I/O
Mode
Logical
Input
PA3
After a device reset, these input/output lines remain at
high levels or a floating state, depending upon the
pull-high configuration options. Each bit of these input/output latches can be set or cleared using the ²SET
[m].i² and ²CLR [m].i² instructions.
Note:
I/P
O/P
(Normal) (Normal)
Each I/O line has a pull-high option. Once a pull-high option is selected, the I/O line has a pull-high resistor
connected, otherwise, there are none. Take note that a
non-pull-high I/O line operating as an input will be in a
floating state.
PD0
I/P
O/P
(Normal) (Normal)
Logical
Input
Q
Q
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
S
Q
M
P A 3
(P D 0 o r P W M )
P F D
M
R e a d D a ta R e g is te r
S y s te m
W a k e -u p
( P A o n ly )
Logical
Input
PWM
D D
P A
P A
P A
P A
P A
P A
P B
P C
P D
C h ip R e s e t
R e a d C o n tr o l R e g is te r
O/P
(PWM)
It is recommended that unused or not bonded out I/O
V
S
Logical
Output
I/P
(PWM)
P u ll- H ig h
O p tio n
C o n tr o l B it
C K
PFD
(Timer on)
The PFD frequency is the timer/event counter
overflow frequency divided by 2.
I/O
Mode
Pin PA3 is pin-shared with the PFD signal. If the PFD
configuration option is selected, the output signal on
PA3, if setup as an output, will be the PFD signal gener-
D
Logical
Input
PB and PC can also be used as A/D converter inputs.
The A/D function will be described later. There are two
SPI interfaces which are shared with pins PD1~PD4,
PD7 and PF0~PF2. The SPI function will be described
later. There is a PWM function shared with pin PD0. If
the PWM function is enabled, the PWM signal will appear on pin PD0 (if PD0 is setup as an output). Writing a
²1² to the PD0 data register will enable the PWM output
function and writing a ²0² will force the PD0 to remain at
²0². The I/O functions of PD0 are shown in the table.
Each line of port A has the capability of waking-up the
device.
D a ta B u s
O/P
(PFD)
PA6, PA5 and PA4 are pin-shared with the INT0, INT1
and TMR pins respectively.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
W r ite C o n tr o l R e g is te r
Logical
Output
I/P
(PFD)
U
U
7
0 ~ P
3 /P
4 /T
5 /IN
6 /IN
A 2
F D
M R
T 0
T 1
0 /A N 0 ~ P B 7 /A N 7
0 /A N 8 ~ P C 7 /A N 1 5
0 /P W M
X
P F D E N
(P A 3 )
X
W a k e - u p o p tio n
IN T fo r P A 5 O n ly
T M R fo r P A 4 O n ly
Input/Output Ports
Rev. 1.00
16
December 20, 2006
HT82J30R/HT82J30A
lines should be set as output pins using software instructions to minimise power consumption should they
be inadvertently setup as floating inputs.
Group 2 is denoted by AC which has the value of
PWM.1~PWM.0.
In a PWM cycle, the duty cycle of each modulation cycle
is shown in the table.
Pulse Width Modulator - PWM
Parameter
The microcontroller provides a single channel (6+2) bit
Pulse Width Modulator output shared with pin PD0. Its
data register is known as PWM. The frequency source
for the PWM counter comes from fSYS. The PWM register is an eight bit register. If the configuration option selects pin PD0 to be a PWM output, and if the pin is setup
as an output by setting bit PDC.0 to ²0², then writing 1 to
the PD0 data register will enable the PWM output function. Writing a ²0² will force the PD0 to stay at ²0².
Y S
Duty Cycle
i<AC
DC + 1
64
i³AC
DC
64
Modulation cycle i
(i=0~3)
The modulation frequency, cycle frequency and cycle
duty of the PWM output signal are summarized in the
following table.
A PWM cycle is divided into four modulation cycles
(modulation cycle 0~modulation cycle 3). Each modulation cycle has 64 PWM input clock periods. In a (6+2) bit
PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is
denoted by DC which has the value of PWM.7~PWM.2.
fS
AC (0~3)
PWM
Modulation
Frequency
PWM Cycle
Frequency
PWM Cycle
Duty
fSYS/64
fSYS/256
[PWM]/256
/2
[P W M ] = 1 0 0
P W M
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 6 /6 4
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
2 6 /6 4
P W M
m o d u la tio n p e r io d : 6 4 /fS
M o d u la tio n c y c le 0
Y S
M o d u la tio n c y c le 1
P W M
M o d u la tio n c y c le 2
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 3
M o d u la tio n c y c le 0
Y S
PWM
Rev. 1.00
17
December 20, 2006
HT82J30R/HT82J30A
A/D Converter
only and should not be used. Bits 1 and bit 0 are used to
select the A/D converter clock source.
A 16 channel 8-bit resolution A/D converter is integrated
within the microcontroller. The A/D reference voltage is
VDD. The A/D converter contains several special registers, which are ADR, ADCR and ACSR. The ADR register is the A/D result register and is read-only. After an
A/D conversion has completed, the ADR register is read
to obtain the conversion result data. The EOCB flag will
also be automatically cleared to indicate the end of conversion. The ADCR register is the A/D converter control
register, which selects the analog channel, contains the
start A/D conversion control bit and the end of A/D conversion flag. To initiate an A/D conversion, the analog
channel is first selected and then the START bit is given
a falling edge. When the conversion is complete, the
EOCB bit will be cleared and an A/D converter interrupt
is generated. The ACSR register selects the A/D clock
source as well as selecting which pins are to be used as
A/D inputs. Bits 0~3 of ADCR are used to select an analog input channel. There are a total of 16 channels to select. Bits 3~6 of ADSR are used to select which pins on
Port B and Port C are setup as normal I/Os or A/D inputs. The EOCB bit in the ADCR registers, is end of A/D
conversion flag. This bit can be monitored to check
when the A/D conversion has completed. The START bit
in the ADCR register is used to initiate A/D conversion
process. Providing the START bit with a rising edge will
reset and start the A/D conversion. When checking for
the end of an A/D conversion, the START bit should remain at ²0² and the EOCB bit monitored until it is cleared
to ²0² which indicates the end of conversion.
When the A/D conversion has completed, the A/D interrupt request flag is set. The EOCB bit is set to ²1² automatically when the START bit is set to ²1².
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
D7
D6
D5
D4
D3
D2
D1
D0
ADR (21H) Register
ACS3
ACS2
ACS1
ACS0
Analog Channel
0
0
0
0
AN0
0
0
0
1
AN1
0
0
1
0
AN2
0
0
1
1
AN3
0
1
0
0
AN4
0
1
0
1
AN5
0
1
1
0
AN6
0
1
1
1
AN7
1
0
0
0
AN8
1
0
0
1
AN9
1
0
1
0
AN10
1
0
1
1
AN11
1
1
0
0
AN12
1
1
0
1
AN13
1
1
1
0
AN14
1
1
1
1
AN15
Bit 7 of the ACSR register is used for testing purposes
Bit No.
Label
0~3
ACS0~
ACS3
4~5
¾
Function
Analog channel selection
Reserved bit
6
EOCB
Indicates end of A/D conversion (read only). (0 = end of A/D conversion)
7
START
Starts the A/D conversion. (0®1®0= start; 0®1= Reset A/D converter and set EOCB to ²1²)
ADCR (22H) Register
Bit No.
Label
0
1
ADCS0
ADCS1
2
¾
3~6
PCR0~
PCR3
7
TEST
Function
ADCS1,ADCS0 : Selects the A/D converter clock source
0, 0: fSYS/2
0, 1: fSYS/8
1, 0: Undefined
1, 1: Undefined (fWDT for test only)
Unused bit, read as ²0².
Port B & Port C configuration selection.
If PCR0, PCR1 and PCR2, PCR3 are all zero, the ADC circuit is power off to reduce power
consumption
For internal test only, read as ²1².
ACSR (23H) Register
Rev. 1.00
18
December 20, 2006
HT82J30R/HT82J30A
PCR3 PCR2 PCR1 PCR0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
0
0
0
1
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 AN0
0
0
1
0
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5 PB4 PB3 PB2 AN1 AN0
0
0
1
1
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5 PB4 PB3 AN2 AN1 AN0
0
1
0
0
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5 PB4 AN3 AN2 AN1 AN0
0
1
0
1
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5 AN4 AN3 AN2 AN1 AN0
0
1
1
0
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 AN5 AN4 AN3 AN2 AN1 AN0
0
1
1
1
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
1
0
0
0
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
1
0
0
1
PC7 PC6 PC5 PC4 PC3 PC2 PC1 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
1
0
1
0
PC7 PC6 PC5 PC4 PC3 PC2 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
1
0
1
1
PC7 PC6 PC5 PC4 PC3 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
1
1
0
0
PC7 PC6 PC5 PC4 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
1
1
0
1
PC7 PC6 PC5 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
1
1
1
0
PC7 PC6 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
1
1
1
1
AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
M in im u m
o n e in s tr u c tio n c y c le n e e d e d
S T A R T
E O C B
A /D s a m p lin g tim e
3 2 tA D
P C R 3 ~ P C R 0
0 0 0 B
A /D s a m p lin g tim e
3 2 tA D
1 0 0 B
1 0 0 B
0 0 0 B
1 . P B a n d P C s e tu p a s I/O s
2 . A /D c o n v e r te r is p o w e r e d o ff
to r e d u c e p o w e r c o n s u m p tio n
A C S 3 ~ A C S 0
0 0 0 B
d o n 't c a r e
0 0 0 B
0 1 0 B
P o w e r-o n
R e s e t
R e s e t a n d S ta rt
o f A /D c o n v e rte r
R e s e t a n d S ta rt
o f A /D c o n v e rte r
E n d o f A /D
c o n v e r s io n
1 : D e fin e P B , P C c o n fig u r a tio n
2 : S e le c t a n a lo g c h a n n e l
A /D
N o te :
A /D c lo c k m u s t b e fS
Y S
7 6 tA D
c o n v e r s io n tim e
/2 o r fS
Y S
E n d o f A /D
c o n v e r s io n
7 6 tA D
A /D c o n v e r s io n tim e
/8
A/D Conversion Timing
Rev. 1.00
19
December 20, 2006
HT82J30R/HT82J30A
Example: using EOC Polling Method to detect end of conversion.
clr
INTC
mov a, 0010B
mov
ADCR,a
mov a, 00000001B
mov
ACSR,a
Start_conversion:
clr .7
set ADCR.7
clr ADCR.7
Polling_EOC:
sz ADCR.6
jmp
polling_EOC
mov a, ADR
mov
adr_buffer,a
:
:
jmp
start_conversion
; disable A/D interrupt in interrupt control register
; setup ADCR register to configure Port PB0~PB3 as A/D inputs and select
; AN0 to be connected to the A/D converter
; setup the ACSR register to select fSYS/8 as the A/D clock
; reset A/D
; start A/D
; poll the ADCR register EOC bit to detect end of A/D conversion
; continue polling
; read conversion result from the high byte ADRH register
; save result to user defined register
; start next A/D conversion
Example: using Interrupt method to detect end of conversion.
set
INTC
mov a, 0010B
mov
ADCR,a
mov a, 00000001B
mov
ACSR,a
:
Start_conversion:
clr
ADCR.7
set
ADCR.7
clr
ADCR.7
:
:
; enable A/D interrupt in interrupt control register
; setup ADCR register to configure Port PB0~PB3 as A/D inputs and select
; AN0 to be connected to the A/D converter
; setup the ACSR register to select fSYS/8 as the A/D clock
; reset A/D
; start A/D
; interrupt service routine
EOC_service routine:
mov a_buffer,a
mov a,ADR
mov adr_buffer,a
clr .7
set ADCR.7
clr ADCR.7
mov a,a_buffer
reti
Rev. 1.00
; save ACC to user defined register
; read conversion result from the high byte ADRH register
; save result to user defined register
; reset A/D
; start A/D
; restore ACC from temporary storage
20
December 20, 2006
HT82J30R/HT82J30A
SPI Serial Interface
There are two SPI interfaces, with each interface containing four basic signals and pins. These are SDI (serial data input), SDO (serial data output), SCK (serial clock) and SCS (slave select pin). Note that each of these pin names will be
suffixed with either an A or B to denote which SCI interface is being used, however to minimise repetition, this will not be
S C S _ A , S C S _ B
tC
tS
S _ S K
tC
P IC K
S _ S K
S C K _ A , S C K _ B
S D I_ A , S D I_ B
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
S D O _ A , S D O _ B
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
S B C R _ A , S B C R _ B
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
C K S
M 1
M 0
S B E N
M L S
C S E N
W C O L
T R F
0
1
1
0
0
0
0
0
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
S B D R
U
U
U
U
U
U
U
U
D A T A R E G IS T E R
D E F A U L T
S B D R _ A , S B D R _ B
D E F A U L T
S B C R
: S E R IA L B U S
C O N T R O L R E G IS T E R
: S E R IA L B U S
N o te : "U " m e a n s u n c h a n g e d .
¨
mentioned in the description.
Two corresponding registers, SBCR and SBDR are
unique to the serial interface and provide control, status,
and data storage.
Bit2 (CSEN) ® serial bus selection signal enable/disable (SCS), when CSEN=0, SCSB is floating.
Bit1 (WCOL) ® this bit is set to 1 if data is written to
the SBDR register (TXRX buffer) when data is
transferred, writing will be ignored if data is written
to SBDR (TXRX buffer) when data is transferred.
· SBCR_A, SBCR_B: Serial bus control register
Bit7 (CKS) clock source selection: fSIO=fSYS/4,
select as 0
Bit6 (M1), Bit5 (M0) master/slave mode and baud rate
selection
M1, M0: 00 ® MASTER MODE, BAUD RATE= fSIO
01 ® MASTER MODE, BAUD RATE= fSIO/4
10 ® MASTER MODE, BAUD RATE= fSIO/16
11 ® SLAVE MODE
Bit0 (TRF) ® data transferred or data received
used to generate an interrupt.
Note: data reception is still in operation when the
MCU enters the Power-down mode.
· SBDR_A, SBDR_B: Serial bus data register
Data written to SBDR ® write data to the TXRX buffer
only
Data read from SBDR ® read from SBDR only
Operating Mode description:
Master transmitter: clock transmission and data I/O
started by writing to SBDR
Master clock transmission initiated by writing to SBDR
Slave transmitter: data I/O started by clock reception
Slave receiver: data I/O started by clock reception
· Bit4 (SBEN) ® serial bus enable/disable (1/0)
¨
Disable: SCK (SCK), SDI, SDO, SCS floating
Bit3 (MLS) ® MSB or LSB (1/0) shift first control bit
Enable: (SCS dependent on CSEN bit)
Disable ® enable: SCK, SDI, SDO, SCS= 0
(SCKB= ²0²) and waiting for writing data to SBDR
(TXRX buffer)
Master mode: write data to SBDR (TXRX buffer)
start transmission/reception automatically
Master mode: when the data has been transferred,
set TRF
Slave mode: when an SCK (and SCS dependent on
CSEN) is received, data in the TXRX buffer is
shifted-out and data on SDI is shifted-in.
Rev. 1.00
21
December 20, 2006
HT82J30R/HT82J30A
Clock polarity= rising (SCK) or falling (SCK): 1 or 0 (mask option).
Modes
Operations
1.
2.
3.
4.
Master
5.
6.
7.
8.
9.
1.
2.
3.
4.
Slave
5.
6.
7.
8.
9.
Select CKS and select M1, M0 = 00,01,10
Select CSEN, MLS (the same as the slave)
Set SBEN
Writing data to SBDR ® data is stored in TXRX buffer ® output SCK (and SCS) signals ® go to
step 5 ® (SIO internal operation ® data stored in TXRX buffer, and SDI data is shifted into TXRX
buffer ® data transferred, data in TXRX buffer is latched into SBDR)
Check WCOL; WCOL= 1 ® clear WCOL and go to step 4; WCOL= 0 ® go to step 6
Check TRF or waiting for SBI (serial bus interrupt)
Read data from SBDR
Clear TRF
Go to step 4
CKS don¢t care and select M1, M0= 11
Select CSEN, MLS (the same as the master)
Set SBEN
Writing data to SBDR ® data is stored in TXRX buffer ® waiting for master clock signal (and SCS):
SCK ® go to step 5 ® (SIO internal operations ® SCK (SCS) received ® output data in TXRX
buffer and SDI data is shifted into TXRX buffer ® data transferred, data in TXRX buffer is latched
into SBDR)
Check WCOL; WCOL= 1 ® clear WCOL, go to step 4; WCOL= 0 ® go to step 6
Check TRF or wait for SBI (serial bus interrupt)
Read data from SBDR
Clear TRF
Go to step 4
Operation of Serial Interface
WCOL: master/slave mode, set while writing to SBDR
when data is transferring (transmitting or receiving) and
this writing will then be ignored. WCOL function can be
enabled/disabled by mask option. WCOL is set by SIO
and cleared by users.
has 2 options: CSEN mask option is used to enable/disable software CSEN function. If CSEN mask option is
disabled, the software CSEN is always disabled. If
CSEN mask option is enabled, software CSEN function
can be used.
Data transmission and reception are still working when
the MCU enters the HALT mode.
SBEN= 1 ® serial bus standby; SCS (CSEN= 1) = 1;
SCS= floating (CSEN= 0); SDI= floating; SDO= 1; master SCK= output 1/0 (dependent on CPOL mask option),
slave SCK= floating.
CPOL is used to select the clock polarity of SCK. It is a
mask option.
SBEN= 0 ® serial bus disabled; SCS=SDO=1,
SDI=SCK= floating in master mode, SDI=SDO=SCK=
floating, SCS=1 in slave mode.
MLS: MSB or LSB first selection.
CSEN: chip select function enable/disable, CSEN=1 ®
SCS signal function is active. Master should output SCS
signal before SCL signal is set and slave data transferring should be disabled (or enabled) before (after) SCS
signal is received. CSEN= 0, SCS signal is not needed,
SCS pin (master and slave) should be floating. CSEN
Rev. 1.00
TRF is set by SIO and cleared by users. When data
transfer (transmission and reception) is completed, TRF
is set to generate SBI (serial bus interrupt).
22
December 20, 2006
HT82J30R/HT82J30A
S B E N = 1 , C S E N = 0 a n d w r ite d a ta to S B D R
( if p u ll- h ig h e d )
S B E N = C S E N = 1 a n d w r ite d a ta to S B D R
S C S
S C K
D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7
S D I
D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7
S D O
S C K
S B C R
D e fa u lt
S B D R
D e fa u lt
D 7
C K S
0
D 7
u
D 6
M 1
1
D 6
u
D 5
M 0
1
D 5
u
D 4
S B E N
0
D 4
u
D 3
M L S
0
D 3
u
D 2
C S E N
0
D 2
u
D 1
W C O L
0
D 1
u
D 0
T R F
0
D 0
u
N o te : "u " m e a n s u n c h a n g e d .
D a ta B u s
S B D R
( R e c e iv e d D a ta R e g is te r )
D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
M
S D O
U
X
M
a n d , s ta rt
E N
S C K
a n d , s ta rt
C lo c k P o la r ity
S D I
U
X
M
S D O
S B E N
M L S
In te r n a l B a u d R a te C lo c k
B u ffe r
U
X
T R F
C 0 C 1 C 2
M a s te r o r S la v e
A N D
In te r n a l B u s y F la g
S B E N
a n d , s ta rt
E N
W C O L F la g
W r ite S B D R
W r ite S B D R E n a b le /D is a b le
S B E N
W r ite S B D R
S C S
M a s te r o r S la v e
S B E N
C S E N
W C O L : s e t b
C S E N : e n a b
1 . m a s te r
2 . s la v e m
S B E N : e n a b
1 . W h e n S
2 . W h e n S
T R F 1 : d a ta
C P O L 1 /0 : c
Rev. 1.00
y S IO c le a r e d b y u s e r s
le /d is a b le c h ip s e le c tio n fu n c tio
m o d e 1 /0 : w ith /w ith o u t S C S o u
o d e 1 /0 : w ith /w ith o u t S C S in p u
le /d is a b le s e r ia l b u s ( 0 : in itia liz
B E N = 0 , a ll s ta tu s fla g s s h o u ld
B E N = 0 , a ll S IO r e la te d fu n c tio
tr a n s m itte d o r r e c e iv e d , 0 : d a ta
lo c k p o la r ity r is in g /fa llin g e d g e
23
n
tp
t
e
p in
u t fu n c tio n
c o n tr o l fu n c tio
a ll s ta tu s fla g
b e in itia liz e d
n p in s s h o u ld s
is tr a n s m ittin g
: m a s k o p tio n
n
s )
ta y a t flo a tin g s ta te
o r s till n o t r e c e iv e d
December 20, 2006
HT82J30R/HT82J30A
Low Voltage Reset - LVR
The relationship between VDD and VLVR is shown below.
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as when changing a battery, the LVR
will automatically reset the device internally.
V D D
5 .5 V
V
O P R
5 .5 V
V
L V R
3 .0 V
The LVR includes the following specifications:
2 .2 V
· The low voltage (0.9V~VLVR) has to remain in its origi-
nal state for longer than 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and will
not perform a reset function.
0 .9 V
Note:
· The LVR uses an ²OR² function with the external RES
VOPR is the voltage range for proper chip operation at 4MHz system clock.
signal to perform a chip reset.
V
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
R e s e t
*1
*2
Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024
system clock pulses before starting normal operation.
*2: Since a low voltage has to be maintained in its original state for longer than 1ms, therefore a 1ms delay
enters the reset mode.
Rev. 1.00
24
December 20, 2006
HT82J30R/HT82J30A
Options
The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure proper
system functioning.
Items
Options
1
Lock or unlock (1/0)
2
PA0~PA7 wake-up enable or disable (1/0) options
3
WDT clock source (fS) : WDTOSC/ fTID (0/1)
4
CLR WDT instruction(s): one or two clear WDT instruction(s) (1/0)
5
WDT enable or disable (0/1)
6
PA pull-high enable or disable (1/0)
7
PB pull-high enable or disable (1/0) by nibble
8
PC pull-high enable or disable (1/0) by nibble
9
PD pull-high enable or disable (1/0) by nibble
10
PF pull-high enable or disable (1/0) by nibble
11
PWM enable or disable
12
PFD enable or disable
13
System oscillators 0/1: RC/crystal
14
Low voltage reset: Enable or disable
15
LVR voltage: 3.0V/3.8V (0/1)
16
SIO_A (Serial Interface) enable or disable (default disable)
17
SIO_A_ CPOL: Clock polarity 1/0 : clock polarity rising or falling edge (default falling edge)
18
SIO_A_WCOL: Enable or disable (default disable)
19
SIO_A_CSEN: Enable or disable, CSEN mask option is used to enable or disable software CSEN function
(default disable)
20
PD4, PB2, PB3, PD7 CMOS or NMOS output (default CMOS)
21
SIO_B (Serial Interface) enable or disable (default disable)
22
SIO_ B_CPOL: Clock polarity 1/0: clock polarity rising/falling edge (default falling edge)
23
SIO_B_WCOL: Enable or disable (default disable)
24
SIO_B_CSEN: Enable or disable, CSEN mask option is used to enable or disable software CSEN function
(default disable)
Rev. 1.00
25
December 20, 2006
HT82J30R/HT82J30A
Application Circuits
V
D D
0 .0 1 m F *
V D D
1 0 0 k W
0 .1 m F
R E S
1 0 k W
P A 0 ~ P A 2
P A 3 /P F D
P A 4 /T M R
P A 5 /IN T 0
V
P A 6 /IN T 1
0 .1 m F *
R
P A 7
V S S
O S C 2
S e e R ig h t S id e
O S C 1
4 7 0 p F
P B 0 /A N 0
P B 7 /A N 7
P C 0 /A N 8
P C 7 /A N 1 5
C 1
P D 0 /P W M
C 2
O S C 1
P F 0 ~ P F 2
O S C 2
R 1
H T 8 2 J 3 0 R /H T 8 2 J 3 0 A
Note:
R C S y s te m O s c illa to r
3 0 k W < R O S C < 7 5 0 k W
O S C 2
N M O S o p e n d r a in
~
O S C 1
O S C
~
O S C
C ir c u it
D D
O S C
C ry s ta l S y s te m
F o r th e v a lu e s ,
s e e ta b le b e lo w
O s c illa to r
C ir c u it
The resistance and capacitance for the reset circuit should be designed to ensure that VDD is stable and remains within a valid range of the operating voltage before bringing RES high.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise
interference.
The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only)
Crystal or Resonator
C1, C2
R1
4MHz Crystal
0pF
10kW
4MHz Resonator (3 pins)
0pF
12kW
4MHz Resonator (2 pins)
10pF
12kW
3.58MHz Crystal
0pF
10kW
3.58MHz Resonator (2 pins)
25pF
10kW
2MHz Crystal & Resonator (2 pins)
25pF
10kW
1MHz Crystal
35pF
27kW
480kHz Resonator
300pF
9.1kW
455kHz Resonator
300pF
10kW
429kHz Resonator
300pF
10kW
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the
MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed.
Rev. 1.00
26
December 20, 2006
HT82J30R/HT82J30A
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.00
27
December 20, 2006
HT82J30R/HT82J30A
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 1.00
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
28
December 20, 2006
HT82J30R/HT82J30A
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
29
December 20, 2006
HT82J30R/HT82J30A
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
30
December 20, 2006
HT82J30R/HT82J30A
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
31
December 20, 2006
HT82J30R/HT82J30A
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
32
December 20, 2006
HT82J30R/HT82J30A
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
33
December 20, 2006
HT82J30R/HT82J30A
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
Program Counter ¬ Program Counter+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
34
December 20, 2006
HT82J30R/HT82J30A
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
Program Counter ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
35
December 20, 2006
HT82J30R/HT82J30A
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
36
December 20, 2006
HT82J30R/HT82J30A
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
37
December 20, 2006
HT82J30R/HT82J30A
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
38
December 20, 2006
HT82J30R/HT82J30A
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
39
December 20, 2006
HT82J30R/HT82J30A
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
40
December 20, 2006
HT82J30R/HT82J30A
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
41
December 20, 2006
HT82J30R/HT82J30A
Package Information
28-pin SKDIP (300mil) Outline Dimensions
A
B
2 8
1 5
1
1 4
H
C
D
E
Symbol
Rev. 1.00
F
a
G
I
Dimensions in mil
Min.
Nom.
Max.
A
1375
¾
1395
B
278
¾
298
C
125
¾
135
D
125
¾
145
E
16
¾
20
70
F
50
¾
G
¾
100
¾
H
295
¾
315
I
330
¾
375
a
0°
¾
15°
42
December 20, 2006
HT82J30R/HT82J30A
28-pin SOP (300mil) Outline Dimensions
2 8
1 5
A
B
1
1 4
C
C '
G
H
D
E
Symbol
Rev. 1.00
a
F
Dimensions in mil
Min.
Nom.
Max.
A
394
¾
419
B
290
¾
300
C
14
¾
20
C¢
697
¾
713
D
92
¾
104
E
¾
50
¾
F
4
¾
¾
G
32
¾
38
H
4
¾
12
a
0°
¾
10°
43
December 20, 2006
HT82J30R/HT82J30A
44-pin QFP (10´10) Outline Dimensions
H
C
D
G
2 3
3 3
I
3 4
2 2
L
F
A
B
E
1 2
4 4
K
a
J
1
Symbol
Rev. 1.00
1 1
Dimensions in mm
Min.
Nom.
Max.
A
13
¾
13.4
B
9.9
¾
10.1
C
13
¾
13.4
D
9.9
¾
10.1
E
¾
0.8
¾
F
¾
0.3
¾
G
1.9
¾
2.2
H
¾
¾
2.7
I
0.25
¾
0.5
J
0.73
¾
0.93
K
0.1
¾
0.2
L
¾
0.1
¾
a
0°
¾
7°
44
December 20, 2006
HT82J30R/HT82J30A
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
B
Reel Inner Diameter
62±1.5
C
Spindle Hole Diameter
13+0.5
-0.2
D
Key Slit Width
330±1
2±0.5
T1
Space Between Flange
24.8+0.3
-0.2
T2
Reel Thickness
30.2±0.2
Rev. 1.00
45
December 20, 2006
HT82J30R/HT82J30A
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
B 0
P
K 0
A 0
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24±0.3
P
Cavity Pitch
12±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5+0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4±0.1
P1
Cavity to Perforation (Length Direction)
2±0.1
A0
Cavity Length
10.85±0.1
B0
Cavity Width
18.34±0.1
K0
Cavity Depth
2.97±0.1
t
Carrier Tape Thickness
0.35±0.01
C
Cover Tape Width
Rev. 1.00
21.3
46
December 20, 2006
HT82J30R/HT82J30A
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 86-21-6485-5560
Fax: 86-21-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District,
Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9533
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752
Fax: 86-10-6641-0125
Holtek Semiconductor Inc. (Chengdu Sales Office)
709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016
Tel: 86-28-6653-6590
Fax: 86-28-6653-6591
Holmate Semiconductor, Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holmate.com
Copyright Ó 2006 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
47
December 20, 2006