AL440B Data Sheets Version 1.0 AVERLOGIC TECHNOLOGIES, INC. TEL: 1 408 361-0400 e-mail: [email protected] URL: www.averlogic.com November 28, 2001 AL440B Amendments 11-28-01 AL440B AL440B version 1.0 release data sheets. November 28, 2001 2 AL440B AL440B 4MBits FIFO Field Memory Contents: 1.0 Description _________________________________________________________________ 4 2.0 Features____________________________________________________________________ 4 3.0 Applications_________________________________________________________________ 4 4.0 Ordering Information _________________________________________________________ 4 5.0 Pin-out Diagram _____________________________________________________________ 5 6.0 Block Diagram ______________________________________________________________ 5 7.0 Pin Definition and Description__________________________________________________ 6 8.0 Register Definition ___________________________________________________________ 8 8.1 Register Set ____________________________________________________________________________ 8 9.0 Multiple Devices Bus Expansion and Cascading ___________________________________ 9 10.0 Serial Bus Interface _________________________________________________________ 9 11.0 Memory Operation _________________________________________________________ 11 11.1 Power-On-Reset & Initialization __________________________________________________________ 11 11.2 WRST, RRST Reset Operation ___________________________________________________________ 11 11.3 Control Signals Polarity Select ___________________________________________________________ 11 11.4 FIFO Write Operation __________________________________________________________________ 12 11.5 FIFO Read Operation___________________________________________________________________ 12 11.6 IRDY, ORDY Flags____________________________________________________________________ 13 11.7 Window Write Register Programming _____________________________________________________ 14 11.8 Window Read Register Programming ______________________________________________________ 17 12.0 Electrical Characteristics ____________________________________________________ 19 12.1 Absolute Maximum Ratings _____________________________________________________________ 19 12.2 Recommended Operating Conditions ______________________________________________________ 19 12.3 DC Characteristics _____________________________________________________________________ 19 12.4 AC Characteristics _____________________________________________________________________ 20 13.0 Timing Diagrams __________________________________________________________ 22 14.0 Mechanical Drawing – 44 PIN PLASTIC TSOP (II) ______________________________ 30 15.0 Application Notes __________________________________________________________ 32 15.1 Chip Global Reset Recommend Circuit_____________________________________________________ 32 15.2 The AL440B Reference Schematic ________________________________________________________ 32 AL440B November 28, 2001 3 AL440B 1.0 Description The AL440B 4Mbits (512k x 8-bit) FIFO memory provides completely independent 8bit input and output ports that can operate at a maximum speed of 80 MHz. The built-in address and pointer control circuits provide a very easy-to-use memory interface that greatly reduces design time and effort. Manufactured using state-of-the-art embedded high density memory cell array, the AL440B uses high performance process technologies with extended controller functions (write mask, read skip.. etc.), allowing easy operation of non-linearity and regional read/write FIFO for PIP, Digital TV, security system and video camera applications. The status flags can be used to indicate Fullness/Emptiness of the FIFO and also allow multiple cascading AL440Bs to expand the storage depth or provide a longer delay, which cannot be achieved with only a single device. Expanding AL440B data bus width is also possible by using multiple AL440B chips in parallel. To get better design flexibility, the polarities of the AL440B control signals are selectable. The read and write control signals, such as Read/Write Enable, Input/Output Enable.., can be either active low or high by pulling /PLRTY signal to high or low respectively. In AL440B, Window data write/read and data mirroring functions can offer better control assistance in the application design. The built-in registers set can be easily programmed via serial bus (I2C like control bus) to perform various useful functions such as multi-freeze, P-in-P in the digital TV, VCR, and video camera application. Available as a 44-pin TSOP (II), the small footprint allows product designers to keep real estate to a minimum. 2.0 Features • • • • • • • • • • • 4Mbits (512k x 8 bits) organization FIFO Independent 8bit read/write port operations (different read/write data rates acceptable) Maximum Read/write cycle time: 80Mhz and 40Mhz (2 speed grades) Input Enable (write mask) / Output Enable (data skipping) control Window read/write with Mirroring capable Selectable control signal polarity Input Ready / Output Ready flags Direct cascade connection Self refresh 3.3V ± 10% power supply Standard 44-pin TSOP (II) package 3.0 Applications • • • • • • • • • • Multimedia systems Video capture or editing systems for NTSC/PAL or SVGA resolution Security systems Scan rate converters PIP (Picture-In-Picture) video display TBC (Time Base Correction) Frame synchronizer Digital video camera Hard disk cache memory Buffer for communication systems * 80MHz High-Speed version • DTV/HDTV video stream buffer 4.0 Ordering Information The AL440B has two speed grades, AL440B-24 and AL440B-12, which can operate at frequencies of 40MHz and 80MHz respectively. Both speed grades are powered by 3.3V and are available in a 44-pin standard TSOP-II package. AL440B November 28, 2001 4 AL440B Part number Package Power Supply Status AL440B-24 (40MHz) 44-pin plastic TSOP(II) +3.3V±10% Sample Dec., 2001 AL440B-12 (80MHz) 44-pin plastic TSOP(II) +3.3V±10% Sample Dec.., 2001 5.0 Pin-out Diagram 28 27 26 DI6 15 16 17 18 19 20 21 22 AGND DI5 14 NC DI4 13 NC VDD 12 NC DI3 11 AVDD DI2 10 TEST DI0 9 /PLRTY 8 IRDY 7 23 Date Code WRST 6 24 Lot Number GND 5 25 Speed WCK 4 IE 3 WE 2 DI7 1 DI1 AVERLOGIC AL440B-XX XXXXX XXXX /SDAEN 29 SDA 30 SCL 31 /RESET 32 GND 33 VDD 34 NC 35 RRST 36 ORDY 37 38 RCK 39 GND DO4 40 RE VDD 41 OE DO3 42 DO7 DO2 43 DO6 DO1 44 DO5 DO0 The AL440B pin-out diagram is following. AL440B-12/24 TSOP (II) pinout diagram (Top view) 6.0 Block Diagram Write Data Register Internal Bus 512kx8 memory cell array Timing Generator & Arbiter To all Modules To all Modules Control Registers Output Buffer DO[7:0] ORDY Output Control Iutput Control /SDAEN SCL & SDA Read Data Register Memory Control IRDY WCK WRST IE WE Internal Bus Address Bus Input Buffer Control Bus DI[7:0] Refresh Counter Timing & Logic Control RCK RRST OE RE /PLRTY /RESET AL440B Block Diagram AL440B November 28, 2001 5 AL440B The internal structure of the AL440B consists of an Input/Output buffers, Write Data Registers, Read Data Registers and main 512k x8 memory cell array and the state-of-the-art logic design that takes care of addressing and controlling the read/write data. 7.0 Pin Definition and Description The pin definitions and descriptions are as follows: Write Bus Signals Pin name Pin number I/O type Description DI[7:0] 9,8,7,6,4,3,2, 1 I WE 10 I IE 11 I WCK 13 I WRST 14 I IRDY 15 O The DI pins input 8bits of data. Data input is synchronized with the WCK clock. Data is acquired at the rising edge of WCK clock. WE is an input signal that controls the 8bit input data write and write pointer operation. IE is an input signal that controls the enabling/ disabling of the 8bit data input pins. The internal write address pointer is always incremented at rising edge of WCK by enabling WE regardless of the IE level. WCK is the write clock input pin. The write data input is synchronized with this clock. The WRST is a reset input signal that resets the write address pointer to 0. IRDY is a status output flag that reports the FIFO space availability. *Note: For the polarity definition of all write control signals (WE, IE, WRST and IRDY), please refer to /PLRTY pin definition and “Memory Operation” section for details. Read Bus Signals Pin name DO[7:0] RE OE RCK AL440B Pin number I/O Description type 36,37,38,39, O The DO pins output 8bit of data. Data output is 41,42,43,44 synchronized with the RCK clock. Data is output at the rising edge of the RCK clock. 35 I RE is an input signal that controls the 8bit output data read and read pointer operation. 34 I OE is an input signal that controls the enabling/ disabling of the 8bit data output pins. The internal read address pointer is always incremented at rising edge of RCK by enabling RE regardless of the OE level. 32 I RCK is the read clock input pin. The read data November 28, 2001 6 AL440B RRST 31 I ORDY 30 O output is synchronized with this clock. The RRST is a reset input signal that resets the read address pointer to 0. ORDY is a status output flag that reports the FIFO data availability. *Note: For the polarity definition of all read control signals (RE, OE, RRST and ORDY), please refer to /PLRTY pin definition and “Memory Operation” section for details. Serial Port Bus Signals Pin name SDA SCL /SDAEN Description Pin number I/O type 25 I/O SDA carries the serial bus read/write data bits. The SDA data bit is valid when the SCL is high after start up sequence. 24 I SCL supplies the serial bus clock signal to FIFO. The serial data bit is valid when the SCL is high after start up sequence. 23 I /SDAEN controls the enabling/disabling of serial bus interface. When /SDAEN is high, the serial interface is disabled and SDA pin is high impedance. When /SDAEN is low, the serial interface is enabled and data can be written to or read from the FIFO registers. Power/Ground Signals Pin name VDD GND AVDD AGND Pin number I/O Description type 5, 29, 40 - 3.3V ± 10%. 12, 26, 33 - Ground. 18 - Dedicated power pin for the internal oscillator. 3.3V ± 10%. 22 - Dedicated ground pin for the internal oscillator. Miscellaneous Signals Pin name /RESET AL440B Pin number I/O Description type 27 I The global reset pin /RESET will automatically initialize chip logic. For the recommended circuit for the global reset signal, please refer to the Application Notes. November 28, 2001 7 AL440B /PLRTY 16 I TEST 17 I NC 19,20,21,28 - Select active polarity of the control signals including WE, RE, WRST, RRST, IE, OE, IRDY and ORDY totally 8 signals /PLRTY = VDD, active low. /PLRTY = GND, active high. Note: during memory operation, the pin must be permanently connected to VDD or GND. If /PLRTY level is changed during memory operation, memory data is not guaranteed. For testing purpose only. No connect or connect to Ground. No connect or connect to Ground 8.0 Register Definition There are some built-in registers in the AL440B that allows performing some optional functions such as window read/write access. These registers can be programmed via serial bus (SDA, SCL and /SDAEN). The serial bus interface protocol is illustrated in “Serial Bus Interface” chapter. The serial bus control software code or tool is available at Averlogic Technologies, Inc. upon request. 8.1 Register Set Address 00h 02h 03h 04h 05h 06h Register COMPANYID WSTART_L WSTART_H WXSIZE_L WXSIZE_H WSTRIDE_L R/W R R/W R/W R/W R/W R/W 07h WSTRIDE_H R/W 08h 09h 0Ah WYSIZE_L WYSIZE_H WWCTRL R/W R/W R/W 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h RSTART_L RSTART_H RXSIZE_L RXSIZE_H RSTRIDE_L RSTRIDE_H RYSIZE_L R/W R/W R/W R/W R/W R/W R/W AL440B Description Company ID (46h) Window write starting address (Low byte) Window write starting address (High byte) Window write horizontal size (Low byte) Window write horizontal size (High byte) Window write strike size (Low byte) 2’s complement (for Y-mirror) Window write strike size (High byte) 2’s complement (for Y-mirror) Window write vertical size (Low byte) Window write vertical size (High byte) Window write control register [7]: enable window write function [6]: X mirror [5]: freeze Window read starting address (Low byte) Window read starting address (High byte) Window read horizontal size (Low byte) Window read horizontal size (High byte) Window read strike size (Low byte) Window read strike size (High byte) Window read vertical size (Low byte) November 28, 2001 8 AL440B 12h 13h RYSIZE_H RWCTRL R/W Window read vertical size (High byte) R/W Window read control register [7]: enable window read function 9.0 Multiple Devices Bus Expansion and Cascading The AL440B FIFO memory can be applied to very wide range of media applications. A parallel connect or cascade of multiple AL440B FIFOs provides FIFO bus width or memory depth expansion for some applications; eg. accommodating HDTV resolution.. etc. Read Reset Write Reset AL440 8-bit Input RRST DI[7:0] DO[7:0] Input Enable FIFO Empty IE Write Enable WE OE ORDY IRDY Write Clock AL440 WRST RE WRST RRST 8-bit Output DI[7:0] DO[7:0] (2) IE (2) (1) (1) FIFO Empty RRST DI[7:0] DO[7:0] WE WCK Read Clock RCK WCK AL440 WRST IE IRDY Read Enable RE WE AL440 8-bit Input Output Enable FIFO Full ORDY IRDY RCK WCK 8-bit Output OE OE WRST RRST 8-bit Output DI[7:0] DO[7:0] (2) (2) IE IRDY (1) (1) WE ORDY RE RCK WCK 8-bit Output OE ORDY FIFO Full RE RCK (1) Logic Block: "OR" Gate if /PLTY = HIGH, "AND" Gate if /PLTY = HIGH (2) Always Enabled : Tie to LOW if /PLTY = HIGH, Tie to High if /PLTY = LOW AL440B Expanding & Cascading 10.0 Serial Bus Interface The serial bus interface consists of the SCL (serial clock), SDA (serial data) and /SDAEN (serial interface enable) signals. There are pull up circuit internally for both SCL and SDA pins. When /SDAEN is high, the serial bus interface is disabled and both SCL and SDA pins are pulled high. When /SDAEN is low, the serial bus interface is enabled and data can be written into or read from the AL440B register set. For both read and write, each byte is transferred MSB first and LSB last, and the SDA data bit is valid when the SCL is pulled high. The serial bus control sample C code is available in Averlogic Technologies, Inc. upon request. The read/write command format is as follows: Write: <S> <Write SA> <A> <Register Index> <A> <Data> <A> <P> AL440B November 28, 2001 9 AL440B Read: <S> <Write SA> <A> <Register Index> <A> <S> <Read SA> <A> <Data> <NA> <P> Following are the details: <S>: Start signal SCL SDA High High High Low The Start signal is HIGH to LOW transition on the SDA line when SCL is HIGH. <WRITE SA>: Write Slave Address: 0h <READ SA>: Read Slave Address: 1h <REGISTER INDEX>: Value of the AL440B register index. <A>: Acknowledge stage The acknowledge-related clock pulse is generated by the host (master). The host releases the SDA line (HIGH) for the AL440B (slave) to pull down the SDA line during the acknowledge clock pulse. <NA>: Not Acknowledged stage The acknowledge-related clock pulse is generated by the host (master). The host releases the SDA line (HIGH) during the acknowledge clock pulse, but the AL440B does not pull it down during this stage. <DATA>: Data byte write to or read from the register index. In read operation, the host must release the SDA line (high) before the first clock pulse is transmitted to the AL440B. <P>: Stop signal SCL SDA High Low High High The Stop signal is LOW to HIGH transition on the SDA line when SCL is HIGH. Suppose data F0h is to be written to register 0Fh using write slave address 0h, the timing is as follows: AL440B November 28, 2001 10 AL440B Start Slave addr = 0h Ack Index = 0Fh Ack Data = F0h Ack Stop SDA SCL AL440B Serial bus Write timing Suppose data is to be read from register 05h using read slave address 1h, the timing is as follows: Start Slave addr = 0h Ack Index = 05h Ack Stop Read slave addr = 1h NAck Start Ack Data read cycle Stop SDA SCL AL440B Serial bus read timing 11.0 Memory Operation 11.1 Power-On-Reset & Initialization During the system power on, a 200µs negative pulse on the /RESET pin is required and will automatically initialize chip logic. Apply a valid reset pulse to WRST and RRST after power-onreset to reset read/write address pointer to zero. 11.2 WRST, RRST Reset Operation The reset signal can be given at any time regardless of the WE, RE and OE status, however, they still need to meet the setup time and hold time requirements with reference to the clock input. When the reset signal is provided during disabled cycles, the reset operation is not executed until cycles are enabled again. 11.3 Control Signals Polarity Select The AL440B provides the option for operating polarity on controlling signals. With this feature the application design can benefit by matching up the operation polarity between AL440B and an existing interfacing devices without additional glue logic. The operating polarity of control signals WE, RE, WRST, RRST, IE, OE, IRDY and ORDY are controlled by /PLRTY signal. When /PLRTY is pulled high all 8 signals will be active low. When /PLRTY is pulled low all 8 signals will be active high. AL440B November 28, 2001 11 AL440B 11.4 FIFO Write Operation In the FIFO write operation, 8 bits of write data are input in synchronization with the WCK clock. The FIFO write operation is determined by WRST, WE, IE and WCK signals and the combination of these signals could produce different write result. The /PLRTY signal determines the activated polarity of these control signals. The following tables describe the WRITE functions under different operating polarities. /PLRTY = VDD WRST L WE - IE - H H L L L H H H - WCK Function Write reset. ↑ The write pointer is reset to zero. Normal Write operation. ↑ Write address pointer increases, but no new data will be ↑ written to memory. Old data is retained in memory. (Write mask function) Write operation stopped. Write address pointer is also stopped. ↑ /PLRTY = GND WRST H WE - IE - L L H H H L L L - WCK Function Write reset. ↑ The write pointer is reset to zero. Normal Write operation. ↑ Write address pointer increases, but no new data will be ↑ written to memory. Old data is retained in memory. (Write mask function) Write operation stopped. Write address pointer is also stopped. ↑ 11.5 FIFO Read Operation In the FIFO read operation, 8 bits of read data are available in synchronization with the RCK clock. The access time is stipulated from the rising edge of the RCK clock. The FIFO read operation is determined by RRST, RE, OE and RCK signals, so the combination of these signals could produce varying read results. The /PLRTY signal could decide the activated polarity of these control signals. The following tables describe the READ functions under different operating polarities. /PLRTY = VDD RRST L RE L OE L L L H L H L AL440B RCK Function Read reset. The read pointer is reset to zero. ↑ Data in the address 0 is output. Read reset. The read pointer is reset to zero. ↑ Output is high impedance. Read address pointer is stopped. Output data is held. Read ↑ address pointer will be reset to zero and data in the address 0 is output after RE goes low. November 28, 2001 12 AL440B L H H ↑ H H L L L H ↑ ↑ H H H H L H ↑ ↑ Read address pointer is stopped. Output data is held. Read address pointer will be reset to zero and output is high impedance after RE goes low. Normal Read operation. Read address pointer increases. Output is high impedance. (Data skipping function) Read address pointer is stopped. Output data is held. Read operation stopped. Read address pointer is stopped. Output is high impedance. /PLRTY = GND RRST H RE H OE H H H L H L H H L L L L H H H L L L L L H L RCK Function Read reset. The read pointer is reset to zero. ↑ Data in the address 0 is output. Read reset. The read pointer is reset to zero. ↑ Output is high impedance. Read address pointer is stopped. Output data is held. Read ↑ address pointer will be reset to zero and data in the address 0 is output after RE goes low. Read address pointer is stopped. Output data is held. Read ↑ address pointer will be reset to zero and output is high impedance after RE goes low. Normal Read operation. ↑ Read address pointer increases. Output is high impedance. ↑ (Data skipping function) Read address pointer is stopped. Output data is held. ↑ Read operation stopped. Read address pointer is stopped. ↑ Output is high impedance. When the new data is read, the read address should be between 192 and 524,287 cycles after the write address pointer, otherwise the output for new data is not guarantee. 11.6 IRDY, ORDY Flags The IRDY, ORDY flags indicate the status of FIFO. The IRDY signal reports whether or not there is space available for writing new data to the FIFO. An ORDY signal reports whether or not there is valid new data available at output. The IRDY and ORDY signals only report the status of the address pointer; they will not stop or affect the read/write operations. The following tables describe the IRDY/ORDY functions under different operating polarities. /PLRTY = VDD Signal IRDY ORDY AL440B State H L H Function No more free space is available for new input data Memory space is available for new input data. No new data is available in FIFO memory. November 28, 2001 13 AL440B L New data are available in the FIFO memory. /PLRTY = GND Signal IRDY ORDY State H L H L Function Memory space is available for new input data. No more free space is available for new input data New data are available in the FIFO memory. No new data is available in FIFO memory. 11.7 Window Write Register Programming Window data read/write is supported in the AL440B to benefit the designing effort for applications such as PIP display. The window mode is enabled by driving low on /SDAEN signal. A serial bus can program built-in registers to set up coordinates of the window and the settings take effect following by next read/write reset pulse. Window mirroring can cooperate with the window mode data access to flip window data in x or y direction. When window-mirroring function is turned on, write data can be stored in reverse sequence. 0 1 2 Block number: 8189 8190 8191 The serial communication interface consists of 3 signals, they are SCL (serial clock), SDA (serial data) and /SDAEN (window mode enable). The serial communication interface is enabled by driving low on /SDAEN signal. The detail operation timing of the serial bus is illustrated in chapter 10. In Window read/write mode, read and/or write may begin at the start address of any of the 8192 blocks. Each block is 64 bytes in length. (8192 blocks x 64 byte = 512 kbytes) 64 bytes each block Memory size: 8192 blocks x 64 bytes = 512 kbytes AL440B Window mode block address The Window Write related registers are listed as follows: WSTART_L and WSTART_H define the widow data write starting address. Addr Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 02h WSTART_L [7] [6] [5] [4] [3] [2] 03h WSTART_H 0 0 0 [12] [11] [10] WSTART (Write Start address) <= WSTART_H[4:0] & WSTART_L ; WSTART range is from 0 to 8191 (block). AL440B Bit1 [1] [9] Bit0 [0] [8] November 28, 2001 14 AL440B WXSIZE_L and WXSIZE_H define the window data write horizontal size. Addr Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 04h WXSIZE_L [7] [6] [5] [4] [3] [2] 05h WXSIZE_H 0 0 0 0 0 0 WXSIZE (Write X Size) <= WXSIZE_H[2:0] & WXSIZE_L ; WXSIZE range is from 0 to 1023 (block). Bit1 [1] [9] Bit0 [0] [8] WXSTRIDE_L and WXSTRIDE_H define the window data write horizontal width. Addr Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 06h WSTRIDE_L [7] [6] [5] [4] [3] [2] [1] [0] 07h WSTRIDE_H 0 0 0 [12] [11] [10] [9] [8] WSTRIDE (Write Stride) <= WSTRIDE_H[4:0] & WSTRIDE _L ; WSTRIDE range is from –4096 to +4095 (block). When the value of WSTRIDE is negative, it is used to implement Y-Mirror function. WYSIZE_L and WYSIZE_H define the window data write vertical high. Addr Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 08h WYSIZE_L [7] [6] [5] [4] [3] [2] 09h WYSIZE_H [15] [14] [13] [12] [11] [10] WYSIZE (Write Y Size) <= WYSIZE_H & WYSIZE_L ; Write Y Size range is from 0 to 65535 (unsign). Bit1 [1] [9] Bit0 [0] [8] WWCTRL is the register that control window data write function enable/disable and the window mirroring write. Addr Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0Ah WWCTRL [7] [6] [5] 0 0 0 0 0 WWCTRL[7] Window Write mode enable 1: enable Window Write mode 0: disable Window Write mode. The memory is operating in standard FIFO write mode. WWCTRL[6] X-mirror function enable 1: enable X-mirror function 0: disable X-mirror function WWCTRL[5] Freeze function enable. This function is as same as hardware “Write Mask” function. When Window Write mode is enabled, software freeze function override hardware Write Mask function. On the other hand, in FIFO mode (WWCTRL[7] = ‘0’), Register WWCTRL[5] is ignored. 1: enable software Freeze function 0: disable software Freeze function A mirroring read/write function can be cooperated with the window-block data access function. By turning on the mirroring read/write function in the window block access mode, write data can be AL440B November 28, 2001 15 AL440B stored in reversed sequence. For some applications like video conferencing, this function can correct reciprocal positioning of a captured object. Please refer the following diagrams which illustrate Window Write operation. Memory Area WSTART+(XSIZE-1) WXSIZE WSTART WSTART+1xWSTRIDE WSTART+2xWSTRIDE Normal Write Window: Go ba ck to WS TA RT WYSIZE WWCTRL[6]: 0 No X-mirror WSTRIDE: postive numer No Y-mirror Write Window Area WSTART+(WYSIZE-1)x WSTRIDE AL440B Write Window(1) Memory Area WSTART-XSIZE+1 WXSIZE WSTART WSTART+1xWSTRIDE X-mirror Write Window: WSTART+2xWSTRIDE G o ba ck to W S R TA T WYSIZE WWCTRL[6]: 1 X-mirror WSTRIDE: postive numer No Y-mirror Write Window Area WSTART+(WYSIZE-1)x WSTRIDE AL440B-03 Write Window(2) AL440B November 28, 2001 16 AL440B Memory Area WSTART+(WYSIZE-1)x WSTRIDE Write Window Area G o ba ck to W ST AR T X-mirror & Y-mirror Write Window: WYSIZE WWCTRL[6]: 1 X-mirror WSTRIDE: negative numer Y-mirror WSTART+2xWSTRIDE WSTART+1xWSTRIDE WSTART-XSIZE+1 WXSIZE WSTART AL440B Write Window(3) 11.8 Window Read Register Programming The operations of Window Read function are same as Window Write. The operation of Window Read is operated independently from Window Write. The Window Read related registers are listed as follows: RSTART_L and RSTART_H define the widow data read starting address. Addr Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0Bh RSTART_L [7] [6] [5] [4] [3] [2] [1] [0] 0Ch RSTART_H 0 0 0 [12] [11] [10] [9] [8] RSTART (Read Start address) <= RSTART_H[4:0] & RSTART_L ; RSTART range is from 0 to 8191 (block). RXSIZE_L and RXSIZE_H define the window data read horizontal size. Addr Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 0Dh RXSIZE_L [7] [6] [5] [4] [3] [2] 0Eh RXSIZE_H 0 0 0 0 0 0 RXSIZE (Read X Size) <= RXSIZE_H[2:0] & RXSIZE_L ; WXSIZE range is from 0 to 1023 (block). Bit1 [1] [9] RXSTRIDE_L and RXSTRIDE_H define the window data write horizontal width. Addr Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 0Fh RSTRIDE_L [7] [6] [5] [4] [3] [2] [1] 10h RSTRIDE_H 0 0 0 0 [11] [10] [9] RSTRIDE (Read Stride) <= RSTRIDE_H[3:0] & RSTRIDE _L ; RSTRIDE range is from 0 to +4095 (block). AL440B Bit0 [0] [8] Bit0 [0] [8] November 28, 2001 17 AL440B RYSIZE_L and RYSIZE_H define the window data read vertical high. Addr Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 11h RYSIZE_L [7] [6] [5] [4] [3] [2] 12h RYSIZE_H [15] [14] [13] [12] [11] [10] RYSIZE (Read Y Size) <= RYSIZE_H & RYSIZE_L ; Write Y Size range is from 0 to 65535. Bit1 [1] [9] Bit0 [0] [8] RWCTRL is the register that control window data read function enable/disable . Addr Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 13h RWCTRL [7] 0 0 0 0 0 0 Bit0 0 RWCTRL[7] Read Write mode enable 1: enable Window Read mode 0: disable Window Read mode. The memory is operating in standard FIFO Read mode. Note: 1. X-mirror and Y-mirror functions are not needed in Window Read mode, so they are not implemented in Window Read operation. 2. There is no “freeze” function in Window Read mode. Please refer to the following illustration as an application example for the explanation of Window read operation. Memory Area RXSIZE RSTART RSTART+ (RXSIZE-1) RSTART+1xRSTRIDE RSTART+2xRSTRIDE RYSIZE Go ba ck to RS TA RT Read Window Area RSTART+ (RYSIZE-1)x RSTRIDE AL440B Read Window AL440B November 28, 2001 18 AL440B 12.0 Electrical Characteristics 12.1 Absolute Maximum Ratings Parameter VDD Supply Voltage VP Pin Voltage IO Output Current TAMB Ambient Op. Temperature Tstg Storage temperature Rating Unit -0.3 ~ +3.8 V -0.3 ~ +(VDD+0.3) V -20 ~ +20 mA 0 ~ +85 °C -40 ~ +125 °C 12.2 Recommended Operating Conditions Parameter Min Typ Max Unit +3.0 +3.3 +3.6 V VDD Supply Voltage VIH High Level Input Voltage 0.7 VDD VDD V VIL Low Level Input Voltage 0 0.3 VDD V 12.3 DC Characteristics (VDD = 3.3V, Vss=0V. TAMB = 0 to 70°C) Parameter Min Typ Max Unit IDD Operating Current - 52 62 mA IDDS Standby Current - 14 - mA VOH Hi-level Output Voltage 2.4 - VDD V VOL Lo-level Output Voltage - - +0.4 V ILI Input Leakage Current (No pull-up or pull-down) -5 - +5 µA ILO Output Leakage Current (No pull-up or pull-down) -5 - +5 µA RL Input Pull-up/Pull-down Resistance 1. 2. AL440B 50 KΩ Tested with outputs disabled (IOUT = 0) RCLK and WCLK toggle at 20 Mhz and data inputs switch at 10 Mhz. November 28, 2001 19 AL440B 12.4 AC Characteristics (VDD = 3.3V, Vss=0V, TAMB = 0 to 70°C) 40MHz Parameter AL440B 80MHz Unit Min Max Min Max TWC WCK Cycle Time 25 - 12.5 - ns TWPH WCK High Pulse Width 10 - 5 - ns TWPL WCK Low Pulse Width 10 - 5 - ns TRC RCK Cycle Time 25 - 12.5 - ns TRPH RCK High Pulse Width 10 - 5 - ns TRPL RCK Low Pulse Width 10 - 5 - ns TAC Access Time - 20 - 12 ns TOH Output Hold Time 6 - 4 - ns THZ Output High-Z Setup Time 5 4 ns TLZ Output Low-Z Setup Time 6 5 ns TWRS WRST Setup Time 8 - 4 - ns TWRH WRST Hold Time 8 - 5 - ns TRRS RRST Setup Time 8 - 4 - ns TRRH RRST Hold Time 8 - 5 - ns TDS Input Data Setup Time 5 - 4 - ns TDH Input Data Hold Time 6 - 5 - ns TWES WE Setup Time 6 - 4 - ns TWEH WE Hold Time 6 - 5 - ns TWPW WE Pulse Width 15 - 12 - ns TRES RE Setup Time 6 - 4 - ns TREH RE Hold Time 6 - 5 - ns TRPW RE Pulse Width 15 - 12 - ns TIES IE Setup Time 6 - 4 - ns TIEH IE Hold Time 6 - 5 - ns TIPW IE Pulse Width 15 - 12 - ns TOES OE Setup Time 8 - 5 - ns TOEH OE Hold Time 8 - 5 - ns TOPW OE Pulse Width 20 - 12 - ns TTR Transition Time 3 CI Input Capacitance - 3 7 - ns 7 pF November 28, 2001 20 AL440B CO • Output Capacitance - 7 - 7 pF The read address needs to be at least 192 cycles after the write address. AL440B November 28, 2001 21 AL440B 13.0 Timing Diagrams Reset cycle (s) cycle n cycle 0 cycle 1 WCK TTR TWRS TWRH WRST TDS DI7~0 n-1 /PLRTY=VDD n TDH 0 , WE= "L" 1 , IE= "L" Write Cycle Timing (Write Reset) cycle n cycle n+1 Disable cycle (s) cycle n+2 TWPL WCK TWPH TWC TWES TWEH WE TWPW TDS DI7~0 n-1 /PLRTY=VDD ,IE="L" TDH n n+1 n+2 ,WRST="H" Write Cycle Timing (Write Enable) AL440B November 28, 2001 22 AL440B cycle n cycle n+1 Disable cycle (s) cycle 0 cycle 1 T WPL WCK T WPH T WC T WRS T WRH WRST T WES T WEH WE T WPW T DS DI7~0 n-1 TDH n n+1 0 1 /PLRTY=VDD ,IE="L" Write Cycle Timing (WE, WRST) cycle n cycle n+1 cycle n+2 cycle n+3 cycle n+4 TWPL WCK TWPH TWC TIES TIEH IE TIPW TIH DI7~0 n-1 /PLRTY=VDD ,WE="L" n n+1 n+4 ,WRST="H" Write Cycle Timing (Input Enable) AL440B November 28, 2001 23 AL440B Reset cycle (s) cycle n cycle 0 cycle 1 TRPL RCK TRPH TRRS TRRH RRST TAC TOH DO7~0 n-1 /PLRTY=VDD n ,RE= "L" 0 0 1 ,OE= "L" Read Cycle Timing (Read Reset) cycle n cycle n+1 Disable cycle (s) cycle n+2 TRPL RCK TRPH TRC TRES TREH RE TRPW TAC TOH DO7~0 n-1 n n+1 n+2 /PLRTY=VDD ,OE="L" ,RRST="H" Read Cycle Timing (Read Enable) AL440B November 28, 2001 24 AL440B cycle n cycle n+1 Disable cycle (s) cycle 0 TRPL RCK TRPH TRC TRRS TRRH RRST TRES TREH RE TRPW TAC TOH DO7~0 n-1 n n+1 0 /PLRTY=VDD ,OE="L" Read Cycle Timing (RE, RRST) cycle n cycle n+1 cycle n+2 cycle n+3 cycle n+4 TRPL RCK TRPH TRC TOES TOEH OE TOPW TAC TOH DO7~0 n-1 /PLRTY=VDD ,RE="L" n THZ n+1 TLZ Hi-Z n+4 ,RRST="H" Read Cycle Timing (Output Enable) AL440B November 28, 2001 25 AL440B Reset cycle (s) cycle n cycle 0 cycle 1 WCK TTR TWRS TWRH WRST TDS DI7~0 n-1 /PLRTY=GND n TDH 0 , WE= "H" 1 , IE= "H" Write Cycle Timing (Write Reset) cycle n cycle n+1 Disable cycle (s) cycle n+2 TWPL WCK TWPH TWC TWES TWEH WE TWPW TDS DI7~0 n-1 /PLRTY=GND ,IE="H" TDH n n+1 n+2 ,WRST="L" Write Cycle Timing (Write Enable) AL440B November 28, 2001 26 AL440B cycle n cycle n+1 Disable cycle (s) cycle 0 cycle 1 TWPL WCK TWPH TWC TWRS TWRH WRST TWES TWEH WE TWPW TDS DI7~0 n-1 TDH n n+1 0 1 /PLRTY=GND ,IE="H" Write Cycle Timing (WE, WRST) cycle n cycle n+1 cycle n+2 cycle n+3 cycle n+4 TWPL WCK TWPH TWC TIES TIEH IE TIPW TIH DI7~0 n-1 /PLRTY=GND ,WE="H" n n+1 n+4 ,WRST="L" Write Cycle Timing (Input Enable) AL440B November 28, 2001 27 AL440B Reset cycle (s) cycle n cycle 0 cycle 1 TRPL RCK TRPH TRRS TRRH RRST TAC TOH DO7~0 n-1 n /PLRTY=GND ,RE= "H" 0 0 1 ,OE= "H" Read Cycle Timing (Read Reset) cycle n cycle n+1 Disable cycle (s) cycle n+2 TRPL RCK TRPH TRC TRES TREH RE TRPW TAC TOH DO7~0 n-1 /PLRTY=GND ,OE="H" n n+1 n+2 ,RRST="L" Read Cycle Timing (Read Enable) AL440B November 28, 2001 28 AL440B cycle n cycle n+1 Disable cycle (s) cycle 0 TRPL RCK TRPH TRC TRRS TRRH RRST TRES TREH RE TRPW TAC TOH DO7~0 n-1 n n+1 0 /PLRTY=GND ,OE="H" Read Cycle Timing (RE, RRST) cycle n cycle n+1 cycle n+2 cycle n+3 cycle n+4 TRPL RCK TRPH TRC TOES TOEH OE TOPW TAC TOH DO7~0 n-1 /PLRTY=GND n ,RE="H" THZ n+1 TLZ Hi-Z n+4 ,RRST="L" Read Cycle Timing (Output Enable) AL440B November 28, 2001 29 AL440B 14.0 Mechanical Drawing – 44 PIN PLASTIC TSOP (II) AL440B November 28, 2001 30 (Unit: mm) “D ” “b” NOTE: 1. Controlling Dimension : Millimeters. 2. Dimension “D” does not include mold protrusion. Mold protrusion shall not exceed 0.15(0.006”) per side. Dimension “E1” does not include interlead protrusion. Interlead protrusion shall not exceed 0.25(0.01”) per side. 3. Dimension “b” does not include damar protrusions/intrusion. Allowable damar protrusion shall not cause the lead to be wider than the MAX “b” dimension by more than 0.13mm. Damar intrusion shall not cause the lead to be narrower than the MIN “b” dimension by more than 0.07mm. AL440B November 28, 2001 31 15.0 Application Notes 15.1 Chip Global Reset Recommend Circuit To ensure a proper reset pulse can be applied to /RESET pin (pin 27) to complete the power-on reset, the recommend reset circuit is to connect the AL440B /RESET pin (pin 27) to VDD with a 2k Ω resistor and to Ground with a 10µf capacitor as follows. AL440B 8-bit Input DI[7:0] DO[7:0] 8-bit Output VDD 2K Ohm /RESET 27 50K Ohm 10 uf AL440B Global Reset Circuit It is also recommend adding buffers for the power-on reset circuit to increase the driving capability for any application with multiple AL440B chips. 15.2 The AL440B Reference Schematic U8 AL440 VDD3S DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 RNSMD1 1 2 3 4 WE IE WCK WRST IRDY R2 R5 2K DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 44 43 42 41 39 38 37 36 DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 35 34 32 31 30 25 24 23 RNSMD3 CTL7 1 CTL8 2 CTL9 3 CTL10 4 CTL11 1 CTL12 2 CTL13 3 CTL14 4 10 8 7 6 5 CTL0 CTL1 CTL2 CTL3 CTL4 CTL5 10 R3 1 2 3 4 6 7 8 9 10 11 13 14 15 16 17 WE IE WCK WRST IRDY PLRTY TEST 2K RE OE RCK RRST ORDY SDA SCL SDAEN VDD3S R6 4.7K R7 4.7K 10 8 7 6 5 8 7 6 5 RNSMD4 10 RE OE RCK RRST ORDY SDA SCL SDAEN R1 2K VDD3S 5 29 40 Populate R2 or R3 to select Control Singals polarity 1 L5 F B 2 0.1uf C55 C56 C57 18 FAVDD 0.1uf 12 26 33 GND GND GND AGND 22 1 10 F L7 B FB 2 VDD3S + C67 10uF C62 28 19 20 21 10uF AVDD FDVDD 0.1uf 0.1uf FB C54 + /RESET R5 NC NC NC NC VDD3S VDD VDD VDD 27 AL440B November 28, 2001 32 CONTACT INFORMATION AverLogic Technologies, Inc. 90 Great Oaks Blvd. #204 San Jose, CA 95119 USA Tel : +1 408 361-0400 Fax : +1 408 361-0404 E-mail : [email protected] URL : www.averlogic.com AverLogic Technologies, Corp. 4F., No.514, Sec.2, Cheng Kung Rd., Nei-Hu Dist., Taipei, Taiwan R.O.C Tel : +886 2-27915050 Fax : +886 2-27912132 E-mail : [email protected] URL : www.averlogic.com.tw