PRO-LINX ™ GS7000 Serial Digital Video Transceiver PRELIMINARY DATA SHEET DESCRIPTION • fully integrated 270Mb/s SDI receiver or transmitter The GS7000 is a dual function IC capable of operating as either a 270Mb/s Serial Digital Video receiver or a 270Mb/s Serial Digital Video transmitter. The GS7000 is designed so that it can be programmed to operate in either receive or transmit mode via a mode select pin. • fully compliant with SMPTE 259M-C • lock and carrier detect output indication • performance from 0 - 85°C RECEIVER FUNCTION • accepts SMPTE 259M-C 270Mb/s serial digital video and outputs SMPTE 125M compliant 27Mb/s parallel digital video and clock • integrated cable equalization (beyond 100m Belden 8281) • ease of design use and adjustment free operation • H timing signal output TRANSMITTER FUNCTION • accepts SMPTE 125M (27Mb/s) parallel video data and clock, outputs SMPTE 259M-C 270Mb/s serial digital video • integrated cable driver provides one differential output (or two single-ended outputs) When operating as a receiver, the serial data input accepts SMPTE 259M-C compliant signals. Line terminations are on the device. An on-chip by-passable fixed gain equalizer provides cable equalization beyond 100m of high quality co-axial cable. The clock recovery is performed on chip with minimal external components. Incoming Serial Digital Video data is decoded using a NRZI decoder and SMPTE descrambler to provide clocked SMPTE 125M compliant parallel output. The SMPTE descrambler and NRZI decoding functions can be disabled. When operating as a transmitter, the GS7000 accepts parallel SMPTE 125M compliant ten bit video. An on-chip scrambler and NRZI encoder converts the parallel data into a bit serial SMPTE 259M-C compliant NRZI output signal suitable for driving co-axial cable. Through the SMPTE select pin, the SMPTE scrambler and NRZI coding functions can be disabled. APPLICATIONS Space limited, low power 270Mb/s serial to parallel or parallel to serial interfaces; Alternate, broadcast quality uncompressed video interface for industrial and professional video equipment using the IEEE P1394 interface. SMPTE 10 PART NUMBER PACKAGE TEMPERATURE GS7000-CQT 52 pin MQFP 0°C to 85°C GS7000-CTT 52 pin MQFP Tape 0°C to 85°C C1 C2 NRZI ENCODER SCRAMBLER DIN (0,9) ORDERING INFORMATION P to S SDO SDO f/10 SIGNAL LOCK DETECT PLL PCLKOUT H PCLKIN MUX DOUT(0,9) S to P LOCK CD TRS DETECTOR 10 DESCRAMBLER NRZI DECODER SLICER EQUALIZER SDI SDI SMPTE Rx/Tx EQ BLOCK DIAGRAM Revision Date: August 1999 Document No. 522 - 06 - 02 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected] www.gennum.com GS7000 FEATURES ABSOLUTE MAXIMUM RATINGS PARAMETER VALUE Supply Voltage GS7000 Input Voltage Range (any input) 5.5V VEE < VIN < VCC DC Input Current (any one input) 10mA Power Dissipation (VCC = 5.25 V) 830mW Maximum Die Temperature Operating Temperature Range Storage Temperature Range 125°C 0°C ≤ TA ≤ 85°C -65°C ≤ TS ≤ 150°C Lead Temperature (soldering 10s) 260°C AC ELECTRICAL CHARACTERISTICS (Receiver Mode) VCC = 5V, VEE = 0V, TA = 0°C to 85°C, unless otherwise specified. Serial Data Rate = 270Mb/s, Parallel Data Rate = 27Mb/s, fPCLK = 27MHz CONDITIONS SYMBOL MIN TYP MAX UNITS NOTES TEST LEVEL CL = 20pF tR/F_PDO 1.0 - 6.0 ns 1 1 tD - - ±5 ns 2, 3 1 CL = 20pF tR/F_PCLKo 0.5 - 3.0 ns 1 1 75Ω match LOSSIN - 17 - dB Asynchronous Lock Time tLOCK_ASYNC - - 250 ms 4 1 Synchronous Lock Time tLOCK_SYNC - - 10 µs 5 1 PARAMETER Parallel Data Output - Rise/Fall Time PCLK rising edge to DOUT(n) center PCLK rise/fall time Input Return Loss 6 5MHz -> 270MHz Input Jitter Tolerance pathological Input tJ_SI - 0.4 - U.I. 6 4 Output PCLK Jitter pathological Input tJ_PCLKo - 1000 - ps p-p 6 1 Max Error Free Cable Length pathological Input 75 100 - m 6, 7 1, 4 NOTES TEST LEVELS 1. Rise/Fall time is defined as the time for the signal to rise from 20% to 80% of the specified p-p value, or to fall from 80% to 20% of the specified value. 1. 100% tested at 25 °C 2. Refer also to Figure 21. 3. This is the time difference between the rising edge of PCLKOUT and the center of the bit period. 3. Inferred or correlated value 4. This is the time delay between a valid serial TRS signal on the input, to the moment valid data appears on the parallel outputs. 4. Evaluated using test setup Figure 1a. 5. This is the time for the PLL to re-lock when video streams are switched during the vertical blanking interval in accordance with SMPTE RP168-1993. The two streams may be 180° out of phase with respect to one another, but pixel aligned. 5. Evaluated using test setup Figure 1b. 6. This pathological pattern is defined in SMPTE RP178-1996, paragraphs 4.1 and 4.3. 7. "Error free" is defined as no single bit errors over a period of 10 minutes, using Belden 8281 Cable and 75Ω connections. The MIN value is fully tested and the TYP value is based on using the EB7000 Evaluation Board. 2 522 - 06 - 02 2. Guaranteed by design 6. Evaluated using test setup Figure 1c. AC ELECTRICAL CHARACTERISTICS (Transmitter Mode) VCC = 5V, VEE = 0V, TA = 0°C to 85°C, unless otherwise specified in ‘conditions’ Serial Data Rate = 270Mb/s, Parallel Data Rate = 27Mb/s, fPCLK = 27MHz PARAMETER CONDITIONS UNITS NOTES TEST LEVEL 10 ns 1 2 - - ns 8 1 4 - - ns 8 1 MIN Parallel Data Inputs - rise/fall time tR/F_DPI 0.5 Parallel Data Inputs - setup tSETUP 4 Parallel Data Inputs - hold tHOLD TYP Parallel Data Inputs - high VCC = 5.25V VDPI 2.0 - VCC V 1 Parallel Data Inputs - low VCC = 4.75V VDPI VEE - 0.8 V 1 tR/F_PCLK 0.5 - 4 ns 2 VDSO 720 800 880 mV p-p 9, 10 1 Serial Data Output - high VOH - VCC - 0.8 - V 11 2 Serial Data Output - low VOL - VCC - 1.6 - V 11 2 Serial Data Output - rise/fall time tR/F 400 600 1500 ps 1 1 tJ_DSO - - 675 ps p-p 12 1 tLOCK - - 250 ms 13 1 15 - - dB Parallel Clock Input - rise/fall time Serial Data Output - signal swing Serial Data Output - jitter VCC = 4.75 - 5.25V VCC = 4.75V Lock Time Output Return Loss 270MHz 6 NOTES TEST LEVELS 8. Refer to Figure 26. 1. 100% tested at 25°C 9. The outputs are capable of driving a 75Ω single-ended load, terminated to ground. 2. Guaranteed by design 10.This value is measured after the resistor network at the SDI outputs shown in Figure 2. 3. Inferred or correlated value 11.Typical PECL values 4. Evaluated using test setup Figure 1a. 12.6σ additive intrinsic jitter contribution based on pathological input signal 5. Evaluated using test setup Figure 1b. 13.This is the lapsed time between valid parallel TRS input to valid serial output 6. Evaluated using test setup Figure 1c. DC ELECTRICAL CHARACTERISTICS VCC = 5V, VEE = 0V, TA = 0°C to 85°C, unless otherwise specified. Serial Data Rate = 270Mb/s, Parallel Data Rate = 27Mb/s, fPCLK = 27MHz PARAMETER CONDITIONS Positive Supply Voltage SYMBOL MIN TYP MAX UNITS VCC + 4.75 + 5.00 + 5.25 V TEST LEVEL Supply Current - Receive Mode VCC = 5.25V ICC - 150 - mA 1 Supply Current - Transmit Mode VCC = 5.25V ICC - 130 - mA 1 Power Consumption - Receive Mode VCC = 5.25V PD - 750 - mW 3 Power Consumption - Transmit Mode VCC = 5.25V PD - 650 - mW 3 Logic Inputs - Low VCC = 5.25V VIL VEE - 0.8 V 2 Logic Inputs - High VCC = 4.75V VIH 2.0 - VCC V 2 Logic Outputs - Low VCC = 5.25V VOL VEE - 0.5 V 2 Logic Outputs - High VCC = 4.75V VOH 2.4 - VCC V 2 3 522 - 06 - 02 GS7000 MAX SYMBOL BELDEN 8281 CABLE DATA GS9028 CABLE DRIVER DATA TEKTRONIX GigaBERT 1400 TRANSMITTER EB7000 BOARD TEKTRONIX TDS 820 SCOPE CLOCK GS7000 TRIGGER Fig. 1a Test Setup for Jitter Measurements TEKTRONIX VIDEO SlGNAL GENERATOR BELDEN 8281 CABLE VIDEO STREAM WITH EDH EB9021 EDH ERROR COUNTER EB7000 BOARD Fig. 1b Test Setup for Error-Free Cable Length BELDEN 8281 CABLE BELDEN 8281 CABLE HP 4195A NETWORK ANALYSER HP 4195A NETWORK ANALYSER EB7000 BOARD Fig. 1c Test Setup for Return Loss Measurements VCC 220 CD VCC 10k 7.5 10u 33 MODE 7.5 PARALLEL CLOCK OUT VCC 100n 825 10u 100n 100n NC VSS VDD NC DIN0 PCLKOUT NC SMPTE CD SDO VCC3 NC NC 39 DOUT0 38 DOUT1 37 DOUT2 36 DOUT3 35 34 DOUT4 33 DOUT5 32 DOUT6 31 DOUT7 30 DOUT8 29 DOUT9 28 LOCK 27 NC DIN1 DIN2 DIN3 DIN4 GS7000 DIN5 DIN6 DIN7 DIN8 PARALLEL DATA OUTPUTS VCC 220 LOCK 10k VCC 100n 100n 14 15 16 17 18 19 20 21 22 23 24 25 26 100n All resistors in ohms, all capacitors in farads, unless otherwise shown. NC Rx/Tx EQ VEE2 VCC2 SDI SDI VCC1 C2 NC C1 H PCLKIN DIN9 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 SDO NC 52 51 50 49 48 47 46 45 44 43 42 41 40 PARALLEL DATA INPUTS Rx/Tx PARALLEL CLOCK IN VCC 33 10p 10u 10u SERIAL DIGITAL IN VCC EQ Fig. 2 Test Circuit (Half Duplex Operation) 4 522 - 06 - 02 VCC 10p 825 VEE3 SERIAL DIGITAL OUT VCC VEE1 SERIAL DIGITAL OUT 10u NC VEE3 SDO SDO VCC3 CD SMPTE NC NC PCLKOUT VDD VSS NC PIN CONNECTIONS 39 38 37 36 35 34 33 32 31 30 29 28 27 NC DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 DOUT8 DOUT9 LOCK NC NC VEE1 C1 C2 VCC1 SDI SDI VCC2 PCLKIN VEE2 EQ Rx/Tx NC 52 51 50 49 48 47 46 45 44 43 42 41 40 1 2 3 4 5 GS7000 6 TOP VIEW 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 GS7000 NC DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DIN8 DIN9 H NC PIN DESCRIPTIONS NUMBER SYMBOL TYPE MODE DESCRIPTION 1, 13, 14, 26, 27, 39, 40, 44, 45, 52 NC - - 2-11 DIN(0,9) I Tx 27Mb/s Parallel Data Input 12 H O Rx Indicates the presence of active video. Low after SAV ID and high after EAV ID 15 VEE1 - - Most negative supply for analog circuits 16, 17 C1, C2 - - External 100nF Loop Filter Capacitor Connection 18 VCC1 - - Most positive supply for analog circuits 19, 20 SDI, SDI I Rx 21 VCC2 - - 22 PCLKIN I Tx 23 VEE2 - - 24 EQ I Rx 25 Rx/Tx I - 28 LOCK O Rx/Tx 29 - 38 DOUT(9,0) O Rx No Connect - Connected to Ground. Differential Serial Data Input Most positive supply for PECL circuits 27MHz External Clock Input Most negative supply for PECL circuits Equalizer control. LOW = EQ on, HIGH = EQ bypassed. Receiver/Transmitter Mode Control Input Signal Lock Indication Output. Goes HIGH approximately 38 µs after valid parallel data occurs. 27Mb/s Parallel Data Output 5 522 - 06 - 02 GS7000 PIN DESCRIPTIONS NUMBER SYMBOL TYPE MODE DESCRIPTION 41 VSS - - Most negative supply for CMOS circuits 42 VDD - - Most positive supply for CMOS circuits 43 PCLKOUT O Rx 46 SMPTE I Rx/Tx NRZI de/encoding and SMPTE de/scrambling control. LOW = NRZI and SMPTE mode on, HIGH = NRZI and SMPTE mode disabled. 47 CD O Rx/Tx Indicates loss of carrier. Low when carrier is present and high when carrier is lost. 48 VCC3 - - 49, 50 SDO, SDO O Tx 51 VEE3 - - 27MHz Clock Output Most positive supply for Analog and PECL Circuits Differential Serial Data Output Most negative supply for Analog and PECL Circuits INPUT / OUTPUT CIRCUITS VDD VDD TO INTERNAL STRUCTURES ESD IN ESD OUT TO INTERNAL STRUCTURES VEE VEE Fig. 3 SDI, SDI Fig. 4 SDO, SDO VDD VDD ESD ESD TO INTERNAL STRUCTURES TO INTERNAL STRUCTURES TTL-IN VEE VSS Fig. 5 DIN(0,9), PCLKIN, EQ, Rx/Tx, SMPTE Fig. 6 DOUT(0,9), H, LOCK, CD 6 522 - 06 - 02 OUT VDD ESD TO INTERNAL STRUCTURES OUT GS7000 VEE Fig. 7 PCLKOUT (VCC = 5 V, TA = 25 °C unless otherwise shown) DATA TO FOLLOW DATA TO FOLLOW Fig. 8 Output PCLK Jitter vs. Cable Length Fig. 9 815 0 810 -10 RETURN LOSS (dB) SERIAL DATA OUTPUT LEVEL (mV) TYPICAL PERFORMANCE CURVES 805 800 795 270MHz -20 -30 135MHz -40 790 0 10 20 30 40 50 60 70 80 -50 90 0.05 GHz 1 GHz FREQUENCY (GHz) TEMPERATURE (˚C) Fig. 10 Serial Data Output Level vs. Temperature Fig. 11 Input Return Loss 7 522 - 06 - 02 0 0 AMPLITUDE (dB) RETURN LOSS (dB) 270MHz -20 135MHz -30 600kHz -3 -6 -40 -50 0.05 1k 1 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (GHz) Fig. 12 Output Return Loss Fig. 13 Loop Bandwidth J1 J2 J0.5 54MHz 1.97GHz 270MHz 540MHz Impedances normalized to 50 W -J0.5 -J2 -J1 Fig. 14 Serial Data Output Fig. 15 Input Impedance J1 800 J2 Rx J0.5 700 600 1.97GHz POWER (mW) GS7000 -10 54MHz 270MHz Tx 500 400 300 200 540MHz 100 Impedances normalized to 50 W -J0.5 0 0 -J2 10 20 30 40 50 60 TEMPERATURE (˚C) -J1 Fig. 16 Output Impedance Fig. 17 Power vs. Temperature 8 522 - 06 - 02 70 80 90 RECEIVER OPERATION Rx/Tx SMPTE GS7000 OPERATING MODE 0 1 0 SMPTE 259M Receiver (Equalizer on, SMPTE / NRZI on) 1 1 0 SMPTE 259M Receiver with equalizer bypassed 0 1 1 Receiver function with NRZI and SMPTE Descrambler disabled, equalizer enabled. 1 1 1 Receiver function with NRZI and SMPTE Descrambler disabled, equalizer bypassed. The diagram below depicts the active portions of the chip when operating in Receiver mode (Rx/Tx set to logic high level) with the equalizer, descrambling and NRZI functions all active. In this mode of operation the output of the LOCK pin is logic high whenever the receiver has successfully locked to the input serial bit stream. The output H is set low after the SAV ID and is set high after the EAV ID when these sequences are identified in the incoming bit stream. Note the function available called "Equalizer Control" (EQ). Setting EQ to a logic HIGH level shuts off the equalization function of the device for implementations where the length of cable to be equalized is very short (less than 10 m). It is possible to turn off the NRZI and SMPTE Descrambler function by setting SMPTE HIGH. When operating in this mode, the output of H, will be either "1" or "0" (indeterminate). SMPTE NRZI ENCODER SCRAMBLER DIN (0,9) C1 C2 SDO SDO P to S 10 f/10 SIGNAL LOCK DETECT PLL PCLKOUT H PCLKIN MUX DOUT(0,9) LOCK CD TRS DETECTOR S to P 10 DESCRAMBLER NRZI DECODER SLICER EQUALIZER SDI SDI Rx/Tx SMPTE EQ Fig. 18 Functional Block Diagram (Receiver Mode) TRANSMITTER OPERATION EQ Rx/Tx SMPTE GS7000 OPERATING MODE X 0 0 SMPTE 259M Transmitter X 0 1 Transmitter function with NRZI and SMPTE Scrambler disabled The diagram below depicts the active portions of the chip when operating in Transmitter mode (Rx/Tx set to logic low level), with the NRZI and scrambling functions active. Note that similar to receive mode above, it is possible to turn off the NRZI and SMPTE Scrambler by setting SMPTE high. 9 522 - 06 - 02 GS7000 EQ SMPTE NRZI ENCODER SCRAMBLER DIN (0,9) C1 C2 SDO SDO P to S GS7000 10 f/10 SIGNAL LOCK DETECT PLL PCLKOUT LOCK CD H PCLKIN MUX DOUT(0,9) TRS DETECTOR S to P 10 NRZI DECODER DESCRAMBLER SLICER SDI EQUALIZER SDI Rx/Tx SMPTE EQ Fig. 19 Functional Block Diagram (Transmitter Mode) DIAGRAMS The figure below describes the timing relationship between the outputs of the GS7000 when operating in receiver mode. PCLKOUT ... XXX XXX 3FF 000 000 XXX XXX XXX XXX XXX ... XXX XXX 3FF 000 000 XXX XXX XXX DOUT(n) EAV ID SAV ID H ... Fig. 20 Timing Diagram For Parallel Outputs, PCLKOUT and H The figure below describes the relationship between the output parallel clock and the output parallel data. The output parallel clock rising edge is centered on the output data within ±5 ns. WORD CENTER 5 ns 5 ns DOUT(n) PCLKOUT Fig. 21 Receiver Parallel Clock Alignment 10 522 - 06 - 02 The figure below describes the relationship between the input parallel clock and the input parallel data. The input parallel data must be stable for 4ns prior to the rising edge of the PCLKIN (setup time), and for 4 ns following the rising edge of the PCLKIN (hold time). tHOLD = 4ns tSETUP = 4ns GS7000 DIN(n) PCLKIN Fig. 22 Transmitter Setup and Hold Time TYPICAL APPLICATION CIRCUITS VCC VCC1 GND VCC GS9024 VCC All resistors in ohms, all capacitors in farads, unless otherwise shown. 75 10n 475 220 EQ Rx/Tx NC NC DIN1 VEE2 DIN0 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DIN8 PCLKIN NC 52 VEE3 51 50 SDO 49 SDO 48 VCC3 47 CD 46 SMPTE 45 NC 44 NC 43 PCLKOUT 42 VDD 41 VSS 40 NC NC OEM VCC2 1 DOUT0 VCC GS7000 SDI DOUT1 10n CD-ADJ DOUT2 DOUT GND SDI DOUT3 37.5 DIN VCC1 DOUT4 75 VCC DOUT DIN C2 DOUT5 10n CD 5 4 3 2 C1 DOUT6 75 75 VCC 6 VEE1 DOUT8 10n 10n AGC GND TRISTATE 9 8 7 NC DOUT9 AGC 14 15 VCC 100n 16 17 100n 18 75 75 19 20 VCC 21 VCC 22 100n 23 475 24 VCC 25 26 2k VCC NC 100p VCC H 10n DIN9 NC 13 12 11 10 DOUT7 10u LOCK 100n SSI-CD 27 28 29 30 31 32 33 34 35 36 37 38 39 LOCK 1u 10k 10n VCC 220 100n CD 10k VCC MODE 33 PCLK OUT VCC 10p 100n PARALLEL DATA OUTPUTS Typical Receiver Application Circuit with External Equalizer 11 522 - 06 - 02 PARALLEL DATA IN NC DIN0 2 1 DIN1 DIN2 DIN3 5 4 3 DIN4 DIN5 DIN6 DIN7 DIN8 H DIN9 7 6 NC VEE1 VEE3 C1 SDO C2 SDO VCC1 VCC3 SDI CD GS7000 SDI SMPTE VCC2 NC PCLKIN NC VEE2 PCLKOUT NC VCC 220 75 OUT IN OUT IN NC/GND 75 75 VEE VCC 220 MODE CD All resistors in ohms, all capacitors in farads, unless otherwise shown. 10u 10µ 7.5 825 GS7000 7.5 10µ SDO 825 75 All resistors in ohms, all capacitors in farads, unless otherwise shown. Typical Transmitter Application Circuit - Single Ended Output Operation (as above with changes shown) 12 522 - 06 - 02 8.2n 1u OUT VCC 10k Typical Transmitter Application Circuit with Cable Driver SDO 1u 59 VCC 100n 8.2n 75 VCC LOCK 75 RSET GS9028 100n 27 28 29 30 31 32 33 34 35 36 37 38 39 10k VCC OUT CC NC DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 NC DOUT7 VSS DOUT8 VDD Rx/Tx DOUT9 EQ 52 51 50 10u 49 10u 48 VCC 47 100n 46 45 44 43 42 41 40 V VCC 75 10u 100n NC LOCK 14 15 100n 16 VCC 17 18 VCC 100n 10k 19 10k 20 VCC 100n 21 22 23 10p 24 PARALLEL CLOCK IN 25 26 33 VCC NC GS7000 NC 13 12 11 10 9 8 100n VCC VCC 220 10k VCC CD VCC VCC 33 All resistors in ohms, all capacitors in farads, unless otherwise shown. MODE VCC 100n 10u 10p 100n VCC GS7000 100n NC VSS VDD NC PCLKOUT NC CD SMPTE SDO VCC3 SDO NC DIN6 NC 39 DOUT0 38 DOUT1 37 DOUT2 36 DOUT3 35 DOUT4 34 DOUT5 32 33 D DIN7 DOUT7 NC DIN0 DIN1 DIN2 DIN3 DIN4 GS7000 DIN5 DIN8 PARALLEL DATA OUT 31 30 DOUT8 29 DOUT9 28 LOCK 27 NC VCC 220 NC Rx/Tx EQ PCLKIN VEE2 VCC2 SDI SDI VCC1 C2 C1 H VEE1 DIN9 NC PARALLEL CLOCK OUT OUT6 NC 100n 14 15 16 17 18 19 20 21 22 23 24 25 26 100n 1 2 3 4 5 6 7 8 9 10 11 12 13 VEE3 52 51 50 49 48 47 46 45 44 43 42 41 40 100n VCC 10k LOCK VCC SERIAL DIGITAL INPUT 10u VCC 10u EQ Typical Receiver Application Circuit - Unbalanced Input Operation 13 522 - 06 - 02 PACKAGE DIMENSIONS 17.20 BSC 14.00 BSC 14 ±2˚ 0.40 MIN GS7000 0˚ MIN 17.20 BSC 14.00 BSC 0.13 MIN RADIUS 7˚ MAX 0˚ MIN 14 ±2˚ 0.88 ±0.15 0.13 MIN. RADIUS 1.60 REF 52 pin MQFP 1.00 BSC 0.50 MAX 0.35 MIN CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DOCUMENT IDENTIFICATION REVISION NOTES: PRELIMINARY DATA SHEET The product is in a preproduction phase and specifications are subject to change without notice. Removed figure 8. GENNUM CORPORATION MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 GENNUM JAPAN CORPORATION C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku Tokyo 168-0081, Japan Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839 GENNUM UK LIMITED Centaur House, Ancells Bus. Park, Ancells Rd, Fleet, Hants, England GU13 8UJ Tel. +44 (0)1252 761 039 Fax +44 (0)1252 761 114 Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. © Copyright April 1999 Gennum Corporation. All rights reserved. Printed in Canada. 522 - 06 - 02 14