GENNUM GS7005

PRO-LINX ™ GS7005
Complete Serial Digital Video Receiver
DATA SHEET
DESCRIPTION
• SMPTE 259M-C compliant
The GS7005 is a BiCMOS integrated circuit capable of
operating as a complete 270Mb/s Serial Digital Video
receiver. The GS7005 provides a complete serial digital
video receive solution while consuming only 750mW.
• fully integrated 270 Mb/s SDI receiver
• integrated cable equalization (100m Belden 8281 typical)
• low power consumption (750mW typical)
• operates from 0°C to 85°C
• small footprint with minimal external components
• Lock and Carrier Detect output indications
• H timing signal output
• SMPTE descrambler and NRZI decoder may be
disabled for DVB - ASI applications
The serial data input accepts SMPTE 259M-C compliant
signals. An on-chip by-passable equalizer typically provides 100m of co-axial cable equalization. The clock
recovery is performed on chip with minimal external
components. The incoming serial data is decoded using an
NRZI decoder and SMPTE descrambler to provide SMPTE
125M compliant 27Mb/s parallel data outputs and clock.
• ease of design use and adjustment free operation
ORDERING INFORMATION
APPLICATIONS
Limited space, low power SMPTE 259M-C or generic
270Mb/s serial to parallel interfaces; DVB-ASI 270Mb/s
receive interface; broadcast quality uncompressed video
interface for industrial and professional video equipment
such as video editing workstations.
PART NUMBER
PACKAGE
TEMPERATURE
GS7005 - CQT
52 pin MQFP
0°C to 85°C
GS7005 - CTT
52 pin MQFP Tape
0°C to 85°C
C1 C2
LOCK
CD
SIGNAL
LOCK
DETECT
PLL
f/10
PCLKOUT
H
MUX
TRS
DETECTOR
SDI
SDI
EQUALIZER
EQ
SLICER
S to P
DOUT[9:0}
10
NRZI
DECODER
DESCRAMBLER
SMPTE
BLOCK DIAGRAM
Revision Date: January 2001
Document No. 522 - 14 - 06
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected]
www.gennum.com
GS7005
FEATURES
ABSOLUTE MAXIMUM RATINGS
PARAMETER
VALUE
Supply Voltage
5.5V
Input Voltage Range (any input)
GND < VIN < VCC
10mA
Power Dissipation (VCC = 5.25V)
1W
Maximum Die Temperature
GS7005
DC Input Current (any one input)
125°C
Operating Temperature Range
0°C <= TA <= 85°C
-65°C <= TS <= 150°C
Storage Temperature Range
Lead Temperature (soldering 10s)
260°C
DC ELECTRICAL CHARACTERISTICS
VCC = 5V, TA = 25°C, unless otherwise specified.
Serial data rate = 270Mb/s, Parallel Data Rate = 27Mb/s, ƒPCLK = 27MHz
PARAMETER
Positive Supply Voltage
Power Consumption
SYMBOL
VCC
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
TEST LEVEL
Operating
range
4.75
5.00
5.25
V
6
P
VCC = 5.25V
-
750
-
mW
5
Supply Current
ICC
VCC = 5.25V
-
140
-
mA
1
Logic Inputs - Low
VIL
VCC = 5.25V
-
-
0.8
V
6
Logic Inputs - High
VIH
VCC = 4.75V
2
-
-
V
6
Logic Outputs - Low
VOL
VCC = 5.25V
-
-
0.5
V
1
Logic Outputs - High
VOH
VCC = 4.75V
2.4
-
-
V
1
TEST LEVELS
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using
correlated test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1,2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.
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AC ELECTRICAL CHARACTERISTICS
VCC = 5V, TA = 25°C, unless otherwise specified in ‘conditions’
Serial data rate = 270Mb/s, Parallel Data Rate = 27Mb/s, ƒPCLK = 27MHz
PARAMETER
Parallel Data - Rise/Fall Time
SYMBOL
tR/F_DOUT
PCLK Rise/Fall Time
Input Return Loss
CL = 20pF
tD
MIN
TYP
MAX
UNITS
NOTE
S
TEST
LEVEL
1.0
-
6.0
ns
1
4, 7
-
-
±5
ns
2, 3
4, 7
1
4, 7
tR/F_PCLKOUT
CL = 20pF
0.5
-
3.0
ns
LOSSIN
75Ω match
-
17
-
dB
7
5MHz to 270MHz
Asynchronous Lock Time
tLOCK_ASYNC
-
-
250
ms
4
1
Synchronous Lock Time
tLOCK_SYNC
-
-
10
µs
5
1
Pathological Input
-
0.35
-
U.I.
6
7
Pseudorandom
Input
-
800
-
ps p-p
Pathological Input
-
1000
-
ps p-p
Pseudorandom
Input
-
100
-
m
75
100
-
m
Input Jitter Tolerance
Output PCLK Jitter
tJ_SI
tJ_PCLKOUT
Error Free Cable Length
Pathological Input
1
6
7
7
6, 7
1
NOTES
1. Rise/Fall time is defined as the time for the signal to rise from 20% to 80% of the specified p-p value, or to fall from 80% to 20% of the
specified value.
2. Refer also to Figure 10.
3. This is the time difference between the rising edge of PCLKOUT and the centre of the bit period.
4. This is the time delay between a valid serial TRS signal on the input to the moment valid data appears on the parallel outputs.
5. This is the time for the PLL to re-lock when video streams are switched during the vertical blanking interval in accordance with SMPTE
RP168-1993. The two streams may be 180° out of phase with respect to one another, but pixel aligned.
6. This pathological pattern is defined in SMPTE RP178-1996, paragraphs 4.1 and 4.3.
7. "Error free" is defined as no single bit errors over a period of 10 minutes, using Belden 8281 Cable and 75Ω connections. The MIN
value is fully tested and the TYP value is based on using the EB7005 Evaluation Board.
TEST LEVELS
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated
test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1,2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.
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GS7005
PCLK Rising Edge to DOUT(N) Centre
CONDITIONS
TEST SETUP
DATA
DATA
BELDEN 8281
CABLE
EB7005
BOARD
GS7005
TEKTRONIX
GigaBERT
1400
TRANSMITTER
GS9028
CABLE
DRIVER
TEKTRONIX
TDS 820
SCOPE
CLOCK
TRIGGER
Fig. 1a Test Setup for Jitter Measurements
TEKTRONIX
VIDEO SlGNAL
GENERATOR
VIDEO STREAM
WITH EDH
BELDEN 8281
CABLE
EB7005
BOARD
EB9021
EDH ERROR
COUNTER
Fig. 1b Test Setup for Error-Free Cable Length
HP 4195A
NETWORK
ANALYSER
BELDEN 8281
CABLE
EB7005
BOARD
Fig. 1c Test Setup for Return Loss Measurements
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GND
GND
RSVD1
RSVD1
VCC3
CD
SMPTE
RSVD0
RSVD0
PCLKOUT
VDD
GND
GND
PIN CONNECTIONS
39
38
37
36
35
34
33
32
31
30
29
28
27
GND
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
DOUT8
DOUT9
LOCK
GND
GND
GND
C1
C2
VCC1
SDI
SDI
VCC2
RSVD0
GND
EQ
RSVD1
GND
52 51 50 49 48 47 46 45 44 43 42 41 40
1
2
3
4
5
GS7005
6
TOP VIEW
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24 25 26
GS7005
GND
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
H
GND
NOTE: RSVD = Reserved
PIN DESCRIPTIONS
NUMBER
SYMBOL
TYPE
DESCRIPTION
1, 13, 14, 26, 27,
39, 40, 52
GND
-
Connect to Ground.
2-11, 22, 44, 45
RSVD0
-
Connect to Ground.
12
H
O
H Indication. HIGH after EAV ID and LOW after SAV ID.
15
GND
-
Ground for analog blocks of the device.
16, 17
C1, C2
-
External 100nF loop filter capacitor connection.
18
VCC1
-
Power supply for analog blocks of the device.
19, 20
SDI, SDI
I
Differential Serial Data Input
21
VCC2
-
Power supply for PECL blocks of the device.
23
GND
-
Ground for PECL blocks of the device.
24
EQ
I
Equalizer Control; LOW = EQ on, HIGH = EQ bypassed.
25, 49, 50
RSVD1
-
Connect to VCC.
28
LOCK
O
Signal Lock Indication Output. Goes HIGH approximately 38µs after valid parallel data
occurs.
29-38
DOUT[9:0]
O
27Mb/s Parallel Data Outputs.
41
GND
-
Ground for CMOS blocks of the device.
42
VDD
-
Power supply for CMOS blocks of the device.
43
PCLKOUT
O
27MHz Clock Output.
46
SMPTE
I
NRZI decoding and descrambling control.
LOW = NRZI and SMPTE mode on. HIGH = NRZI and SMPTE mode disabled.
47
CD
O
Carrier Detect. Active LOW. Goes LOW when carrier is detected and high when carrier is
lost.
48
VCC3
-
Power supply for Analog and PECL blocks of the device.
51
GND
-
Ground for analog and PECL blocks of the device.
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INPUT / OUTPUT CIRCUITS
VDD
ESD
GS7005
IN
TO INTERNAL
STRUCTURES
GND
Fig. 2 SDI, SDI
VDD
ESD
TO INTERNAL
STRUCTURES
OUT
GND
Fig. 3 DOUT[9:0], H, LOCK, CD, PCLKOUT
VDD
ESD
TO INTERNAL
STRUCTURES
TTL-IN
GND
Fig. 4 EQ, SMPTE
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TYPICAL PERFORMANCE CURVES (VCC = 5V, TA = 25°C unless otherwise shown)
J1
J2
0
J0.5
270MHz
GS7005
RETURN LOSS (dB)
-10
-20
54MHz
135MHz
-30
1.97GHz
270MHz
540MHz
-40
Impedances
normalized
to 50W
-50
0.05 GHz
1 GHz
-J0.5
-J2
FREQUENCY (GHz)
-J1
Fig. 5 Input Return Loss
Fig. 7 Input Impedance
800
700
600
POWER (mW)
AMPLITUDE (dB)
0
600kHz
-3
500
400
300
200
-6
100
0
1k
10k
100k
1M
0
10M
FREQUENCY (Hz)
10
20
30
40
50
60
70
80
90
TEMPERATURE (˚C)
Fig. 6 Loop Bandwidth
Fig. 8 Power vs. Temperature
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RECEIVER OPERATION
SMPTE
GS7005 Operating mode
0
0
SMPTE 259M Receiver (Equalizer ON, SMPTE / NRZI Descrambler enabled).
1
0
SMPTE 259M Receiver with equalizer bypassed.
0
1
Receiver function with equalizer enabled and NRZI and SMPTE Descrambler disabled.
1
1
Receiver function with equalizer bypassed and NRZI and SMPTE Descrambler disabled.
GS7005
EQ
If external equalization is performed prior to this device,
bypass the equalization control function (EQ) by setting it
HIGH.
The output of the LOCK pin is logic high approximately
38µs after the receiver has successfully locked to the input
serial bit stream. The output H is set low after the SAV ID
and is set high after the EAV ID when these sequences are
identified in the incoming bit stream.
To turn off the NRZI and SMPTE Descrambler function, set
SMPTE HIGH. When operating in this mode, the output of H
is either "1" or "0" (indeterminate).
DIAGRAMS
The figure below shows the timing relationship between the outputs of the GS7005.
...
PCLKOUT
DOUT[9:0]
XXX
XXX
3FF
000
000
SAV ID
XXX
XXX
XXX
XXX ...
XXX
XXX
3FF
000
000
EAV ID
XXX
XXX
H
...
Fig. 9 Timing Diagram for Parallel Outputs, PCLKOUT, and H
The figure below shows the relationship between the parallel clock and the parallel data outputs. The rising edge of the
parallel clock is within ±5ns of the centre of the data.
WORD CENTRE
5ns
5ns
DOUT[9:0]
PCLKOUT
Fig. 10 Parallel Clock Alignment
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DETAILED DESCRIPTION
signal by applying the same algorithm to the received
signal. For data structures that do not require descrambling and NRZI-NRZ conversion, bypass this block
by setting the SMPTE pin to logic HIGH.
The main functional blocks of the GS7005 are:
1. PECL input buffer
2. Fixed Gain Equalizer
5. PLL, MUX and f/10
3. Slicer
4. NRZI Decoder & SMPTE Descrambler
5. TRS Detector
6. Signal Lock Detect
7. Serial to Parallel Convertor
The PLL self-centres the VCO to approximately 29MHz
when there are no input data transitions. This allows the PLL
to lock when a valid signal within the lock range is applied.
However, if the GS7005 detects a spurious input with
random data transitions, the centering function of the VCO
is inhibited. This causes the VCO control voltage to drift to a
low clamp level resulting in a VCO frequency of 22MHz. To
prevent this “latch-up” condition implementation of a high
impedance (1MΩ) bleed resistor across the C1 and C2
(loop filter, pins 16 and 17) is recommended. Due to the
large resistance value, the effect on IJT is negligible (see
Figure 11).
Refer to the Functional Block Diagram on the front page of
this data sheet.
1. PECL INPUT BUFFER
This differential input buffer features a built-in load
termination for the incoming SDI signal. The load is
characterized as 75Ω over a wide frequency range and is
made up of an internal fixed resistor and current source.
2. FIXED GAIN EQUALIZER
The Fixed Gain Equalizer stage is used to compensate the
frequency dependent loss of the SDI signal through co-axial
cable. The SDI signal is connected to the input pins (SDI/
SDI) either differentially or single ended. The input signal
passes through a fixed gain equalizing stage whose
frequency response closely matches the inverse cable loss
characteristic. The equalizer typically provides 100m of
coaxial cable equalization. The frequency response is
optimized for maximum cable length. For short cable
lengths (<10m), bypass the equalizing stage by setting the
EQ control pin to a logic HIGH level. If an external equalizer
is used, bypass the internal equalizer of the GS7005 to
avoid over-equalization (see Figure 12).
6. TRS DETECTOR
The TRS Detector detects the TRS headers (EAV and SAV).
It consists of a word-counter, bit-counter and control statemachine. The bit-counter is reset by either the decoded
data or the output of the state-machine. In a normal case,
the state-machine output is LOW. The reset of the bit
counter is active LOW so that the bit-counter will be started
when the data is HIGH. The detection of a valid TRS header
is indicated by a level change of the H-signal pin.
7. SIGNAL LOCK DETECT
When there are no input data transitions, the CD pin goes to
a HIGH logic level and forces the VCO to the centre
frequency as described in section 5, PLL, MUX, and f/10.
This output can be used to control an external transistor
and LED. When there are input data transitions (valid or
invalid), the CD pins goes to a LOW logic state.
3. POST EQUALIZATION SLICER
The Post Equalization Slicer stage slices the equalized
signal, thereby eliminating any DC offset due to the AC
coupling requirement of the SDI signal. Using a differential
comparator, the received signal voltage is compared to a
midway voltage, known as the baseline or the slicing level.
The sliced signal is then applied to the NRZI/SMPTE
Decoder/Descrambler and the PLL MUX.
The locking state of the PLL is indicated by the output
LOCK signal being set to a logical HIGH level. This pin
however, may have periodic transitions to a LOW logic state
of 64µs maximum duration even though the device is
properly locked. The parallel data signal integrity is not
affected under these conditions. Therefore, the LOCK pin
should not be used as a logic control signal if a steady level
is required. The output voltage remains in a logic HIGH
state for a sufficient period and can be used to drive visual
indicators such as LEDs.
4. NRZI DECODER & SMPTE DESCRAMBLER
To comply with the the ANSI/SMPTE 259M standard, use a
scrambled, polarity free NRZI code. The polynomial
9
4
generator for the scrambler is G1(X) = X +X +1. The NRZI
code is produced by a second polynomial, G2(X) = X+1.
The NRZI Decoder and SMPTE Descrambler blocks within
the GS7005 regenerate the original NRZ unscrambled
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GS7005
The PLL clock recovery circuitry provides an internal,
synchronous 270MHz clock. The 27MHz parallel data clock
is derived from the serial clock through a resettable
frequency divider. To synchronize the parallel clock signal,
set the frequency divider to the initial state at the same time
the state machine has detected the Timing Reference
Signal (TRS).
8. SERIAL TO PARALLEL CONVERTOR
GS7005
The final function of the GS7005 is the serial-to-parallel
conversion. The output signals of the receiver are ten data
signals and one clock signal. The shift register is filled by
the serial data and read out at a positive edge of the readout signal. After parallel read out of the shift register, the
parallel data is sampled with the negative edge of the
27MHz clock to achieve synchronization.
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APPLICATION CIRCUITS
VCC
220
VCC
33
10k
CD
VCC
MODE
VCC
VCC
100n
VCC
100n
10p
100n
10µ
GS7005
GND
VDD
GND
RSVD0
RSVD0
PCLKOUT
RSVD0
CD
SMPTE
VCC3
RSVD1
GND
RSVD1
GND
RSVD0
RSVD0
RSVD0
RSVD0
GS7005
RSVD0
RSVD0
RSVD0
RSVD0
PARALLEL
CLOCK OUT
GND 39
DOUT0 38
DOUT1 37
DOUT2 36
DOUT3 35
DOUT4 34
DOUT5 33
DOUT6 32
DOUT7 31
DOUT8 30
29
DOUT9
28
LOCK
27
GND
PARALELL
DATA OUT
VCC
GND
RSVD1
EQ
GND
VCC2
SDI
SDI
VCC1
C2
C1
GND
GND
H
RSVD0
RSVD0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
GND
52 51 50 49 48 47 46 45 44 43 42 41 40
220
100n
100n
100n
14 15 16 17 18 19 20 21 22 23 24 25 26
1M
VCC
10µ
SERIAL DIGITAL
INPUT
LOCK
10k
VCC
VCC
RSVD = Reserved.
10µ
EQ
All resistors in ohms,
all capacitors in farads,
unless otherwise shown.
Fig. 11 Application Circuit - Unbalanced Serial Input Operation
VCC
VCC
VCC1
VCC
75
10n
475
OUTPUT EYE
MONITOR
220
GND
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
H
RSVD0
GND
EQ
RSVD1
GND
GND
OEM
GS9024
DOUT0
VCC
VCC2
CD 47
46
SMPTE
45
RSVD0
44
RSVD0
43
PCLKOUT
42
VDD
41
GND
40
GND
DOUT1
CD-ADJ
GS7005
SDI
DOUT2
DOUT
GND
GND 52
GND 51
RSVD1 50
RSVD1 49
48
V
27 28 29 30 31 32 33 34 35 36 37 38 39
LOCK
1µ
10k
10n
CD
VCC
100n
10k
VCC
CC3
SDI
DOUT3
DIN
VCC1
DOUT4
10n
DOUT
1
C2
DOUT5
VCC
CD
DIN
2
C1
DOUT6
VCC
75
37.5
AGC
GND TRISTATE
75
10n
AGC
DOUT7
75
10n
5 4 3
GND
GND
VCC
SERIAL
DIGITAL INPUT
10n
GND
DOUT8
14
15
VCC
16
100n 17
75
75
18
19
100n
20
VCC
21
VCC
22
100n
23
475
24
VCC
25
26
2k
VCC
1M
DOUT9
10n
100n
RSVD0
GND
13 12 11 10 9 8 7 6
RSVD0
220
10µ
LOCK
100n
SSI-CD
GND
PARALLEL DATA OUTPUTS
MODE
33
PCLK OUT
10p
VCC
RSVD = Reserved.
All resistors in ohms,
all capacitors in farads,
unless otherwise shown.
100n
Fig. 12 Typical Application Circuit with External Equalizer
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PACKAGE DIMENSIONS
17.20 BSC
14.00 BSC
14 ±2˚
7˚ MAX
0˚ MIN
2.7
GS7005
17.20
BSC
14.00
BSC
0.40 MIN
0.13 MIN
0˚ MIN RADIUS
14 ±2˚
0.88
±0.15
0.13 MIN.
RADIUS
1.60
REF
1.00 BSC
0.50 MAX
0.35 MIN
2.67
±0.08
3.00 MAX
0.18
±0.05
0.25 MAX
0.10 MIN
All dimensions are in millimetres.
52 pin MQFP
BSC = Basic or nominal
CAUTION
ELECTROSTATIC
SENSITIVE DEVICES
REVISION NOTES:
Added label to package dimension drawing to show package
thickness and included the third view; Added information to
section 5, PLL, MUX and f/10; Removed Figures 5 and 6 “Data to Follow”; Added resistor to Figures 11 and 12; Added
to Package Dimensions legend.
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
DATA SHEET
The product is in production. Gennum reserves the right to make
changes at any time to improve reliability, function or design, in order to
provide the best product possible.
GENNUM CORPORATION
MAILING ADDRESS:
P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
SHIPPING ADDRESS:
970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
For the latest product information, visit www.gennum.com.
GENNUM JAPAN CORPORATION
C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku
Tokyo 168-0081, Japan
Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839
GENNUM UK LIMITED
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
© Copyright November 1999 Gennum Corporation. All rights reserved. Printed in Canada.
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