SN74AUC2G00 DUAL 2-INPUT POSITIVE-NAND GATE www.ti.com SCES440C – MAY 2003 – REVISED JANUARY 2007 FEATURES • • • • • • • • Available in the Texas Instruments NanoFree™ Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub-1-V Operable Max tpd of 1.2 ns at 1.8 V DCT PACKAGE (TOP VIEW) • Low Power Consumption, 10 µA at 1.8 V ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DCU PACKAGE (TOP VIEW) 1A 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A 1A 1B 2Y GND 1 2 3 8 7 6 4 5 YEP OR YZP PACKAGE (BOTTOM VIEW) VCC 1Y 2B 2A GND 2Y 1B 1A 4 5 3 6 2 7 1 8 2A 2B 1Y VCC See mechanical drawings for dimensions. DESCRIPTION/ORDERING INFORMATION This dual 2-input positive-NAND gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC2G00 performs the Boolean function Y = A ⋅ B or Y = A + B in positive logic. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING (2) NanoFree™ – WCSP (DSBGA) Reel of 3000 0.23-mm Large Bump – YZP (Pb-free) SN74AUC2G00YZPR _ _ _UA_ SSOP – DCT Reel of 3000 SN74AUC2G00DCTR U00_ VSSOP – DCU Reel of 3000 SN74AUC2G00DCUR U00_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site. DCU: The actual top-side marking has one additional character that designates the assembly/test site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2007, Texas Instruments Incorporated SN74AUC2G00 DUAL 2-INPUT POSITIVE-NAND GATE www.ti.com SCES440C – MAY 2003 – REVISED JANUARY 2007 FUNCTION TABLE (EACH GATE) INPUTS OUTPUT Y A B H H L L X H X L H LOGIC DIAGRAM (POSITIVE LOGIC) 1A 1B 1 7 1Y 2 5 3 2A 2B 2Y 6 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX Supply voltage range –0.5 3.6 V range (2) VI Input voltage –0.5 3.6 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 3.6 V VO Output voltage range (2) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±20 mA ±100 mA Continuous current through VCC or GND θJA Tstg (1) (2) (3) 2 UNIT Package thermal impedance (3) DCT package 220 DCU package 227 YZP package 102 Storage temperature range –65 150 °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback SN74AUC2G00 DUAL 2-INPUT POSITIVE-NAND GATE www.ti.com SCES440C – MAY 2003 – REVISED JANUARY 2007 Recommended Operating Conditions VCC (1) Supply voltage VCC = 0.8 V VIH High-level input voltage MIN MAX 0.8 2.7 UNIT V VCC VCC = 1.1 V to 1.95 V 0.65 × VCC VCC = 2.3 V to 2.7 V V 1.7 VCC = 0.8 V 0 VIL Low-level input voltage VCC = 1.1 V to 1.95 V 0.35 × VCC VI Input voltage 0 3.6 V VO Output voltage 0 VCC V VCC = 2.3 V to 2.7 V IOH High-level output current IOL Low-level output current 0.7 VCC = 0.8 V –0.7 VCC = 1.1 V –3 VCC = 1.4 V –5 VCC = 1.65 V –8 VCC = 2.3 V –9 VCC = 0.8 V 0.7 VCC = 1.1 V 3 VCC = 1.4 V 5 VCC = 1.65 V 8 VCC = 2.3 V ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature (1) V mA mA 9 –40 20 ns/V 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS VCC MIN TYP (1) MAX IOH = –100 µA 0.8 V to 2.7 V IOH = –0.7 mA 0.8 V IOH = –3 mA 1.1 V 0.8 IOH = –5 mA 1.4 V 1 IOH = –8 mA 1.65 V 1.2 IOH = –9 mA 2.3 V 1.8 IOL = 100 µA 0.8 V to 2.7 V IOL = 0.7 mA 0.8 V IOL = 3 mA 1.1 V 0.3 IOL = 5 mA 1.4 V 0.4 IOL = 8 mA 1.65 V 0.45 2.3 V 0.6 IOL = 9 mA UNIT VCC – 0.1 0.55 V 0.2 0.25 V VI = VCC or GND 0 to 2.7 V ±5 µA Ioff VI or VO = 2.7 V 0 ±10 µA ICC VI = VCC or GND, 10 µA Ci VI = VCC or GND II (1) A or B inputs IO = 0 0.8 V to 2.7 V 2.5 V 2.5 pF All typical values are at TA = 25°C. Submit Documentation Feedback 3 SN74AUC2G00 DUAL 2-INPUT POSITIVE-NAND GATE www.ti.com SCES440C – MAY 2003 – REVISED JANUARY 2007 Switching Characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) VCC = 0.8 V A or B Y 8 TYP VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V MIN MAX MIN MAX MIN TYP MAX MIN MAX 1 2.5 0.8 1.6 0.6 0.9 1.2 0.5 1 UNIT ns Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A or B Y VCC = 1.8 V ± 0.15 V MIN 1.2 VCC = 2.5 V ± 0.2 V TYP MAX 1.6 2.1 UNIT MIN MAX 1 1.7 ns Operating Characteristics TA = 25°C PARAMETER Cpd 4 Power dissipation capacitance TEST CONDITIONS VCC = 0.8 V VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V TYP TYP TYP TYP TYP f = 10 MHz 12 12 12 12 13 Submit Documentation Feedback UNIT pF SN74AUC2G00 DUAL 2-INPUT POSITIVE-NAND GATE www.ti.com SCES440C – MAY 2003 – REVISED JANUARY 2007 PARAMETER MEASUREMENT INFORMATION TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 2 × VCC S1 RL From Output Under Test Open S1 Open 2 × VCC GND GND CL (see Note A) RL LOAD CIRCUIT VCC CL RL VD 0.8 V 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 15 pF 15 pF 15 pF 15 pF 15 pF 30 pF 30 pF 2 kW 2 kW 2 kW 2 kW 2 kW 1 kW 500 W 0.1 V 0.1 V 0.1 V 0.15 V 0.15 V 0.15 V 0.15 V VCC Timing Input VCC/2 0V tW tsu VCC Input VCC/2 VCC/2 th VCC Data Input VCC/2 VCC/2 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC VCC/2 Input VCC/2 0V tPLH VOH VCC/2 VOL tPHL VCC/2 tPLZ VCC VCC/2 tPZH VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH VOH Output VCC/2 tPZL tPHL VCC/2 Output VCC Output Control VOL + VD VOL tPHZ VCC/2 VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W, slew rate ³ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms Submit Documentation Feedback 5 PACKAGE OPTION ADDENDUM www.ti.com 15-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74AUC2G00DCTR ACTIVE SM8 DCT 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC2G00DCTRE4 ACTIVE SM8 DCT 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC2G00DCTRG4 ACTIVE SM8 DCT 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC2G00DCUR ACTIVE US8 DCU 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC2G00DCURE4 ACTIVE US8 DCU 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC2G00DCURG4 ACTIVE US8 DCU 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC2G00YZPR ACTIVE DSBGA YZP 8 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Aug-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74AUC2G00DCUR US8 DCU 8 3000 180.0 9.2 2.25 3.35 1.05 4.0 8.0 Q3 SN74AUC2G00YZPR DSBGA YZP 8 3000 180.0 8.4 1.02 2.02 0.63 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Aug-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AUC2G00DCUR US8 DCU 8 3000 202.0 201.0 28.0 SN74AUC2G00YZPR DSBGA YZP 8 3000 220.0 220.0 34.0 Pack Materials-Page 2 MECHANICAL DATA MPDS049B – MAY 1999 – REVISED OCTOBER 2002 DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 8 0,13 M 5 0,15 NOM ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ 2,90 2,70 4,25 3,75 Gage Plane PIN 1 INDEX AREA 1 0,25 4 0° – 8° 3,15 2,75 0,60 0,20 1,30 MAX Seating Plane 0,10 0,10 0,00 NOTES: A. B. C. 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