SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES120F – JULY 1997 – REVISED JUNE 1999 D D D D D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Output Port Has Equivalent 26-Ω Series Resistors, So No External Resistors Are Required Designed to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM Specification ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages OE Y1 Y2 GND Y3 Y4 VCC Y5 Y6 GND Y7 Y8 Y9 Y10 GND Y11 Y12 VCC Y13 Y14 GND Y15 Y16 NC NOTE: For tape and reel order entry: The DGGR package is abbreviated to GR, and the DGVR package is abbreviated to VR. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 CLK A1 A2 GND A3 A4 VCC A5 A6 GND A7 A8 A9 A10 GND A11 A12 VCC A13 A14 GND A15 A16 LE description NC – No internal connection This 16-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. The output port includes equivalent 26-Ω series resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH162334 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES120F – JULY 1997 – REVISED JUNE 1999 FUNCTION TABLE INPUTS CLK A OUTPUT Y X X X Z L X L L L L X H H L H ↑ L L L H ↑ H H Y0† OE LE H L L H L or H X † Output level before the indicated steady-state input conditions were established logic symbol‡ OE CLK LE 1 EN1 48 25 2C3 C3 G2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 2 1 1 3D 3 46 5 44 6 43 1 8 41 9 40 11 38 12 37 13 36 14 35 16 33 17 32 19 30 20 29 22 27 23 26 ‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 47 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES120F – JULY 1997 – REVISED JUNE 1999 logic diagram (positive logic) 1 OE 48 CLK LE 25 47 A1 1D C1 2 Y1 CLK To 15 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES120F – JULY 1997 – REVISED JUNE 1999 recommended operating conditions (see Note 4) VCC Supply voltage VIH High-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V MIN MAX 1.65 3.6 2 0.35 × VCC Low-level input voltage VI VO Input voltage 0 Output voltage 0 0.7 VCC = 2.7 V to 3.6 V IOL ∆t/∆v Low level output current Low-level V 1.7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High level output current High-level V 0.8 VCC VCC VCC = 1.65 V VCC = 2.3 V –2 VCC = 2.7 V VCC = 3 V –8 –6 V V mA –12 VCC = 1.65 V VCC = 2.3 V 2 VCC = 2.7 V VCC = 3 V 8 Input transition rise or fall rate V 0.65 × VCC VIL IOH UNIT 6 mA 12 10 ns/V TA Operating free-air temperature –40 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES120F – JULY 1997 – REVISED JUNE 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –2 mA IOH = –4 mA VOH 6 mA IOH = –6 3V 2 1.65 V to 3.6 V 0.2 1.65 V 0.45 2.3 V 0.4 2.3 V 0.55 3V 0.55 2.7 V 0.6 3V 0.8 ±5 3.6 V 1.65 V 25 VI = 1.07 V VI = 0.7 V 1.65 V –25 2.3 V 45 VI = 1.7 V VI = 0.8 V 2.3 V –45 3V 75 3V –75 VO = VCC or GND VI = VCC or GND, ∆ICC One input at VCC – 0.6 V, IO = 0 Other inputs at VCC or GND UNIT V IOL = 100 µA IOL = 2 mA IOZ ICC Data inputs 1.7 2 VI = VCC or GND VI = 0.58 V Control inputs 1.9 2.3 V 2.4 VI = 2 V VI = 0 to 3.6 V‡ Ci 2.3 V MAX 3V IOL = 8 mA IOL = 12 mA II(hold) ( ) 1.65 V VCC–0.2 1.2 2.7 V IOL = 6 mA II TYP† IOH = –8 mA IOH = –12 mA IOL = 4 mA VOL MIN V µA µA 3.6 V ±500 3.6 V ±10 µA 3.6 V 40 µA 3 V to 3.6 V 750 µA VI = VCC or GND 33V 3.3 5.5 6 pF Co Outputs VO = VCC or GND 3.3 V 8 pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES120F – JULY 1997 – REVISED JUNE 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock tw tsu Clock frequency Pulse duration MIN MAX MIN 150 MAX VCC = 3.3 V ± 0.3 V MIN 150 3.3 3.3 3.3 CLK high or low † 3.3 3.3 3.3 Data before CLK↑ † 1.4 1.7 1.5 CLK high † 1.2 1.6 1.3 CLK low † 1.4 1.5 1.2 † 0.9 0.8 0.9 † 1.2 1.1 1.1 Data before LE↑ Data after LE↑ CLK high or low UNIT MAX 150 LE low Setup time Hold time MAX † VCC = 2.7 V † Data after CLK↑ th VCC = 2.5 V ± 0.2 V MHz ns ns ns † This information was not available at the time of publication. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER TO (OUTPUT) fmax VCC = 1.8 V MIN † A tpd Y LE CLK ten tdis OE Y OE Y † This information was not available at the time of publication. VCC = 2.5 V ± 0.2 V TYP MIN MAX 150 † 1 † 1 † 1 † 1 † 1 VCC = 2.7 V MIN MAX 150 3.9 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz 4.5 1.1 3.9 5 6 1.3 5 4.9 5.4 1 4.9 5.4 6.4 1.1 5.4 ns 5 5.1 1.7 5 ns ns operating characteristics, TA = 25°C PARAMETER Cpd d Power dissipation capacitance TEST CONDITIONS Outputs enabled Outputs disabled CL = 0 0, VCC = 1.8 V TYP † f = 10 MHz † This information was not available at the time of publication. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 † VCC = 2.5 V TYP VCC = 3.3 V TYP 32 37 7 11.5 UNIT pF SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES120F – JULY 1997 – REVISED JUNE 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 2 × VCC S1 1 kΩ From Output Under Test Open GND CL = 30 pF (see Note A) 1 kΩ TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC Input Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES120F – JULY 1997 – REVISED JUNE 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES120F – JULY 1997 – REVISED JUNE 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input 1.5 V 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V Output Control (low-level enabling) 1.5 V 0V tPZL 2.7 V Input 1.5 V 1.5 V 0V tPLH 1.5 V tPLZ 3V 1.5 V tPZH VOH Output Output Waveform 1 S1 at 6 V (see Note B) tPHL 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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