TI SN74ALVCH162832

SN74ALVCH162832
1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCAS588F – MAY 1997 – REVISED JUNE 1999
D
D
D
D
D
D
D
DGG PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus  Family
EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
Output Ports Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Packaged in Thin Shrink Small-Outline
Package
4Y1
3Y1
GND
2Y1
1Y1
VCC
A1
GND
A2
GND
A3
VCC
NC
GND
CLK
OE1
OE2
SEL
GND
A4
A5
VCC
GND
A6
GND
A7
VCC
4Y7
3Y7
GND
2Y7
1Y7
NOTE: For tape and reel order entry:
The DGGR package is abbreviated to GR.
description
This 1-bit to 4-bit address register/driver is
designed for 1.65-V to 3.6-V VCC operation.
This device is ideal for use in applications in which
a single address bus is driving four separate
memory locations. The SN74ALVCH162832 can
be used as a buffer or a register, depending on the
logic level of the select (SEL) input.
When SEL is a logic high, the device is in the buffer
mode. The outputs follow the inputs and are
controlled by the two output-enable (OE) inputs.
Each OE controls two groups of seven outputs.
When SEL is a logic low, the device is in the
register mode. The register is an edge-triggered
D-type flip-flop. On the positive transition of the
clock (CLK) input, data at the A inputs is stored in
the internal registers. OE controls operate the
same as in the buffer mode.
1
64
2
63
3
62
4
61
5
60
6
59
7
58
8
57
9
56
10
55
11
54
12
53
13
52
14
51
15
50
16
49
17
48
18
47
19
46
20
45
21
44
22
43
23
42
24
41
25
40
26
39
27
38
28
37
29
36
30
35
31
34
32
33
1Y2
2Y2
GND
3Y2
4Y2
VCC
1Y3
2Y3
GND
3Y3
4Y3
GND
VCC
GND
1Y4
2Y4
3Y4
4Y4
GND
1Y5
2Y5
VCC
3Y5
4Y5
GND
GND
VCC
1Y6
2Y6
GND
3Y6
4Y6
NC – No internal connection
When OE is a logic low, the outputs are in a normal logic state (high or low logic level). When OE is a logic high,
the outputs are in the high-impedance state.
Neither SEL nor OE affect the internal operation of the flip-flops. Old data can be retained or new data can be
entered while the outputs are in the high-impedance state.
The outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot
and undershoot.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74ALVCH162832
1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCAS588F – MAY 1997 – REVISED JUNE 1999
description (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162832 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OE
SEL
CLK
A
OUTPUT
Y
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
↑
L
L
L
L
↑
H
H
logic diagram (positive logic)
OE1
OE2
16
5
4
CLK
15
A1
D
3Y1
Q
1
18
To Six Other Channels
2
2Y1
CLK
2
7
SEL
1Y1
17
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• DALLAS, TEXAS 75265
4Y1
SN74ALVCH162832
1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCAS588F – MAY 1997 – REVISED JUNE 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
High-level input voltage
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VIL
VI
VO
IOH
Low-level input voltage
MIN
MAX
1.65
3.6
2
0.35 × VCC
0.7
0
0
∆t/∆v
Input transition rise or fall rate
V
0.8
Output voltage
Low level output current
Low-level
V
1.7
Input voltage
IOL
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
High level output current
High-level
UNIT
VCC
VCC
VCC = 1.65 V
VCC = 2.3 V
–2
VCC = 2.7 V
VCC = 3 V
–8
–6
V
V
mA
–12
VCC = 1.65 V
VCC = 2.3 V
2
VCC = 2.7 V
VCC = 3 V
8
6
mA
12
10
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74ALVCH162832
1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCAS588F – MAY 1997 – REVISED JUNE 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
IOH = –100 µA
IOH = –2 mA
1.65 V
2.3 V
1.9
2.3 V
1.7
6 mA
IOH = –6
3V
2.4
2
3V
2
IOL = 100 µA
IOL = 2 mA
1.65 V to 3.6 V
0.2
1.65 V
0.45
IOL = 8 mA
IOL = 12 mA
VI = VCC or GND
VI = 0.58 V
II(hold)
(
)
3V
0.55
2.7 V
0.6
3V
0.8
±5
VI = 1.07 V
VI = 0.7 V
1.65 V
–25
2.3 V
45
VI = 1.7 V
VI = 0.8 V
2.3 V
–45
3V
75
3V
–75
VO = VCC or GND
VI = VCC or GND,
∆ICC
One input at VCC – 0.6 V,
Data inputs
0.55
25
IOZ
ICC
Control inputs
0.4
2.3 V
3.6 V
VI = 2 V
VI = 0 to 3.6 V‡
Ci
2.3 V
1.65 V
IO = 0
Other inputs at VCC or GND
UNIT
V
2.7 V
IOL = 6 mA
II
MAX
IOH = –8 mA
IOH = –12 mA
IOL = 4 mA
VOL
TYP†
VCC–0.2
1.2
IOH = –4 mA
VOH
MIN
V
µA
µA
3.6 V
±500
3.6 V
±10
µA
3.6 V
40
µA
3 V to 3.6 V
750
µA
VI = VCC or GND
4.5
33V
3.3
pF
5
Co
Outputs
VO = VCC or GND
3.3 V
7.5
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
VCC = 1.8 V
MIN
MIN
MAX
VCC = 2.7 V
MIN
MIN
Pulse duration, CLK high or low
§
3.3
3.3
3.3
ns
tsu
th
Setup time, A data before CLK↑
§
2
2
1.6
ns
§
0.7
0.5
1.1
ns
• DALLAS, TEXAS 75265
150
UNIT
MAX
Clock frequency
POST OFFICE BOX 655303
150
MAX
VCC = 3.3 V
± 0.3 V
fclock
tw
Hold time, A data after CLK↑
§ This information was not available at the time of publication.
4
MAX
§
VCC = 2.5 V
± 0.2 V
150
MHz
SN74ALVCH162832
1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCAS588F – MAY 1997 – REVISED JUNE 1999
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
fmax
VCC = 1.8 V
MIN
†
A
tpd
Y
CLK
SEL
VCC = 2.5 V
± 0.2 V
TYP
MIN
MAX
150
VCC = 2.7 V
MIN
MAX
150
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
150
MHz
†
1.1
4.7
4.8
1.5
4.3
†
1
5.3
5.3
1.4
4.7
†
1.1
6
6.2
1.5
4.8
ns
ten
OE
Y
†
1
5.9
5.9
1.1
5.1
ns
tdis
OE
Y
†
1.4
6.3
5.4
1.6
5.1
ns
† This information was not available at the time of publication.
operating characteristics, TA = 25°C
PARAMETER
Cpd
d
Power dissipation
capacitance
TEST CONDITIONS
All outputs enabled
All outputs disabled
CL = 0
0,
VCC = 1.8 V
TYP
†
f = 10 MHz
†
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
119
132
22
25
UNIT
pF
† This information was not available at the time of publication.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN74ALVCH162832
1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCAS588F – MAY 1997 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ALVCH162832
1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCAS588F – MAY 1997 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN74ALVCH162832
1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCAS588F – MAY 1997 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
LOAD CIRCUIT
tw
2.7 V
2.7 V
Timing
Input
1.5 V
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
Output
Control
(low-level
enabling)
2.7 V
1.5 V
1.5 V
0V
tPZL
2.7 V
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
0V
0V
tsu
1.5 V
0V
tPLH
Output
1.5 V
Input
Output
Waveform 1
S1 at 6 V
(see Note B)
3V
1.5 V
VOL + 0.3 V
tPZH
tPHL
VOH
1.5 V
tPLZ
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Output
Waveform 2
S1 at GND
(see Note B)
VOL
tPHZ
1.5 V
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
8
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright  1999, Texas Instruments Incorporated