NanoAmp Solutions, Inc.
1982 Zanker Road, San Jose, CA 95112
ph: 408-573-8878, FAX: 408-573-8877
www.nanoamp.com
N32T1630C1E
32Mb Ultra-Low Power Asynchronous CMOS PSRAM
2M x 16 bit
Overview
Features
The N32T1630C1E is an integrated memory
device containing a 32 Mbit Pseudo Static Random
Access Memory using a self-refresh DRAM array
organized as 2,097,152 words by 16 bits. It is
designed to be identical in operation and interface
to standard 6T SRAMS. The device is designed for
low standby and operating current and includes a
power-down feature to automatically enter standby
mode. Also included are several other power
saving modes: a deep sleep mode where data is
not retained in the array and partial array refresh
mode where data is retained in a portion of the
array. Both these modes reduce standby current
drain. The device can operate over a very wide
temperature range of -25oC to +85oC.
• Dual voltage for Optimum Performance:
Vccq - 2.7V to 3.3V
Vcc - 2.7V to 3.3V
• Fast Cycle Times
TACC < 60 nS
TACC < 70 nS
• Very low standby current
ISB < 120µA
• Very low operating current
Icc < 25mA
• Dual rail operation
VCCQ and VSSQ for separate I/O power rail
• Compact Space Saving BGA Package
Product Family
Part Number
Package
Type
Operating
Temperature
Power
Supply
Speed
N32T1630C1EZ
48-BGA
-25oC to +85oC
2.7V - 3.3V(VCC)
60ns
70ns
Figure 1: Pin Configuration
1
2
3
4
5
6
A
LB
OE
A0
A1
A2
ZZ
B
I/O8
UB
A3
A4
CE
I/O0
C
I/O9
I/O10
A5
A6
I/O1
I/O2
D
VSSQ I/O11
A17
A7
I/O3
VCC
E
VCCQ I/O12
NC
A16
I/O4
F
I/O14 I/O13
A14
A15
G
I/O15
A19
A12
H
A18
A8
A9
Standby
Operating
Current (ISB), Current (Icc),
Max
Max
120 µA
3 mA @ 1MHz
Table 1: Pin Descriptions
Pin Name
Pin Function
A0-A20
Address Inputs
WE
Write Enable Input
CE
Chip Enable Input
VSS
ZZ
Deep Sleep Input
I/O5
I/O6
OE
Output Enable Input
A13
WE
I/O7
LB
Lower Byte Enable Input
A10
A11
A20
48 Pin BGA (top)
6 x 8 mm
UB
Upper Byte Enable Input
I/O0-I/O15
Data Inputs/Outputs
VCC
Power
VSS
Ground
VCCQ
Power I/O only
VSSQ
Ground I/O only
(DOC # 14-02-006 Rev C ECN 01-1040
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
1
N32T1630C1E
NanoAmp Solutions, Inc.
Functional Block Diagram
Address
Inputs
A0 - A20
Address
Decode
Logic
2048K x 16
Input/
Output
Mux I/O0 - I/O7
and
Buffers
Memory
Array
I/O8 - I/O15
CE
WE
OE
UB
LB
Control
Logic
ZZ
Functional Description
CE
WE
OE
UB/LB
ZZ
I/O1
MODE
POWER
H
X
X
X
H
High Z
Standby2
Standby
X
X
X
H
H
High Z
Standby2
Standby
L
L
X3
L1
H
Data In
Write3
Active
L
H
L
L
1
H
Data Out
Read
Active
L
H
H
L
1
H
High Z
Output Disabled
Active
H
X
X
X
L
High Z
Low Power Modes
Low Power
1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only
I/O0 - IO7 are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown. If both UB and LB
are in the deselect mode (high), the chip is in a standby mode regardless of the state of CE.
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are
internally isolated from any external influence and disabled from exerting any influence externally.
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
Capacitance1
Item
Symbol
Test Condition
Input Capacitance
CIN
CI/O
I/O Capacitance
Max
Unit
VIN = 0V, f = 1 MHz, TA = 25oC
8
pF
25oC
8
pF
VIN = 0V, f = 1 MHz, TA =
Min
1. These parameters are verified in device characterization and are not 100% tested
(DOC # 14-02-006 Rev C ECN 01-1040
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
2
N32T1630C1E
NanoAmp Solutions, Inc.
Absolute Maximum Ratings1
Item
Symbol
Rating
Unit
Voltage on any pin relative to VSS
VIN,OUT
–0.2 to VCC+0.3
V
Voltage on VCC Supply Relative to VSS
VCC
–0.2 to 3.6
V
Power Dissipation
PD
1
Storage Temperature
TSTG
Operating Temperature
TA
W
–65 to 125
o
-25 to +85
oC
C
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Operating Characteristics (Over Specified Temperature Range)
Item
Symbol
Comments
Min.
Typ1
Max.
Unit
3.3
V
Supply Voltage
VCC
2.7
3.0
Supply Voltage for I/O
VCCQ
2.7
3.0
3.3
V
Input High Voltage
VIH
0.8VCCQ
VCC+0.2
V
–0.2
0.2VCCQ
V
Input Low Voltage
VIL
Output High Voltage
VOH
IOH = -0.5mA
Output Low Voltage
VOL
IOL = 0.5mA
Input Leakage Current
ILI
VIN = 0 to VCC
Output Leakage Current
ILO
OE = VIH or Chip Disabled
Read/Write Operating Supply Current
@ 1 µs Cycle Time2
ICC1
Read/Write Operating Supply Current
@ Min Cycle Time2
Standby Current
0.8VCCQ
V
0.2VCCQ
V
-1
1
µA
-1
1
µA
VCC=VCCMAX, VIN=VIH / VIL
Chip Enabled, IOUT = 0
3
mA
ICC2
VCC=VCCMAX, VIN=VIH / VIL
Chip Enabled, IOUT = 0
25
mA
ISB
Chip deselected, CE>VCC0.2, ZZ>VCC-0.2 and VIN =
0 or VCC
120
µA
1. Typical values are measured at Vcc=Vcc Typ., TA=25°C and not 100% tested.
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive
output capacitance expected in the actual system.
(DOC # 14-02-006 Rev C ECN 01-1040
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
3
N32T1630C1E
NanoAmp Solutions, Inc.
Timing Test Conditions
Item
Input Pulse Level
0.1VCC to 0.9 VCC
Input Rise and Fall Time
5ns
Input and Output Timing Reference Levels
0.5 VCC
Operating Temperature
-25 oC to +85 oC
Output Load Circuit
I/O
50 pF
Output Load
Power Up Sequence
After applying power, maintain a stable power supply for a minimum of 200us after CE > VIH.
(DOC # 14-02-006 Rev C ECN 01-1040
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
4
N32T1630C1E
NanoAmp Solutions, Inc.
Timings
-60
-70
Units
Item
Symbol
Read Cycle Time
tRC
Address Access Time
tAA
Page Mode Read Cycle Time
tPC
Page Mode Access Time
tPA
Chip Enable to Valid Output
tCO
Output Enable to Valid Output
tOE
Byte Select to Valid Output
tLB, tUB
Chip Enable to Low-Z output
tLZ
10
10
ns
Output Enable to Low-Z Output
tOLZ
5
5
ns
Byte Select to Low-Z Output
tBZ
10
10
ns
Chip Disable to High-Z Output
tHZ
0
5
0
5
ns
Output Disable to High-Z Output
tOHZ
0
5
0
5
ns
Byte Select Disable to High-Z Output
tBHZ
0
5
0
5
ns
Output Hold from Address Change
tOH
5
Write Cycle Time
tWC
60
20000
70
20000
ns
Page Mode Write Cycle Time
tPWC
25
20000
25
20000
ns
Chip Enable to End of Write
tCW
50
60
ns
Address Valid to End of Write
tAW
50
60
ns
Byte Select to End of Write
tBW
50
60
ns
Write Pulse Width
tWP
50
50
ns
Write Recovery Time
tWR
0
0
ns
Write to High-Z Output
tWHZ
Address Setup Time
tAS
0
0
ns
Data to Write Time Overlap
tDW
20
20
ns
Data Hold from Write Time
tDH
0
0
ns
End Write to Low-Z Output
tOW
5
5
ns
Maximum Page Mode Cycle
tPGMAX
Chip Enable High Pulse Width
tCP
Min.
Max.
Min.
Max.
60
20000
70
20000
ns
70
ns
20000
ns
25
25
ns
60
70
ns
25
25
ns
60
70
ns
60
25
20000
25
5
5
5
20000
10
ns
20000
10
ns
ns
ns
Do not access device with invalid cycle time (shorter than tRC, tWC) for a continous period > 20us.
(DOC # 14-02-006 Rev C ECN 01-1040
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
5
N32T1630C1E
NanoAmp Solutions, Inc.
Timing of Read Cycle (CE = OE = VIL, WE = ZZ = VIH)
tRC
Address
tAA
tOH
Data Out
Previous Data Valid
Data Valid
Timing Waveform of Read Cycle (WE = ZZ = VIH)
tRC
Address
tAA
CE
tCO
tLZ
tHZ
tOE
OE
tOLZ
tOHZ
tLB, tUB
LB, UB
tBLZ
Data Out
High-Z
tBHZ
Data Valid
(DOC # 14-02-006 Rev C ECN 01-1040
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
6
N32T1630C1E
NanoAmp Solutions, Inc.
Timing Waveform of Page Mode Read Cycle (WE = ZZ = VIH)
tPGMAX
Page Address (A4 - A20)
tRC
tPC
Word Address (A0 - A3)
tAA
tPA
CE
tHZ
tCO
tOE
tOHZ
OE
tOLZ
LB, UB
Data Out
tBHZ
tLB, tUB
High-Z
tBLZ,
(DOC # 14-02-006 Rev C ECN 01-1040
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
7
N32T1630C1E
NanoAmp Solutions, Inc.
Timing Waveform of Write Cycle (WE control, ZZ = VIH)
tWC
Address
tWR
tAW
CE
tCW
tBW
LB, UB
tAS
tWP
WE
tDW
High-Z
tDH
Data Valid
Data In
tWHZ
tOW
High-Z
Data Out
Timing Waveform of Write Cycle (CE Control, ZZ = VIH)
tWC
Address
tAW
tWR
CE
tCW
tAS
tBW
LB, UB
tWP
WE
tDW
tDH
Data Valid
Data In
tWHZ
Data Out
High-Z
(DOC # 14-02-006 Rev C ECN 01-1040
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
8
N32T1630C1E
NanoAmp Solutions, Inc.
Timing Waveform of Page Mode Write Cycle (ZZ = VIH)
tPGMAX
Page Address
(A4 - A20)
tWC
tPWC
Word Address
(A0 - A3)
CE
tAS
tCW
tWP
WE
tLBW, tUBW
LB, UB
tDW
Data Out
tDH
tPDW
tPDH
tPDW
tPDH
High-Z
(DOC # 14-02-006 Rev C ECN 01-1040
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
9
NanoAmp Solutions, Inc.
N32T1630C1E
Power Savings Modes
The three low power modes are:
• Reduced Memory Size
• Partial Array Refresh
• Deep Sleep Mode
The operation of the power saving modes is controlled by setting the Variable Address Register (VAR).
This VAR is shown in the following “Variable Address Register” figure and is used to enable/disable the
various low power modes. The VAR is set by using the timings defined in the figure titled “Variable
Address Register (VAR) Update Timings”. The register must be set in less then 1us after ZZ is enabled
low.
1) Reduced Memory Size (RMS)
In this mode of operation, the 32Mb PSRAM can be operated as a 8Mb or 16Mb device. The mode and
array size are determined by the settings in the VA register. The VA register is set according to the following timings and the bit settings in the table “Address Patterns for RMS”. The RMS mode is enabled at the
time of ZZ transitioning high and the mode remains active until the register is updated. To return to the full
32Mb address space, the VA register must be reset using the previously defined procedures. While operating in the RMS mode, the unselected portion of the array may not be used.
2) Partial Array Refresh (PAR)
In this mode of operation, the internal refresh operation can be restricted to a 8Mb or 16Mb portion of the
array. The mode and array partition to be refreshed are determined by the settings in the VA register. The
VA register is set according to the following timings and the bit settings in the table “Address Patterns for
PAR”. In this mode, when ZZ is active low, only the portion of the array that is set in the register is
refreshed. The operating mode is only available during standby time (ZZ low) and once ZZ is returned
high, the device resumes full array refresh. All future PAR cycles will use the contents of the VA register
that has been previously set. To change the address space of the PAR mode, the VA register must be
reset using the previously defined procedures.
3) Deep Sleep Mode
In this mode of operation, the internal refresh is turned off and all data integrity of the array is lost. Deep
Sleep is entered by bringing ZZ low with the A4 register programmed to “Deep Sleep Enabled”. The
device will remain in this mode as long as ZZ remains low and when ZZ is driven high, all register settings
will return to default states.
(DOC # 14-02-006 Rev C ECN 01-1040
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
10
N32T1630C1E
NanoAmp Solutions, Inc.
Variable Address Register
A20 - A5
A4
A3
A2
A1
Array mode for ZZ
Reserved for future
Preferably set to all 0
Array section
0 = PAR mode (default)
1 = RMS mode
ZZ Enable/Disable
0 = Deep Sleep Enabled
1 = Deep Sleep Disabled
(default)
A0
1
1
0
0
1 = 1/4 array
0 = 1/2 array
1 = Reserved
0 = Full array
(default)
Array half
0 = Bottom array (default)
1 = Top array
Variable Address Register (VAR) Update Timings
tWC
A0-A4
tWR
tAW
CE
tWP
tAS
WE
tZZWE
ZZ
tBW
LB, UB
Deep Sleep Mode - Entry/Exit Timings
tWC
A4
tAS
tAW
CE
tWP
tWR
WE
LB, UB
ZZ
tZZWE
tBW
tR
tZZMIN
(DOC # 14-02-006 Rev C ECN 01-1040
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
11
N32T1630C1E
NanoAmp Solutions, Inc.
VAR Update and Deep Sleep Timings
Item
Symbol
Min
Max
Unit
1
us
ZZ low to WE low
tZZWE
Deep Sleep Mode
tZZMIN
10
us
tR
200
us
Deep Sleep Recovery
Address Patterns for PAR (A3 = 0, A4 = 1)
A2
0
0
x
1
1
A1
1
1
0
1
1
A0
1
0
0
1
0
Active Section
Address space
One-quarter of die
One-half of die
Full die
One-quarter of die
One-half of die
Size
000000h - 07FFFFh
000000h - 0FFFFFh
000000h - 1FFFFFh
180000h - 1FFFFFh
100000h - 1FFFFFh
Density
512Kb x 16
1Mb x 16
2Mb x 16
512Kb x 16
1Mb x 16
8Mb
16Mb
32Mb
8Mb
16Mb
Address Patterns for RMS (A3 = 1, A4 = 1)
A2
0
0
1
1
A1
1
1
1
1
A0
1
0
1
0
Active Section
Address space
One-quarter of die
One-half of die
One-quarter of die
One-half of die
Size
000000h - 07FFFFh
000000h - 0FFFFFh
180000h - 1FFFFFh
100000h - 1FFFFFh
Density
512Kb x 16
1Mb x 16
512Kb x 16
1Mb x 16
8Mb
16Mb
8Mb
16Mb
Low Power ICC Characteristics
Item
Symbol
PAR Mode Standby
Current
IPAR
RMS Mode
Standby Current
IRMSSB
Deep Sleep Current
IZZ
Array
Partition
Test
VIN = VCC or 0V,
Chip Disabled, tA= 85oC
VIN = VCC or 0V,
Chip Disabled, tA=
85oC
VIN = VCC or 0V,
1/4 Array
1/2 Array
4Mb Device
8Mb Device
Typ
Max
Unit
75
90
75
90
10
uA
uA
uA
Chip in ZZ mode, tA= 85oC
(DOC # 14-02-006 Rev C ECN 01-1040
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
12
N32T1630C1E
NanoAmp Solutions, Inc.
Figure 2: Ball Grid Array Package
0.23±0.05
0.90±0.10
D
A1 BALL PAD
CORNER (3)
1. 0.30±0.05 DIA.
E
2. SEATING PLANE - Z
0.15 Z
0.08
TOP VIEW
Z
SIDE VIEW
1. DIMENSION IS MEASURED AT THE
A1 BALL PAD
MAXIMUM SOLDER BALL DIAMETER.
CORNER
PARALLEL TO PRIMARY Z.
SD
e
SE
2. PRIMARY DATUM Z AND SEATING
PLANE ARE DEFINED BY THE
SPHERICAL CROWNS OF THE
SOLDER BALLS.
3. A1 BALL PAD CORNER I.D. TO BE
MARKED BY INK.
K TYP
J TYP
e
BOTTOM VIEW
Table 2: Dimensions (mm)
e = 0.75
D
6±0.10
SD
SE
J
K
BALL
MATRIX
TYPE
0.375
0.375
1.125
1.375
FULL
E
8±0.10
(DOC # 14-02-006 Rev C ECN 01-1040
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
13
N32T1630C1E
NanoAmp Solutions, Inc.
Ordering Information
N32T1630C1EZ - XX I
60 = 60ns
Performance
Package
70 = 70ns
Z = BGA
Revision History
Revision
Date
Change Description
A
Feb 2004
Initial Advance Release Package Datasheet
B
Mar 2004
Multiple Changes. Change ISB to 120uA. Added tCP timing parameter.
C
December 2004
Changed load circuit to 50pF and clarified low power mode with CE# high
© 2004 Nanoamp Solutions, Inc. All rights reserved.
NanoAmp Solutions, Inc. ("NanoAmp") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice.
NanoAmp does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration purposes only and they vary depending upon specific applications.
NanoAmp makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does NanoAmp assume any liability arising out of the application
or use of any product or circuit described herein. NanoAmp does not authorize use of its products as critical components in any application in which the failure of the NanoAmp
product may be expected to result in significant injury or death, including life support systems and critical medical instrument.
(DOC # 14-02-006 Rev C ECN 01-1040
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
14