SN54AHCT367, SN74AHCT367 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS418F – JUNE 1998 – REVISED MAY 2002 D D D D SN54AHCT367 . . . J OR W PACKAGE SN74AHCT367 . . . D, DB, DGV, N, NS, OR PW PACKAGE (TOP VIEW) Inputs Are TTL-Voltage Compatible True Outputs Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 1OE 1A1 1Y1 1A2 1Y2 1A3 1Y3 GND description The ’AHCT367 devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices are organized as dual 4-line and 2-line buffers/drivers with active-low output-enable (1OE and 2OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 2OE 2A2 2Y2 2A1 2Y1 1A4 1Y4 1A1 1OE NC VCC 2OE SN54AHCT367 . . . FK PACKAGE (TOP VIEW) 1Y1 1A2 NC 1Y2 1A3 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2A2 2Y2 NC 2A1 2Y1 1Y3 GND NC 1Y4 1A4 To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 4 NC – No internal connection ORDERING INFORMATION PDIP – N –55°C to 125°C TOP-SIDE MARKING Tube SN74AHCT367N Tube SN74AHCT367D Tape and reel SN74AHCT367DR SOP – NS Tape and reel SN74AHCT367NSR AHCT367 SSOP – DB Tape and reel SN74AHCT367DBR HB367 TSSOP – PW Tape and reel SN74AHCT367PWR HB367 TVSOP – DGV Tape and reel SN74AHCT367DGVR HB367 CDIP – J Tube SNJ54AHCT367J SNJ54AHCT367J CFP – W Tube SNJ54AHCT367W SNJ54AHCT367W LCCC – FK Tube SNJ54AHCT367FK SNJ54AHCT367FK SOIC – D –40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA SN74AHCT367N AHCT367 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54AHCT367, SN74AHCT367 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS418F – JUNE 1998 – REVISED MAY 2002 FUNCTION TABLE (each buffer/driver) INPUTS OE A OUTPUT Y H X Z L H H L L L logic diagram (positive logic) 1OE 1A1 1 2 2OE 3 1Y1 2A1 15 12 To Three Other Channels 11 2Y1 To One Other Channel Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54AHCT367, SN74AHCT367 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS418F – JUNE 1998 – REVISED MAY 2002 recommended operating conditions (see Note 3) SN54AHCT367 SN74AHCT367 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 V Input voltage 0 5.5 0 5.5 V VO IOH Output voltage 0 0 VCC –8 V High-level output current VCC –8 mA IOL ∆t/∆v Low-level output current 8 8 mA 20 20 ns/V High-level input voltage 2 2 0.8 Input transition rise or fall rate V V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VOH IOH = –50 mA IOH = –8 mA 45V 4.5 VOL IOL = 50 mA IOL = 8 mA 45V 4.5 II IOZ ICC ∆ICC† Ci MIN 4.4 TA = 25°C TYP MAX 4.5 3.94 SN54AHCT367 MIN MAX SN74AHCT367 MIN 4.4 4.4 3.8 3.8 MAX UNIT V 0.1 0.1 0.1 0.36 0.44 0.44 V VI = 5.5 V or GND VI = VCC or GND, VO = VCC or GND, OE = VIH 0 V to 5.5 V ±0.1* ±1* ±1 mA 5.5 V ±0.25 ±2.5 ±2.5 mA VI = VCC or GND, IO = 0 One input at 3.4 V, Other inputs at VCC or GND 5.5 V 4 40 40 mA 5.5 V 1.35 1.5 1.5 mA 10 10 10 pF VI = VCC or GND 5V 2.5 Co VO = VCC or GND 5V 5 * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. † This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC. pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54AHCT367, SN74AHCT367 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS418F – JUNE 1998 – REVISED MAY 2002 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL A Y CL = 15 pF tPZH tPZL OE Y CL = 15 pF tPHZ tPLZ OE Y CL = 15 pF tPLH tPHL A Y CL = 50 pF tPZH tPZL OE Y CL = 50 pF tPHZ tPLZ OE Y CL = 50 pF MIN TA = 25°C TYP MAX SN54AHCT367 SN74AHCT367 MIN MAX MIN MAX 2.5* 4.8* 1* 6.5* 1 5.5 2.5* 4.8* 1* 6.5* 1 5.5 3.5* 8* 1* 9.5* 1 8.5 2.8* 7* 1* 8.5* 1 7.5 3.1* 8* 1* 9.5* 1 8.5 2.8* 7* 1* 8.5* 1 7.5 3.5 5.8 1 7.5 1 6.5 3.3 5.8 1 7.5 1 6.5 4.5 9 1 10.5 1 9.5 3.7 8 1 9.5 1 8.5 4.1 9 1 10.5 1 9.5 3.6 8 1 9.5 1 8.5 UNIT ns ns ns ns ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4) SN74AHCT367 PARAMETER MIN TYP MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.4 V Quiet output, minimum dynamic VOL –0.4 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 4.7 V High-level dynamic input voltage 2 VIL(D) Low-level dynamic input voltage NOTE 4: Characteristics are for surface-mount packages only. V 0.8 V TYP UNIT operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load, PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz 22 pF SN54AHCT367, SN74AHCT367 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS418F – JUNE 1998 – REVISED MAY 2002 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point RL = 1 kΩ From Output Under Test S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw 3V 1.5 V Input 1.5 V th tsu 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPZL tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC 3V Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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