TECHNICAL DATA IW4053B Analog Multiplexer Demultiplexer High-Performance Silicon-Gate CMOS The IW4053B analog multiplexer/demultiplexer is digitally controlled analog switches having low ON impedance and very low OFF leakage current. Control of analog signals up to 20V peak-to-peak can be achieved by digital signal amplitudes of 4.5 to 20V (if VCC - GND = 3V, a VCC - VEE of up to 13 V can be controlled; for VCC - VEE level differences above 13V a VCC - GND of at least 4.5V is required). These multiplexer circuits dissipate extremely low quiescent power over the full VCC -GND and VCC - VEE supply-voltage ranges, independent of the logic state of the control signals. When a logic “1”is present at the ENABLE input terminal all channels are off. The IW4053B is a triple 2-channel multiplexer having three separate digital control inputs, A, B, and C, and an enable input. Each control input selects one of a pair of channels which are connected in a singlepole double-throw configuration. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C • Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply ORDERING INFORMATION IW4053BN Plastic DIP IW4053BD SOIC IZ4053B chip TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM Triple Single-Pole, Double-Position Plus Common Off FUNCTION TABLE Control Inputs Enable PIN 16 =VCC PIN 7 = VEE PIN 8 = GND INTEGRAL ON Select Channels C B A L L L L Z0 Y0 X0 L L L H Z0 Y0 X1 L L H L Z0 Y1 X0 L L H H Z0 Y1 X1 L H L L Z1 Y0 X0 L H L H Z1 Y0 X1 L H H L Z1 Y1 X0 L H H H Z1 Y1 X1 H X X X None H = high level L = low level X = don’t care 1 IW4053B MAXIMUM RATINGS * Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) IIN DC Input Current, per Pin PD Power Dissipation in Still Air Ptot Power Dissipation per Output Transistor Tstg Unit -0.5 to +20 V -0.5 to VCC +0.5 V ±10 mA 500* Storage Temperature TL Value Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SO Package) 1 mW 100 mW -65 to +150 °C 260 °C *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. * 1 - for Plastic DIP from -55° to +100°C, for SO Package from -55° to +65°C. +Derating - Plastic DIP: - 12 mW/°C from 100° to 125°C SO Package: - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) TA Operating Temperature, All Package Types Min Max Unit 3.0 18 V 0 VCC V -55 +125 °C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused digital pins must be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused Analog I/O pins may be left open or terminated. INTEGRAL 2 IW4053B DC ELECTRICAL CHARACTERISTICS Digital Section VCC Guaranteed Limit V ≥ -55 °C ≤ 25 °C ≤ 125 °C Unit VIS=VCC thru 1kΩ VEE=GND=0 IIS<2µA on all OFF Chanels RL=1kΩ to GND 5 10 15 3.5 7 11 3.5 7 11 3.5 7 11 V Maximum Low -Level Input Voltage, ChannelSelect or Enable Inputs VIS=VCC thru 1kΩ VEE=GND=0 IIS<2µA on all OFF Chanels RL=1kΩ to GND 5 10 15 1.5 3 4 1.5 3 4 1.5 3 4 V IIN Maximum Input Leakage Current, Channel-Select or Enable Inputs VIN=VCC or GND VEE=GND=0 18 ±0.1 ±0.1 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) Channel Select = VCC or GND VEE=GND=0 5 10 15 20 5 10 20 100 5 10 20 100 150 300 600 3000 µA Symbol Parameter VIH Minimum High-Level Input Voltage, ChannelSelect or Enable Inputs VIL Test Conditions DC ELECTRICAL CHARACTERISTICS Analog Section VCC Symbol RON ∆RON IOFF Parameter Test Conditions Guaranteed Limit V ≥ -55 °C ≤ 25 °C ≤ 125 °C Unit Maximum “ON” Resistance VEE=GND=0 VIS = GND to VCC 5 10 15 800 310 200 1050 400 240 1150 550 320 Ω Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package VEE=GND=0 5 10 15 - 10* 15* 5* - Ω Maximum Off- Channel Leakage Current, Any One Channel VEE=GND=0 18 ±100 ±100 ±1000 nA Maximum Off- Channel Leakage Current, Common Channel VEE=GND=0 18 ±100 ±100 ±1000 * - Typical Value INTEGRAL 3 IW4053B INTEGRAL 4 IW4053B AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=20.0 ns) VCC Symbol Parameter Guaranteed Limit V ≥ -55 °C ≤ 25 °C ≤ 125 °C Unit tPHL(tPLH) Maximum Propagation Delay , Analog Input to Analog Output (Figure 1) RL=200kΩ, VEE=GND=0 5 10 15 60 30 20 60 30 20 70 40 30 ns tPHL1(tPLH1) Maximum Propagation Delay , Channel-Select Input to Analog Output (Figure 1) RL=200 kΩ, VEE=GND=0 5 10 15 350 200 160 350 200 160 400 250 200 ns tPZL1(tPZH1) Maximum Propagation Delay , Channel-Select Input to Analog Output (Figure 2) RL=10 kΩ VEE=GND=0 5 10 15 720 320 240 720 320 240 720 320 240 ns VEE=-5Â, GND=0 5 450 450 450 Maximum Propagation Delay , Enable to Analog Output (Figure 2) RL=10 kΩ VEE=GND=0 5 10 15 720 320 240 720 320 240 720 320 240 VEE=-10Â, GND=0 5 400 400 400 Maximum Propagation Delay , Channel-Select Input to Analog Output (Figure 2) RL=10 kΩ VEE=GND=0 5 10 15 720 320 240 720 320 240 720 320 240 VEE=-5Â, GND=0 5 450 450 450 Maximum Propagation Delay , Enable to Analog Output (Figure 2) RL=1,0 kΩ VEE=GND=0 5 10 15 450 210 160 450 210 160 450 210 160 VEE=-10Â, GND=0 5 300 300 600 - - 7.5 - pF CIS 5 - 5* - pF COS 5 - 9* - Feedthrough CIOS 5 - 0.2* - tPZL2(tPZH2) tPLZ1(tPHZ1) tPLZ2(tPHZ2) CIN Maximum Input Capacitance, Channel-Select or Enable Inputs CI/O Maximum Capacitance VEE=GND=-5V INTEGRAL ns ns ns 5 IW4053B ADDITIONAL APPLICATION CHARACTERISTICS VCC Symbol BW Parameter Maximum OnChannel Bandwidth or Minimum Frequency Response (-3db) Test Conditions VEE=GND=0 RL=1kΩ 20 log(VOS/VIS)=-3db VOS at Common OUT/IN VOS at Any Channel f1 (-40db) Feedthrough Frequency (All Channels OFF) VEE=GND=0 RL=1kΩ 20 log(VOS/VIS)=-40db VOS at Common OUT/IN VOS at Any Channel f2 (-40db) Signal Crosstalk Frequency VIS** VEE=GND=0 RL=1kΩ 20 log(VOS/VIS)=-40db Between any 2 Sections : In Pin 2, Out Pin 14 In Pin 15, Out Pin 14 Limits Typical Value Unit V V 25 °C 10 2,5 30 10 2,5 60 10 2,5 8 10 2,5 8 10 10 2,5 2,5 2.5 6 MHz MHz MHz THD Total Harmonic Distortion VEE=GND=0 fIS=1kHz sine wave 5 10 15 1 1,5 2,5 0.3 0.2 0.12 % VAO/I Address-or Enable to Signal Crosstalk VEE=GND=0, RL=10kΩ*** tr,t f=20ns Square Wave 10 - 65 mV (Peak) ** Peak-to-peak voltage symmetrical about (VCC-VEE)/2. *** Both ends of channel. INTEGRAL 6 IW4053B VCC 50% INPUT GND tPLH t PHL 50% 10% ANALOG OUT VCC 90% GND t TLH t THL Figure 1. Switching Waveforms tr ENABLE CHANNEL-SELECT 10% INPUT tPLZ tf 90% 50% VCC 50% GND t PZL VCC 90% 10% VOL 90% VOH ANALOG OUT 10% t PHZ GND t PZH Figure 2. Switching Waveforms EXPANDED LOGIC DIAGRAM IN / OUT Ucc 16 BINARY 1 OF 2 DECODERS WITH ENABLE LOGIC LEVEL CONVERSION A 11 3 B 10 5 1 2 13 12 TG TG OUT/IN TG TG C 9 14 15 OUT/IN TG TG 6 4 OUT/IN ENABLE 8 GND 7 INTEGRAL VEE 7 IW4053B CHIP PAD DIAGRAM 1.95 + 0.03 1.8 + 0.03 15 14 13 Chip marking 204053 12 11 10 16 09 08 01 03 04 05 06 07 02 (0,0) Location of marking (mm): left lower corner x=1.361, y=1.592; right higher corner x=1.423, y=1.652. Chip thickness: 0.46±0.02mm PAD LOCATION Pad No Pin No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 Location (left lower corner), mm X Y 0.116 0.453 0.116 0.175 0.362 0.116 0.669 0.116 1.074 0.116 1.287 0.115 1.699 0.290 1.699 0.620 1.699 0.973 1.700 1.268 1.640 1.583 1.063 1.583 0.756 1.583 0.429 1.583 0.116 1.445 0.116 0.942 Pad size, mm 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 Note: Pad location is given as per passivation layer INTEGRAL 8