ETC OV6130

Advanced Information
Preliminary
OV6630/OV6130
OV6630 SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA
OV6130 SINGLE-CHIP CMOS CIF B&W DIGITAL CAMERA
Features
Frame exposure/line exposure option
3.3-Volt operation, low power dissipation
- < 20 mA active power
101,376 pixels, 1/4” lens, CIF/QCIF format
Progressive scan read out
Data format - YCrCb 4:2:2, GRB 4:2:2, RGB Raw Data
8/16 bit video data: ITU-601, ITU-656, ZV port
Wide dynamic range, anti-blooming, zero smearing
Electronic exposure/gain/white balance control
Image enhancement - brightness, contrast, gamma,
saturation, sharpness, window, etc.
Internal/external synchronization
- < 10 µA in power-save mode
Gamma correction (0.45/0.55/1.00)
2
I C programmable (400 kb/s):
- Color saturation, brightness, contrast, white balance,
exposure time, gain
General Description
smearing, and drastically reduce blooming. All needed camera
functions including exposure control, gamma, gain, white
balance, color matrix, windowing, and more, are programmable
2
through an I C interface. Both devices can be programmed to
provide image output in 4-bit, 8-bit or 16-bit digital formats.
ASUB
HVDD
FREX
AGCEN
RESET
SVDD
SGND
MULT
SDA
SCL
DEVDD
DEGND
6
5
4
3
2
1
48
47
46
45
44
43
The OV6630 (color) and OV6130 (black and white) CMOS Image sensors are single-chip video/imaging camera devices
designed to provide a high level of functionality in a single,
small-footprint package. Both devices incorporate a 352 x 288
image array capable of operating up to 60 frames per second
image capture. Proprietary sensor technology utilizes advanced
algorithms to cancel Fixed Pattern Noise (FPN), eliminate
Applications include: Video Conferencing, Video Phone, Video
Mail, Still Image, and PC Multimedia.
AGND
7
42
CHSYNC/BW
AVDD
8
41
V0/CBAR
PWDN
9
40
Y1
VRCAP1
10
39
Y2/G2X
VcCHG
11
38
Y3/RGB
IICB
12
37
Y4/CS1
VTO
13
36
Y5/SHARP
ADVDD
14
35
Y6/CS2
ADGND
15
34
Y7/CS0
VSYNC/CSYS
FODD/CLK
16
33
PCLK/PWDB
17
32
DOVDD
HREF/VSFRAM
18
31
DOGND
OV6630/
OV6130
30
29
28
27
26
25
24
23
22
21
20
19
DGND
DVDD
XCLK2
XCLK1
UV1/CC656
UV0/GAMMA
UV2/QCIF
UV3
UV4
UV5/MIR
UV6/ABKEN
UV7/B8
Array Element(CIF)
(QCIF)
356x292
(176x144)
Pixel Size
Image Area
Max Frames/Sec
Electronics
Exposure
Scan Mode
Gamma Correction
Min. Illumination
(3000K)
S/N Ration
9µm x 8.2µm
3.1mm x 2.5mm
Up to 60 FPS
Up to 500:1 (for selected
FPS)
Progressive
0.45/0.55/1.0
OV6630 - < 3lux @ f1.2
OV6130 - < 0.5lux @ f1.2
> 48 dB
(AGC off, Gamma=1)
< 0.03% VPP
< 0.2nA/cm2
> 72 dB
2.7−3.6VDC
5VDC/3.3VDC (DIO)
< 20mA active
< 10µA Standby
48 pin LCC
FPN
Dark Current
Dynamic Range
Power Supply
Power
Requirements
Package
Figure 1. OV6630/OV6130 Pin Assignments
Note: Outputs UV0-UV7 are not available on the OV6130. The inputs associated
with these respective pins are still functional.
OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94086 U.S.A.
Tel: (408) 733-3030 Fax: (408) 733-3061
e-mail: [email protected]
Website: http://www.ovt.com
Version 1.0, March 4, 2000
SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
Table 1. Pin Description
Pin No.
01
02
Name
SVDD
RESET
Pin Type
VIN
Function
(Default=0)
Function
(Default=0)
03
AGCEN
04
FREX
Function
(Default=0)
05
06
07
08
09
HVDD
ASUB
AGND
AVDD
PWDN
VREF (4V)
VIN
VIN
VIN
Function
(Default=0)
10
11
12
VRCAP1
VCCHG
IICB
VREF (1.5V)
VREF (2.7V)
Function
(Default=0)
13
14
15
16
17
18
19
VTO
ADVDD
ADGND
VSYNC/CSYS
FODD/CLK
HREF/VSFRAM
*
UV7/B8
O
VIN
VIN
I/O
I/O
I/O
I/O
20
*
I/O
21
*
I/O
22
*
I/O
23
*
I/O
24
*
I/O
25
*
I/O
26
*
I/O
27
28
29
30
31
32
33
34
35
36
37
38
XCLK1
XCLK2
DVDD
DGND
DOGND
DOVDD
PCLK/PWDB
Y7/CS0
Y6/CS2
Y5/SHARP
Y4/CS1
Y3/RGB
I
O
VIN
VIN
VIN
VIN
I/O
I/O
I/O
I/O
I/O
I/O
UV6/ABKEN
UV5/MIR
UV4
UV3
UV2/QCIF
UV1/CC656
UV0/GAMMA
March 4, 2000
Function/Description
Array power (+3.3VDC)
Chip reset, active high
Automatic Gain Control (AGC) selection
“0” – Disable AGC
“1” – Enable AGC
Note: This function is disabled when OV6630/OV6130 sensor is configured in I2C mode.
Frame exposure control
“0” – Disable frame exposure control
“1” – Enable frame exposure control
Charge pump voltage. Connect to ground through 10µF capacitor.
Analog substrate voltage.
Analog ground
Analog power supply (+3.3VDC)
Power down mode selection.
“0” – Normal mode.
“1” – Power down mode.
Array reference. Connect to ground through 0.1µF capacitor.
Internal voltage reference. Connect to ground through 1µF capacitor.
I2C enable selection.
“0” – Enable I2C
“1” – Enable auto-control mode
Luminance composite signal output (black/white in PAL standard).
Analog power supply (+3.3VDC)
Analog signal ground
Vertical sync output. At power up, read as CSYS.
Field ID FODD output or main clock output
HREF output. At power up, read as VSFRAM
Bit 7 of U video component output. At power up, sampled as B8.
* Note: Output UV7 is not available on the OV6130 sensor.
Bit 6 of U video component output. At power up, sampled as ABKEN.
* Note: Output UV6 is not available on the OV6130 sensor.
Bit 5 of U video component output. At power up, sampled as MIR.
* Note: Output UV5 is not available on the OV6130 sensor.
Bit 4 of U video component output.
* Note: Output UV4 is not available on the OV6130 sensor.
Bit 3 of U video component output.
* Note: Output UV3 is not available on the OV6130 sensor.
Bit 2 of U video component output. At power up, sampled as QCIF.
* Note: Output UV2 is not available on the OV6130 sensor.
Bit 1 of U video component output. At power up, sampled as CC656.
* Note: Output UV1 is not available on the OV6130 sensor.
Bit 0 of U video component output. At power up, sampled as GAMMA.
* Note: Output UV0 is not available on the OV6130 sensor.
Crystal clock input
Crystal clock output
Digital power supply (+3.3VDC)
Digital ground
Digital interface output buffer ground
Digital interface output buffer power supply (+3.3VDC or 5VDC)
PCLK output. At power up sampled as PWDB.
Bit 7 of Y video component output. At power up, sampled as CS0.
Bit 6 of Y video component output. At power up, sampled as CS2.
Bit 5 of Y video component output. At power up, sampled as SHAPR.
Bit 4 of Y video component output. At power up, sampled as CS1.
Bit 3 of Y video component output. At power up, sampled as RGB.
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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
39
40
41
42
43
44
45
46
47
Y2/G2X
Y1
Y0/CBAR
CHSYNC/BW
DEGND
DEVDD
SCL
SDA
MULT
I/O
I/O
I/O
I/O
VIN
VIN
I
I/O
Function
(Default=0)
48
SGND
VIN
1
Bit 2 of Y video component output. At power up, sampled as G2X.
Bit 1 of Y video component output.
Bit 0 of Y video component output. At power up, sampled as CBAR.
CHSYNC output. At power up, sampled as BW.
Decoder ground.
Decoder power supply (+3.3VDC)
I2C serial interface clock input.
I2C serial interface data input and output.
I2C slave selection
“0” – Select single slave ID.
“1” – Enable multiple (8) slaves.
Array ground
Function Description
(Note: References to color features do not apply to the OV6130 B&W Digital Image Sensor.)
Overview
The OV6630/OV6130 sensor is a ¼ inch CMOS imaging device. The
sensor contains approximately 101,376 pixels. Its design is based on a
field integration read-out system with line-by-line transfer and an
electronic shutter with a synchronous pixel read out scheme. The
color filter of the sensor consists of a primary color RG/GB array
arranged in line-alternating fashion.
DENB
GAMMA
Referring to Figure 2 below, the OV6630 sensor includes a 356 x 292
resolution image array, an analog signal processor, dual 8-bit A/D
converters, analog video multiplexer, digital data formatter, video
port, I2C interface, registers, and digital controls that include timing
block, exposure control, black level control, and white balance.
R
G
B
MUX
A/D
MUX
A/D
Analog
Processing
Y
Cb
Cr
Row Select
Column Sense Amp
Exposure
Detect
UV[7:0]
WB
Detect
(356x292)
Image Array
registers
Video Timing
Generator
WB
Control
I2C
Interface
IICB
SDA
SCL
AWBTH/
AWBTM
FZEX
AGCEN
PROG
MIR
CHSYNC
FODD
VSYNC
PCLK
HREF
Exposure
Control
AWB
1/2
XCLK1
Y[7:0]
Video port
VTO
Formatter
1.1
Figure 2. OV6630/OV6130 CMOS Image Sensor Block Diagram
March 4, 2000
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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
1.2
Analog Processor Circuits
1.2.1
Overview
The image is captured by the 356 x 292 pixel image array and routed
to the analog processing section where the majority of signal
processing occurs. This block contains the circuitry that performs
color separation, color correction, automatic gain control (AGC),
gamma correction, color balance, black level calibration, “knee”
smoothing, aperture correction, controls for picture luminance and
chrominance, and anti-alias filtering. The analog video signals are
based on the following formula:
Y = 0.59G + 0.31R + 0.11B
U=R–Y
V=B–Y
Where R,G,B are the equivalent color components in each
pixel.
1.2.2
Image Processing
The algorithm used for the electronic exposure control is based on the
brightness of the full image. The exposure is optimized for a “normal”
scene that assumes the subject is well lit relative to the background. In
situations where the image is not well lit, the automatic exposure
control (AEC) white/black ratio may be adjusted to suit the needs of
the application.
Additional on-chip functions include
⇒
AGC that provides a gain boost of up to 24dB
⇒
White balance control that enables setting of proper color
temperature and can be programmed for automatic or manual
operation.
⇒
Separate saturation, brightness, contrast, and sharpness
adjustments allow for further fine-tuning of the picture quality
and characteristics.
YCrCb format is also supported, based on the formula below:
The OV6630 image sensor also provides control over the White
Balance ratio for increasing/decreasing the image field Red/Blue
component ratio. The sensor provides a default setting that may be
sufficient for many applications.
Y = 0.59G + 0.31R + 0.11B
Cr = 0.713 (R – Y)
Cb = 0.564 (B – Y)
The YCrCb/RGB data signal from the analog processing section is
fed to two on-chip 8-bit analog-to-digital (A/D) converters: one for
the Y/RG channel and one shared by the CrCb/BG channels. The
converted data stream is further conditioned in the digital formatter.
The processed signal is delivered to the digital video port through the
video multiplexer which routes the user-selected 16-, 8-, or 4-bit
video data to the correct output pins.
The on-chip 8-bit A/D operates up to 9 MHz, and fully synchronous
to the pixel rate. Actual conversion rate is related to the frame rate.
A/D black-level calibration circuitry ensures:
⇒
The black level of Y/RGB is normalized to a value of 16
⇒
The peak white level is limited to 240
⇒
CrCb black level is 128
⇒
CrCb Peak/bottom is 240/16
⇒
RGB raw data output range is 16/240
1.2.3
Windowing
The windowing feature of the OV6630/OV6130 image sensors allows
user-definable window sizing as required by the application. Window
size setting (in pixels) ranges from 2 x 2 to 356 x 292, and can be
positioned anywhere inside the 356 x 292 boundary. Note that
modifying window size and/or position does not change frame or data
rate. The OV6630/OV6130 imager alters the assertion of the HREF
signal to be consistent with the programmed horizontal and vertical
region. The default output window is 352 x 288.
1.2.4
Zoom Video Port (ZV)
The OV6630/OV6130 image sensor includes a Zoom Video (ZV)
function that supports standard ZV Port interface timing. Signals
available include VSYNC, CHSYNC, PCLK and 16-bit data bus:
Y[7:0] and UV[7:0]. The rising edge of PCLK clocks data into the ZV
port. See Figure 3. Zoom Video Port Timing below.
(Note: Values 0 and 255 are reserved for sync flag)
March 4, 2000
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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
Even Field 1 (FODD=0)
Odd Field 1 (FODD=1)
VSYNC
t8
t8
HREF
t6
t7
t5
t4
PCLK
t1
t3
t2
Y[7:0]/UV[7:0]
1
2
351
352
Valid Data
Horizontal Timing
VSYNC
1 Line
TVS
TVE
Y[7:0]/UV[7:0]
TLINE
Vertical Timing
Figure 3. Zoom Video Port Timing
Notes:
1.
Zoom Video Port format output signal includes:
VSYNC: Vertical sync pulse.
HREF: Horizontal valid data output window.
PCLK: Pixel clock used to clock valid data and CHSYNC into Zoom V Port. Default frequency is 8.86MHz when use
17.73MHz as system clock. Rising edge of PCLK is used to clock the 16 Bit data.
Y[7:0]: 8 Bit luminance data bus.
UV[7:0]: 8 Bit chrominance data bus.
2.
All timing parameters are provided in Table 13. Zoom Video Port AC Parameters.
1.2.5
QCIF Format
A QCIF mode is available for applications where higher resolution
image capture is not required. Only half of the pixel rate is required
when programmed in this mode. Default resolution is 176 x 144
pixels and can be programmed for other resolutions. Refer to Table 7.
QCIF Digital Output Format (YUV beginning of line) and Table 8.
QCIF Digital Output Format (RGB raw data beginning of line) for
further information.
March 4, 2000
1.2.6
Video Output
The video output port of the OV6630/OV6130 image sensors
provides a number of output format/standard options to suit many
different application requirements. Table 2. Digital Output Format,
below, indicates the output formats available. These formats are user
programmable through the I2C interface (See I2C Bus Protocol
Format).
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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
– UV channel output sequence is B G B G
The OV6630/OV6130 imager supports both ITU-601 and ITU-656
output formats in the following configurations (See Table 3. 4:2:2 16bit Format for further details):
The video output appears in Y channel only and the UV channel is
disabled in 8-bit RGB raw data. The output sequence is B G R G.
- 16-bit, 4:2:2 format
In RGB raw data ITU-656 modes, the OV6630/OV6130 imager
asserts SAV (Start of Active Video) and EAV (End of Active Video)
to indicate the beginning and the ending of HREF window. As a
result, SAV and EAV change with the active pixel window. The 8-bit
RGB raw data is also accessible without SAV and EAV information.
(This mode complies with the 60/50 Hz ITU-601 timing
standard. See Table 3. 4:2:2 16-bit Format below)
- 8-bit data mode
(In this mode, video information is output in Cb Y Cr Y
order using the Y port only and running at twice the pixel
rate during which the UV port is inactive. See Table 4. 4:2:2
8-bit Format below)
The OV6630/OV6130 imager offers flexibility in YUV output format.
The device may be programmed as standard YUV 4:2:2. The device
may also be configured to “swap” the U V sequence. When swapped,
the UV channel output sequence in the 16-bit configuration becomes:
- 4-bit nibble mode
- V U V U···.
(In the nibble mode, video output data appears at bits Y4Y7. The clock rate for the output runs at twice the normal
output speed when in B/W mode, and 4 times the normal
output speed in when in color mode.)
The 8-bit configuration becomes:
- V Y U Y···.
The third format available in the 8-bit configuration is the Y/UV
sequence swap:
- 704 x 288 format
(When programmed in this mode, the pixel clock is doubled
and the video output sequence is Y0Y0Y1Y1 ··· and
U0U0V0V0 ···. See Figure 4. Pixel Data Bus (YUV Output)
below.)
- Y U Y V···.
The single-chip camera can be configured for use as a black and white
image device. The vertical resolution is higher than in color mode.
Video data output is provided at the Y port and the UV port is tristated. The data (Y/RGB) rate is equivalent to 16-bit in color mode.
The OV6630/OV6130 imager provides VSYNC, HREF, PCLK,
FODD, and CHSYNC as standard output video timing signals.
The MSB and LSB of Y/UV or RGB output can be reversed. Y7 is
MSB and Y0 is LSB in the default setting. Y7 becomes LSB and Y0
becomes MSB in the reserve order configuration. Y2-Y6 are also
reversed appropriately.
The OV6630/OV6130 imager can also be programmed to provide
RGB raw data in 16-bit, 8-bit, and 4-bit format. The output sequence
is matched to the OV6630 color filter pattern (See Figure 5. Pixel
Data Bus (RGB Output) below):
– Y channel output sequence is G R G R
Table 2. Digital Output Format
Resolution
YUV 4:2:2
RGB
Y/UV swap2
U/V swap
YG
One Line
MSB/LSB swap
Pixel Clock
16-bit
8-bit
ITU-656
Nibble
16-bit
8-bit
ITU-6561
Nibble
16-bit
8-bit
YUV3
RGB4
16-bit
8-bit
16-bit
8-bit
352 x 288
Y
Y
Y
Y
Y
Y
Y
Y
704 x 288
Y
Y
Y
Y
Y
Y
Y
Y
176 x 144
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Note:
(“Y” indicates mode/combination is supported by OV6630/OV6130)
1. Output is 8-bit in RGB ITU-656 format. SAV and EAV are inserted at the beginning and ending of HREF, which
synchronize the acquisition of VSYNC and HSYNC. 8-bit data bus configuration (without VSYNC and
CHSYNC) can provide timing and data in this format.
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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
2. Y/UV swap is valid in 8-bit only. Y channel output sequence is Y U Y V ···
3. U/V swap means UV channel output sequence swap in YUV format, i.e., V U V U ··· for 16 bit and V Y U Y
··· for 8-bit.
4. U/V swap means neighbor row B R output sequence swap in RGB format. Refer to RGB raw data output format
for further details.
Table 3. 4:2:2 16-bit Format
Data Bus
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
UV7
UV6
UV5
UV4
UV3
UV2
UV1
UV0
Pixel Byte Sequence
Y7
Y7
Y6
Y6
Y5
Y5
Y4
Y4
Y3
Y3
Y2
Y2
Y1
Y1
Y0
Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
UV7
UV6
UV5
UV4
UV3
UV2
UV1
UV0
UV7
UV6
UV5
UV4
UV3
UV2
UV1
UV0
UV7
UV6
UV5
UV4
UV3
UV2
UV1
UV0
1
2
Y Frame
UV Frame
0
0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
UV7
UV6
UV5
UV4
UV3
UV2
UV1
UV0
UV7
UV6
UV5
UV4
UV3
UV2
UV1
UV0
UV7
UV6
UV5
UV4
UV3
UV2
UV1
UV0
3
4
2
5
4
Table 4. 4:2:2 8-bit Format
Data Bus
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y Frame
UV Frame
March 4, 2000
U7
U6
U5
U4
U3
U2
U1
U0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
V7
V6
V5
V4
V3
V2
V1
V0
0
Pixel Byte Sequence
Y7
U7
Y6
U6
Y5
U5
Y4
U4
Y3
U3
Y2
U2
Y1
U1
Y0
U0
1
2
01
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
V7
V6
V5
V4
V3
V2
V1
V0
3
23
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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
TCLK
PCLK
THD
TSU
HREF
Y[7:0]
UV[7:0]
10
Y
Y
10
80
U
V
80
Repeat for all data bytes
Pixel Data 16-bit Timing
(PCLK rising edge latches data bus)
TCLK
PCLK
THD
TSU
HREF
Y[7:0]
10
80
10
U
Y
V
Y
80
10
Repeat for all data bytes
Pixel Data 8-bit Timing
(PCLK rising edge latches data bus)
Note: TCLK is pixel clock period.. TCLK=112ns for 16-bit output and TCLK=56ns for 8-bit output if the system
clock is 17.73MHz. TSU is the setup time of HREF. The maximum is 15ns. THD is the hold time of HREF.
The maximum is 15ns.
Figure 4. Pixel Data Bus (YUV Output)
March 4, 2000
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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
TCLK
PCLK
THD
TSU
HREF
Y[7:0]
UV[7:0]
10
G
R
10
10
B
G
10
Repeat for all data bytes
Pixel Data 16-bit Timing
(PCLK rising edge latches data bus)
TCLK
PCLK
THD
TSU
HREF
Y[7:0]
10
10
10
B
G
R
G
10
10
Repeat for all data bytes
Pixel Data 8-bit Timing
(PCLK rising edge latches data bus)
Note: TCLK is pixel clock period.. TCLK=112ns for 16-bit output and TCLK=56ns for 8-bit output if the system
clock is 17.73MHz. TSU is the setup time of HREF. The maximum is 15ns. THD is the hold time of HREF.
The maximum is 15ns.
Figure 5. Pixel Data Bus (RGB Output)
March 4, 2000
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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
The default U/UV channel output port relation before MSB/LSB swap
Table 5. Default Output Sequence
Output port
Internal output data
MSB
Y7
Y7
Y6
Y6
Y5
Y5
Y4
Y4
Y3
Y3
Y2
Y2
Y1
Y1
LSB
Y0
Y0
Y5
Y2
Y4
Y3
Y3
Y4
Y2
Y5
Y1
Y6
LSB
Y0
Y7
6
Y5
U5, V5
7
Y6
U6, V6
The relation after MSB/LSB swap changes to
Table 6. Swapped MSB/LSB Output Sequence
Output port
Internal output data
MSB
Y7
Y0
Y6
Y1
Table 7. QCIF Digital Output Format (YUV beginning of line)
Pixel #
Y
UV
1
Y0
U0, V0
2
Y1
U1, V1
3
Y2
U2, V2
4
Y3
U3, V3
5
Y4
U4, V4
8
Y7
U7, V7
- Y channel output Y2 Y3 Y6 Y7 Y10 Y11 ···
- UV channel output U2 V3 U6 V7 U10 V11 ···
- Half (176 pixels) data are outputted every line and only half line data (every other line, total 144 lines) in one frame.
Table 8. QCIF Digital Output Format (RGB raw data beginning of line)
Pixel #
Line 1
Line 2
1
B0
G0
2
G1
R1
3
B2
G2
4
G3
R3
1. Default RGB two line output mode:
– Y channel output G0 R1 G4 R5 G8 R9 ···
– UV channel output B0 G1 B4 G5 B8 G9 ···
– Every line output half data (176 pixels) and all lines (144
lines) data in one frame will be output.
2. YG two line output mode:
- Y channel output G0 R1 G4 R5 G8 R9 ···
- UV channel output B0 G1 B4 G5 B8 G9 ···
5
B4
G4
6
G5
R5
7
B6
G6
8
G7
R7
- Every line outputs half data (176 pixels) and all lines (144
lines) data in one frame will be output.
3. QCIF Resolution Digital Output Format
- Y channel output Y2 Y3 Y6 Y7 Y10 Y11 ···
- UV channel output U2 V3 U6 V7 U10 V11···
- Every line output data number is half (176 pixels) and only one
half line data (every other line, total 144 lines) in one frame will
be output.
Table 9. RGB Raw Data Format
R\C
1
2
3
4
1
B1,1
G2,1
B3,1
G4,1
2
G1,2
R2,2
G3,2
R4,2
3
B1,3
G2,3
B3,3
G4,3
4
G1,4
R2,4
G3,4
R4,4
289
290
291
292
B289,1
G290,1
B291,1
G292,1
G289,2
R290,2
G291,2
R292,2
B289,3
G290,3
B291,3
G292,3
G289,4
R290,4
G291,4
R292,4
···
353
B1,353
G2,353
B3,353
G4,353
354
G1,354
R2,354
G3,354
R4,354
355
B1,355
G2,355
B3,355
G4,355
356
G1,356
R2,356
G3,356
R4,356
B289,353
G290,353
B291,353
G292,353
G289,354
R290,354
G291,354
R292,354
B289,355
G290,355
B291,355
G292,355
G289,356
R290,356
G291,356
R292,356
Notes:
A. Y port output data sequence: G R G R G R ··· or G G G G ···; UV port output data sequence: B G B G B G ··· or B R B R ···; and
the array color filter pattern is Bayer-Pattern.
B. Output Modes
1. 16-bit Format (Total 292 HREFs)
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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
Default mode:
- 1st HREF Y channel output unstable data, UV output B11 G12 B13 G14 ···
- 2nd HREF Y channel output G21 R22 G23 R24 ···, UV output B11 G12 B13 G14 ···
- 3rd HREF Y channel output G21 R22 G23 R24 ···, UV output B31 G23 B33 G34 ···
- Every line of data is output twice.
YG mode:
- 1st HREF Y and UV output unstable data.
- 2nd HREF Y channel output G21 G12 G23 G14 ···, UV output B11 R22 B13 R24 ···
- 3rd HREF Y is G21 G32 G23 G34 ···, UV channel is B31 R22 B33 R24 ···
- Every line data output twice.
One line mode:
- 1st HREF Y channel output B11 G12 B13 G14 ···
- 2nd HREF Y channel output G21 R22 G23 R24 ···
- UV channel tri-state.
2. 8-bit Format (Total 292 HREFs)
- 1st HREF Y channel output unstable data.
- 2nd HREF Y channel output B11 G21 R22 G12 ···
- 3rd HREF Y channel output B31 G21 R22 G32 ···
- PCLK timing is doubled and PCLK rising edge latch data bus. UV channel tri-state. Every line data output twice.
3. 4-bit Nibble Mode Output Format
- Uses higher 4 bits of Y port (Y[7:4]) as output port.
- Supports YCrCb/RGB data, ITU-601/ITU-656 timing, Color/B&W.
- Output sequence: High order 4 bits followed by lower order 4 bits
Y0H Y0L Y1H Y1L ···
U0H U0L V0H V0L ···
For B/W or one-line RGB raw data, the output data clock speed is doubled. For color YUV, output clock is four times that of the 16-bit
output data. In color mode, sensor must be set to 8-bit mode, and the nibble timing, clock divided by 2.
Output sequence: U0H U0L Y0H Y0L V0H V0L Y1H Y1L ···
1.2.7
Slave Mode Operation
The OV6630/OV6130 can be programmed to operate in slave mode
(COMI[6] = 1, default is master mode). HSYNC and VSYNC output
signals are provided.
When used as a slave device, the external master must provide the
following clocks to OV6630/OV6130 imager:
1. System clock CLK to XCLK1 pin
2. Horizontal sync, HSYNC, to CHSYNC pin, positive assertion
3. Vertical frame sync, VSYNC, to VSYNC pin, positive assertion
In slave mode, the OV6630/OV6130 tri-states CHSYNC (pin 42) and
VSYNC (pin 16) output pins, and used as input pins. To synchronize
multiple devices, OV6630/OV6130 uses external system clock, CLK,
to synchronize external horizontal sync, HSYNC, which is then used
to synchronize external vertical frame sync, VSYNC. See Figure 6.
Slave Mode External Sync Timing for timing considerations.
1.2.8
Frame Exposure Mode
OV6630/OV6130 supports frame. FREX (pin 4) is asserted by an
external master device to set exposure time. The pixel array is quickly
pre-charged when FREX is set to “1”. OV6630/OV6130 captures the
image in the time period when FREX remains high. The video data
stream is delivered to output port in a line-by-line manner after FREX
switches to “0”.
March 4, 2000
It should be noted that FREX must remain high long enough to ensure
the entire image array has been pre-charged.
When data is being output from OV6630/OV6130, care must be taken
so as not to expose the image array to light. This may affect the
integrity of the image data captured. A mechanical shutter synchronized with the frame exposure rate can be used to minimize this
situation. The timing of frame exposure is shown in Figure 7. Frame
Exposure Timing below.
1.2.9
Reset
OV6630/OV6130 includes a RESET pin (pin 2) that forces a
complete hardware reset when it is pulled high (VCC).
OV6630/OV6130 clears all registers and resets to their default values
when a hardware reset occurs. Reset can also be initiated through the
I2C interface.
1.2.10 Power Down Mode
Two methods are available to place OV6630/OV6130 into powerdown mode: hardware power down and I2C software power down.
To initiate hardware power down, the PWDN pin (pin 9) must be tied
to high (+3.3VDC). When this occurs, OV6630/OV6130 internal
device clock is halted and all internal counters are reset. The current
draw is less than 10µA in this standby mode.
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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
Executing a software power down through the I2C interface suspends
internal circuit activity, but does not halt the device clock. The current
requirements drop to less than 1mA in this mode.
specified pins. Not all device functions are available for configuration
through external pins. Power up pin programming occurs in 1024
system clock cycles.
1.2.11 Configure OV6630/OV6130
Two methods are provided to configure OV6630/OV6130 for specific
application requirements.
A more flexible and comprehensive method to configure
OV6630/OV6130 is to use its on-chip I2C register programming
capability. The I2C interface provides access to all of the device’s
programmable internal registers. See I2C Bus Protocol Format for
further details about using the I2C interface on the OV6630/OV6130
camera device.
At power up, OV6630/OV6130 reads the status of certain pins to
determine what, if any, power up pin programming default settings
are requested. Once the reading of the external pins status is
completed, the device configures its internal registers according to the
TCLK
CLK
THS
HSYNC
1 Line=472 TCLK
VSYNC
1 Frame=625 x 472 TCLK
TVS
Notes:
THS > 6 TCLK (2), THS < TVS < 472 TCLK
HSYNC period is (472 TCLK)
VSYNC period is (625 x 472 TCLK)
OV6630/OV6130 will be stable after 1 field (2nd VSYNC)
Figure 6. Slave Mode External Sync Timing
March 4, 2000
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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
Mechanical Shutter Off
FREX
TSET
TIN
THS
HSYNC
Precharge begins at the rising edge of HSYNC
ARRAY
PRECHARGE
DATA
OUTPUT
TPR
Array Exposure Period TEX
Array Precharge Period TPR
1 Frame (292 Lines) Valid Data
Invalid Data
Black Data
THD Head of Valid Data (8 Lines)
Next Frame
VSYNC
HREF
Note:
TPR=292 x 4 x TCLK. TCLK is internal pixel period. TCLK=112ns if the system clock is 17.73MHz. TCLK will
increase with the clock divider CLK[5:0].
TEX is array exposure time which is decided by external master device.
TIN is uncertain time due to the using of HSYNC rising edge to synchronize FREX. TIN < THS.
There are 8 lines data output before valid data after FREX=0. THD=4 THS. Valid data is output when
HREF=1.
TSET=TIN + TPR + TEX. TSET > TPR + TIN. The exposure time setting resolution is THS (one line) due to the
uncertainty of TIN.
Figure 7. Frame Exposure Timing
March 4, 2000
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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
March 4, 2000
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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
2
Electrical Characteristics
Table 10. DC Characteristics (0°°C ≤ TA ≤ 85°°C, Voltages referenced to GND)
Symbol
Supply
VDD1
VDD2
Descriptions
Supply voltage
(DEVDD, ADVDD, AVDD, SVDD, DVDD)
Supply voltage (DOVDD)
IDD1
Supply current
(@50Hz frame rate and 3.3V digital I/O with 25pF plus 1TTL loading
on 16-bit data bus)
IDD2
Supply current
(VDD=3V, @50Hz frame rate without digital I/O loading, 2 ports
output, and without internal charge pump)
IDD3
Standby supply current
Digital Inputs
VIL
Input voltage LOW
VIH
Input voltage HIGH
CIN
Input capacitor
Digital Outputs (standard loading 25pF, 1.2KΩ to 3V)
VOH
Output voltage HIGH
VOL
Output voltage LOW
I2C Input (5KΩ pull up + 100pF)
VIL
SDA and SCL (VDD2=5V)
VIH
SDA and SCL (VDD2=5V)
VIL
SDA and SCL (VDD2=3V)
VIH
SDA and SCL (VDD2=3V)
Max
Typ
Min
Units
3.6
3.3
2.7
V
5.5
3.6
40
5
3.3
4.5
2.7
V
10
mA
12
mA
5
µA
0.8
2
10
V
V
PF
2.4
V
V
0.6
1.5
VDD+0.5
1
VDD+0.5
3.3
0
3
-0.5
3.0
-0.5
2.5
V
V
V
V
Max
Typ
Min
Units
Table 11. AC Characteristics (TA=25°°C, VDD=3V)
Symbol
Descriptions
RGB/YCrCb Output
ISO
Maximum sourcing current
VY
DC level at zero signal
YPP 100% amplitude (without sync)
Sync amplitude
ADC Parameters
B
Analog bandwidth
ΦDIFF
DLE
DC differential linearity error
ILE
DC integral linearity error
15
1.2
1
0.4
mA
V
MHz
0.5
1
LSB
LSB
Table 12. Timing Characteristics
Symbol
Descriptions
Oscillator and Clock Input
fOSC
Frequency (XCLK1, XCLK2)
tr , tf
Clock input rise/fall time
Clock input duty cycle
I2C Timing (400Kbit/s)
tBUF
Bus free time between STOP and START
tHD:SAT
SCL change after START status
tLOW
SCL low period
tHIGH
SCL high period
tHD:DAT
Data hold time
March 4, 2000
Version 1.0
Max
Typ
Min
Units
24
5
55
17.734
10
50
45
MHz
ns
%
1.3
0.6
1.3
0.6
0
ms
µs
µs
µs
µs
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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
tSU:DAT
Data setup time
tSU:STP
Setup time for STOP status
Digital Timing
tPCLK
PCLK cycle time
16-bit operation
8-bit operation
tr , tf
PCLK rise/fall time
tPDD
PCLK to data valid
tPHD
PCLK to HREF delay
15
15
20
10
0.1
0.6
µs
µs
112
56
ns
5
ns
ns
ns
Table 13. Zoom Video Port AC Parameters
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
Notes:
1.
2.
Parameter
PCLK fall time
PCLK low time
PCLK rise time
PCLK high time
PCLK period
Y/UV/HREF setup time
Y/UV/HREF hold time
VSYNC setup/hold time to HREF
Min
4ns
50ns
4ns
50ns
106ns
10ns
20ns
1µs
Max
8ns
8ns
In Interlaced Mode, there are even/odd field different (t8). When In Progressive Scan Mode, only frame timing same as Even
field(t8).
After VSYNC falling edge, OV6630 will output black reference level, the line number is TVS, which is the line number between the 1st HREF rising edge after VSYNC falling edge and 1st valid data CHSYNC rising edge. Then valid data, then
black reference, line number is TVE, which is the line number between last valid data CHSYNC rising edge and 1st CHSYNC
rising edge after VSYNC rising edge. The black reference output line number is dependent on vertical window setting.
3.
When in default setting, TVE = 14 × TLINE, which is changed with register VS[7:0]. VS[7:0] step equal to 1 line.
4.
When in default setting, TVE = 4 × TLINE for Odd Field, TVE = 3 × TLINE for Even Field, which is changed with register
VE[7:0]. VE[7:0] step equal to 1 line.
March 4, 2000
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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
+0.010
0.060 -0.005
0.440 ±0.005
0.040 ±0.003
31
42
0.040 ±0.007
TYP
43
30
48
Bottom View
0.020 ±0.008
TYP
19
R 0.0075
4 CORNERS
18
6
7
R 0.0075
48 PLCS
0.085 ±0.010
0.003
+0.012
0.560 SQ -0.005
0.003
0.065 ±0.007
0.036 MIN
0.430 SQ ±0.005
0.350 SQ ±0.005
42
31
0.030
±0.002
0.020 ±0.002
0.002
42
43
31
43
30
30
Side View
48
1
6
6
Top View
19
7
19
18
7
0.006 MAX
18
0.002 TYP
March 4, 2000
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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
Array Center
(10.9 mil, 13.2 mil)
(276.9 µm, 335.3 µm)
1
DIE
Sensor
Array
Package Center
(0, 0)
Table 14. Ordering Information
Part Number
OV6630
OV6130
Description
COLOR Image Sensor, CIF, Digital, I2C Bus Control
B/W Image Sensor, CIF, Digital, I2C Bus Control
Package
48 pin LCC
48 pin LCC
OmniVision Technologies, Inc. reserves the right to make changes without further notice to any product herein to improve reliability, function, or
design. OmniVision Technologies, Inc. does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. No part of this publication may be copied or reproduced, in any
form, without the prior written consent of OmniVision Technologies, Inc.
March 4, 2000
Version 1.0
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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
I2C Bus
3
Many of the functions and configuration registers in the
OV6630/OV6130 image sensors are available through the I2C
interface. The I2C port is enabled by asserting the I2CB line (pin 12)
through a 10KΩ resistor to VDD. When the I2C capability is enabled
(I2CB = 1), the OV6630/OV6130 imager operates as a slave device
that supports up to 400 KBps serial transfer rate using a 7-bit
address/data transfer protocol.
1ST BYTE
S
START
SLAVE ID (7BITS)
MSB
2ND BYTE
RW
A
SUB-ADDRESS (8BITS)
LSB=0
3RD BYTE
A
DATA (8BITS)
A
ACK
P
ACK STOP
MASTER TRANSMIT, SLAVE RECEIVE (WRITE CYCLE)
1ST BYTE
S
START
SLAVE ID (7BITS)
MSB
2ND BYTE
RW
A
SUB-ADDRESS (8BITS)
A
P
ACK STOP
LSB=0
MASTER TRANSMIT, SLAVE RECEIVE (DUMMY WRITE CYCLE)
1ST BYTE
S
START
SLAVE ID (7BITS)
MSB
2ND BYTE
RW
A
DATA (8BITS)
LSB=1
3RD BYTE
A
DATA (8BITS)
ACK
MASTER RECEIVE, SLAVE TRANSMIT (READ CYCLE)
SLAVE ID - 110CCC0X
CS2 (PIN 35)
1
S - START CONDITION
A - ACKNOWLEDGE BIT
P - STOP CONDITION
CS1 (PIN 37)
P
STOP
NO ACK IN
LAST BYTE
– SLAVE TRANSMIT
– MASTER TRANSMIT
– MASTER INITIATE
CS0 (PIN 34)
X - RW BIT, 1:READ, 0:WRITE
Figure 8. I2C Bus Protocol Format
3.1
I2C Bus Protocol Format
In I2C operation, the master must perform the following operations:
- Generate the start/stop condition
- Provide the serial clock on SCL
March 4, 2000
- Place the 7-bit slave address, the RW bit, and the 8-bit subaddress on SDA
The receiver must pull down SDA during the acknowledge period.
During the write cycle, OV6630/OV6130 returns acknowledge and,
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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
during read cycle, the master returns acknowledge except the read
data is the last byte. The master does not perform acknowledge if the
read data is the last byte, indicates that the slave can terminate the
read cycle. Note that the restart feature is not supported here.
Within each byte, MSB is always transferred first. Read/write control
bit is the LSB of the first byte.
Standard I2C communications require only two pins: SCL and SDA.
SDA is configured as open drain for bi-directional purpose. A HIGH
to LOW transition on the SDA while SCL is HIGH indicates a
START condition. A LOW to HIGH transition on the SDA while
SCL is HIGH indicates a STOP condition. Only a master can generate
START/STOP conditions.
Except for these two special conditions, the protocol that SDA remain
stable during the HIGH period of the clock, SCL. Each bit is allowed
to change state only when SCL is LOW (See Figure * and Figure 10
below).
The OV6630/OV6130 I2C supports multi-byte write and multi-byte
read. The master must supply the sub-address. in the write cycle, but
not in the read cycle.
SDA
DATA
STABLE
DATA CHANGE
ALLOWED
SCL
Figure 9. Bit Transfer on the I2C Bus
RW
SDA
SLAVD ID
SUB ADD
A
DATA
A
A
SCL
S
P
Figure 10. Data Transfer on the I2C Bus
Therefore, OV6630/OV6130 takes the read sub-address from the
previous write cycle. In multi-byte write or multi-byte read cycles, the
sub-address is automatically increment after the first data byte so that
continuous locations can be accessed in one bus cycle. A multi-byte
cycle overwrites its original sub-address; therefore, if a read cycle
immediately follows a multi-byte cycle, you must insert a single byte
write cycle that provides a new sub-address.
OV6630/OV6130 can be power up pin programmed to one-of-eight
slave ID addresses through function pins CS[2:0] (pins 35, 37, 34,
respectively).
Table 15. Slave ID Addresses
CS[2:0]
WRITE ID (hex)
READ ID (hex)
000
C0
C1
001
C4
C5
010
C8
C9
011
CC
CD
OV6630/OV6130 supports both single chip and multiple chip
configurations. By asserting MULT (pin 47) to high, the sensor can be
programmed for up to 8 slave ID addresses. Asserting MULT low
March 4, 2000
100
D0
D1
101
D4
D5
110
D8
D9
111
DC
DD
configures OV6630/OV6130 for single ID slave address with address
C0 for writes and address C1 for reads. MULT is internally defaulted
to a low condition.
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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
In the write cycle, the second byte in I2C bus is the sub-address for
selecting the individual on-chip registers, and the third byte is the data
associated with this register. Writing to unimplemented sub-address is
ignored. In the read cycle, the second byte is the data associated with
the previous stored sub-address. Reading of unimplemented subaddress returns unknown.
March 4, 2000
3.2
Register Set
The table below provides a list and description of available I2C
registers contained in the OV6630/OV6130 image sensor.
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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
Table 16 I2C Registers
Subaddress
(hex)
00
Register
Default
(hex)
Read/
Write
GAIN
00
RW
01
BLUE
80
RW
02
RED
80
RW
03
SAT
80
RW
04
05
Rsvd 04
CTR
××
48
–
RW
06
BRT
80
RW
07
SHP
C6
RW
08-0B
0C
Rsvd 08-0B
ABLU
××
20
–
RW
0D
ARED
20
RW
0E
COMR
0D
RW
0F
COMS
05
RW
March 4, 2000
Descriptions
AGC gain control
GC[7:6] – Unimplemented.
GC[5:0] – The current gain setting.
This register is updated automatically if AGC is enabled. The internal controller stores the
optimal gain value in this register. The current value is stored in this register if AGC is not
enabled.
Blue gain control
BLU[7] – “0” decrease gain, “1” increase gain.
BLU[6:0] – blue channel gain balance value.
Note: This function is not available on the OV6130 image sensor.
Red gain control
RED[7] – “0” decrease gain, “1” increase gain.
RED[6:0] – red channel balance value.
Note: This function is not available on the OV6130 image sensor.
Color saturation control
SAT[7:3] – Saturation adjustment. “F8h” is highest and “00h” is lowest.
SAT[2:0] – Unimplemented.
Note: This function is not available on the OV6130 image sensor.
Reserved
Contrast control
CTR[7] – selects gain at the dark area. “0” – gain=0.5 and “1” – gain=1.
CTR[6:4] – reserved.
CTR[3:0] – Contrast adjustment. “FFh” is highest and “00h” is lowest.
Brightness control
BRT[7:0] – Brightness adjustment. “FFh” is highest and “00h” is lowest.
Sharpness control
SHP[7:4] – Coring adjustment. Range: 0~80mV with step 5mV.
SHP[3:0] – Strength adjustment. Range: 0~8× with step 0.5×.
Reserved
White balance background: Blue channel
ABLU[7:6] – rsvd
ABLU[5] – “0” decrease background blue component, “1” increase background blue
component
ABLU[4:0] - White balance blue ratio adjustment
Note: This function is not available on the OV6130 image sensor.
White balance background: Red channel
ARED[7:6] – rsvd
ARED[5] – “0” decrease background red component, “1” increase background red
component
ARED[4:0] - White balance red ratio adjustment
Note: This function is not available on the OV6130 image sensor.
Common control R
COMR[7] – Analog signal 2x gain control bit. “1” - Additional 2x gain, “0” - normal.
COMR[6:0] – Reserved.
Common control S
COMS[7:6] – Reserved
COMS[5:4] – select the lowest signal used in automatic black level expanding (or
automatic brightness). “00” – lowest, “11” – highest and image is brighter.
COMS[3:2] – select highest luminance level to be available in AWB control. “00” –
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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
10
AEC
9A
RW
11
CLKRC
00
RW
12
COMA
24
RW
13
COMB
01
RW
14
COMC
00
RW
15
COMD
01
RW
16
FSD
03
RW
March 4, 2000
lowest, “11” – highest.
COMS[1:0] – select lowest luminance level to be available in AWB control. “00” –
lowest, “11” – highest.
Automatic exposure control
AEC[7:0] - Set exposure time
TEX = 2 × TLINE × AEC[7:0]
Clock rate control
CLKRC[7:6] – Sync output polarity selection
“00” – HSYNC=Neg, CHSYNC=Neg, VSYNC=Pos
“01” – HSYNC=Neg, CHSYNC=Neg, VSYNC=Neg
“10” – HSYNC=Pos, CHSYNC=Neg, VSYNC=Pos
“11” – HSYNC=Pos, CHSYNC=Pos, VSYNC=Pos
CLKRC[5:0] – Clock pre-scaler
CLK = (MAIN_CLOCK / ((CLKRC[5:0] + 1) × 2)) / n
Where n=1 if register [3E], COMO<7> is set to “1” and n=2 otherwise.
Common control A
COMA[7] – SRST, “1” initiates soft reset. All registers are set to default values and
chip is reset to known state and resumes normal operation. This bit is automatically
cleared after reset.
COMA[6] – MIRR, “1” selects mirror image
COMA[5] – AGCEN, “1” enables AGC,
COMA[4] – Digital output format, “1” selects 8-bit: Y U Y V Y U Y V
COMA[3] – Select video data output: “1” - select RGB, “0” - select YCrCb
COMA[2] – Auto white balance “1” - Enable AWB, “0” - Disable AWB
COMA[1] – Color bar test pattern: “1” - Enable color bar test pattern
COMA[0] – reserved
Note: COMA[3] is not programmable on the OV6130 image sensor.
Common control B
COMB[7:6] – reserved
COMB[5] - Select data format. “1” - select 8-bit format, Y/CrCb and RGB is
multiplexed to 8-bit Y bus, UV bus is tri-stated, “0” - select 16-bit format
COMB[4] – “1” - enable digital output in ITU-656 format
COMB[3] – CHSYNC output. “1” - horizontal sync, “0” - composite sync
COMB[2] – “1” – Tri-state Y and UV busses. “0” - enable both busses
COMB[1] – “1” - Initiate single frame transfer.
COMB[0] – “1” - Enable auto adjust mode.
Note: COMB[5] is not programmable on the OV6130 image sensor.
Common control C
COMC[7:6] – reserved
COMC[5] – QCIF digital output format selection. 1 - 176x144; 0 - 352x288.
COMC[4] – Field/Frame vertical sync output in VSYNC port selection: 1 - frame sync,
only ODD field vertical sync; 0 - field vertical sync, effect in Interlaced mode
COMC[3] – HREF polarity selection: 0 - HREF positive effective, 1 - HREF negative.
COMC[2] – gamma selection: 1 - RGB Gamma on ; 0 - RGB gamma is 1.
COMC[1:0] – reserved
Common Control D
COMD[7:2] – reserved bit.
COMD[1] – PCLK polarity selection. “0” - OV6630/OV6130 output data at PCLK
falling edge and data bus will be stable at PCLK rising edge; “1” - rising edge output
data and stable at PCLK falling edge. This bit is disable and should use PCLK rising
edge latch data bus in ITU-656 format (COMB[4]=1).
COMD[0] – U V digital output sequence exchange control. 1 - UV UV ··· for 16-bit,
U Y V Y ··· for 8-bit; 0 - V U V U ··· for 16-bit and V Y U Y ··· for 8-bit.
Note: COMD[0] is not programmable on the OV6130 image sensor.
Field slot division
FSD[7:2] – Field interval selection. It has functional in EVEN and ODD mode defined
Version 1.0
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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
17
HREFST
38
RW
18
HREFEND
EA
RW
19
VSTRT
03
RW
1A
VEND
92
RW
1B
PSHFT
00
RW
1C
MIDH
7F
R
1D
MIDL
A2
R
1E-1F
20
Rsvd 1E-1F
COME
××
00
RW
RW
March 4, 2000
by FSD[1:0]. It is disabled in OFF and FRAME mode. The purpose of FSD[7:2] is to
divide the video signal into programmed number of time slots, and allows HREF to
be active only one field in every FSD[7:2] fields. It does not affect the video data or
pixel rate. FSD[7:2] disables digital data output, there is only black reference level at
the output. FSD[7:2]=1 outputs every field. FSD[7:2]=2 outputs one field and
disables one field, etc.
FSD[1:0] – field mode selection. Each frame consists of two fields: Odd and Even,
FSD[1:0] define the assertion of HREF in relation to the two fields.
“00” – OFF mode; HREF is not asserted in both fields, one exception is the single
frame transfer operation (see the description for the register 13)
“01” – ODD mode; HREF is asserted in odd field only.
“10” – EVEN mode; HREF is asserted in even field only.
“11” – FRAME mode; HREF is asserted in both odd field and even field. FSD[7:2]
disabled.
Horizontal HREF start
HS[7:0] – selects the starting point of HREF window, each LSB represents two pixels
for CIF resolution mode, one pixels for QCIF resolution mode, this value is set based
on an internal column counter, the default value corresponds to 352 horizontal
window. Maximum window size is 356. See window description below. HS[7:0]
programmable range is [38] - [EB], and should less than HE[7:0]. HS[7:0] should be
programmable to value larger than or equal to [38]. Value larger than [EC] is invalid.
See window description below.
Horizontal HREF end
HE[7:0] – selects the ending point of HREF window, each LSB represents two pixels
for full resolution and one pixels for QCIF resolution, this value is set based on an
internal column counter, the default value corresponds to the last available pixel. The
HE[7:0] programmable range is [39] - [EC]. HE[7:0] should be larger than HS[7:0]
and less than or equal to [EC]. Value larger than [EC] is invalid. See window
description below.
Vertical line start
VS[7:0] – selects the starting row of vertical window, in full resolution mode, each LSB
represents 1 scan line in one frame. See window description below. Min. is [03],
max. is [93] and should less than VE[7:0].
Vertical line end
VE[7:0] – selects the ending row of vertical window, in full resolution mode, each LSB
represents 1 scan line in one frame, see window description below. Min. is [04], max.
is [94] and should larger than VS[7:0].
Pixel shift
PS[7:0] – to provide a way to fine tune the output timing of the pixel data relative to
that of HREF, it physically shifts the video data output time late in unit of pixel clock
as shown in the figure below. This function is different from changing the size of the
window as defined by HS[7:0] and HE[7:0] in registers 17 and 18. Higher than
default number delay the pixel output relative to HREF. The highest number is “FF”
and the maximum shift number is delay 256 pixels.
Manufacture ID byte: High
MIDH[7:0] – read only, always returns “7F” as manufacturer’s ID no.
Manufacture ID byte: Low
MIDL[7:0] – read only, always returns “A2” as manufacturer’s ID no.
Reserved
Common control E
COME[7] – HREF pixel number selection. “1” - HREF include 704 PCLK, every data
output twice.
COME[6] – reserved.
COME[5] – “1” First stage aperture correction enable. Correction strength will be
decided by register [07]. “0” disable first stage aperture correction.
COME[4] – “1” Second stage aperture correction enable. Correction strength and
threshold value will be decided by COMF[7] ~ COMF[4].
COME[3] – AWB smart mode enable. 1 – do not count pixels that their luminance level
are not in the range defined in register [0F]. 0 - count all pixels to get AWB result.
Valid only when COMB[0]=1 and COMA[2]=1
Version 1.0
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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
COME[2] – reserved.
COME[1] – AWB fast/slow mode selection. “1” - AWB is always fast mode, that is
register [01] and [02] is changed every field. “0” AWB is slow mode, [01] and [02]
change every 16/ 64 field decided by COMK[1]. When AWB enable, COMA[2]=1,
AWB is working as fast mode until it reaches stable, than as slow mode.
COME[0] – Digital output driver capability increase selection: “1” Double digital
output driver current; “0” low output driver current status.
21
YOFF
80
RW
22
UOFF
80
RW
23
CLKC
04
RW
24
AEW
33
RW
25
26
March 4, 2000
AEB
COMF
97
B0
RW
RW
Note: COME[3] (AWB smart mode), COME[2] (AWB stop), and COME[1] (AWB
fast/slow) are not programmable on the OV6130 image sensor.
Y channel offset adjustment
YOFF[7] – Offset adjustment direction 0 - Add Y[6:0]; 1 -Subtract Y[6:0].
YOFF[6:0] –Y channel digital output offset adjustment. Range: +127 ~ -127. If
COMG[2]=0, this register will be updated by internal circuit. Write a value to this
register through I2C has no effect. COMG[2]=1, Y channel offset adjustment will use
the stored value which can be changed through I2C. This register has no effect to A/D
output data if COMF[1]=0. If output RGB raw data, this register will adjust R/G/B
data.
U Channel offset adjustment
UOFF[7] – Offset adjustment direction: 0 - Add U[6:0]; 1 - Subtract U[6:0].
UOFF[6:0] – U channel digital output offset adjustment. Range: +128 ~ -128. If
COMG[2]=0, this register will be updated by internal circuit. Write a value to this
register through I2C has no effect. COMG[2]=1, U channel offset adjustment will use
the stored value which can be changed through I2C. This register has no effect to A/D
output data if COMF[1]=1. If output RGB raw data, this register will adjust R/G/B
data.
Note: This function is not available on the OV6130 image sensor.
Oscillator circuit control
CLKC[7:6] – Select different crystal circuit power level (“11” = minimum).
CLKC[5:0] – reserved
Automatic exposure control: Bright pixel ratio adjustment
AEW[7:0] – Used as calculate bright pixel ratio. OV6630/OV6130 AEC algorithm is
count whole field bright pixel (its luminance level is higher than a fixed level) and
black pixel (its luminance level is lower than a fixed level) number. When
bright/black pixel ratio is same as the ratio defined by register [25] and [26], image
stable. This register is used to define bright pixel ratio, default is 25%, each LSB
represent step: 0.5% Change range is: [01] ~ [CA]; Increase AEW[7:0] will increase
bright pixel ratio. For same light condition, the image brightness will increase if
AEW[7:0] increase.
Note: AEW[7:0] must combine with register [26] AEB[7:0]. The relation must be as
follows: AEW[7:0] + AEB[7:0] > [CA].
Automatic Exposure Control: Black pixel ratio adjustment
AEB[7:0] – used as calculate black pixel ratio. OV6630 AEC algorithm is count whole
field/ frame bright pixel (its luminance level is higher than a fixed level) and black
pixel (its luminance level is lower than a fixed level) number. When bright/black
pixel ratio is same as the ratio defined by register [25] and [26], image stable. This
register is used to define black pixel ratio, default is 80%, each LSB represent step:
0.5%; Change range is: [01] ~ [CA]; Increase AEB[7:0] will increase black pixel
ratio. For same light condition, the image brightness will decrease if AEB[7:0]
increase.
Note: AEB[7:0] must e combined with register [25] AEW[7:0]. The relation must be as follows: AEW[7:0] + AEB[7:0] > [CA].
Common control F
COMF[7:4] – reserved.
COMF[3] – UV offset difference. “1” use separate offsets for U and V; “0” use one
offset for both U and V.
COMF[2] – Digital data MSB/LSB swap. “1” LSB→bit7, MSB→bit0; “0” normal.
Version 1.0
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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
27
COMG
A0
RW
28
COMH
01
RW
29
COMI
00
RW
2A
FRARH
84
RW
2B
FRARL
5E
RW
March 4, 2000
COMF[1] – “1” digital offset adjustment enable. “0” disable.
COMF[0] – “1” Output first 4 line black level before valid data output. HREF number
will increase 4 relatively. “0” no black level output.
Common control G
COMG[7:6] – reserved
COMG[5] - Select CKOUT pin output V flag. “1” - CKOUT output V flag signal.
CKOUT=1 if UV channel output V or Red. CKOUT=0 if UV channel output U or
BLUE. “0” - CKOUT output buffered XCLK2
COMG[4:3] – reserved.
COMG[2] – “1” digital offset adjustment manually mode enable. Digital data will be
add/subtract a value defined by register [21] and [22], the contents are programmed
through I2C. “0” - digital data will be added/subtract a value defined by register [21]
and [22], which are updated by internal circuit.
COMG[1] – Digital output full range selection. OV6630/OV6130 default output data
range is [10] - [F0]. The output range changes to [01] - [FE] with signal overshoot
and undershoot level if COMG[1]=1.
COMG[0] – reserved.
Common control H
COMH[7] – “1” selects one-line RGB raw data output format, “0” selects normal twoline RGB raw data output.
COMH[6] – “1” enable black/white mode. The vertical resolution will be higher than
color mode when the imager works as BW mode. OV6630/OV6130 can’t work at 8bit output in this mode. OV6630/OV6130 outputs data from Y port. UV port will be
tri-state. COMB[5] and COMB[4] will be set to “0”. “0” normal color mode.
COMH[5] – reserved.
COMH[4] – Freeze AEC/AGC value, effective only at COMB[0]=1. “1” - register [00]
and [10] will not be updated and hold latest value. “0” - AEC/AGC normal working
status.
COMH[3] – AGC disable. “1” - when COMB[0]=1 and COMA[5]=1, internal circuit
will not update register [00], register [00] will kept latest updated value before
COMH[3]=1. “0” - when COMB0=1 and COMA[5]=1, register [00] will be updated
by internal algorithm.
COMH[2] – RGB raw data output YG format: “1” - Y channel G, UV channel B R; “0”
- Y channel: G R G R ···, UV channel B G B G ···
COMH[1] – Gain control bit. “1” channel gain increases 6dB. “0” no change to the
channel gain.
COMH[0] – reserved.
Note: COMH[2] (RGB Raw Data) is not programmable on the OV6130 image sensor.
Common control I
COMI[7] – AEC disable. “1” If COMB[0]=1, AEC stop and register [10] value will be
held at last AEC value and not be updated by internal circuit. “0” - if COMB[0]=1,
register [10] value will be updated by internal circuit
COMI[6] – Slave mode selection. “1” slave mode, use external SYNC and VSYNC;
“0” master mode.
COMI[5:4] – reserved
COMI[3] – Central 1/4 image area rather whole image used to calculate AEC/AGC. “0”
use whole image area to calculate AEC/AGC.
COMI[2] – reserved
COMI[1:0] – Version flag. For version A, value is [00], these two bits are read only.
Frame rate adjust high
FRARH[7] – Frame Rate adjustment enable bit. “1” Enable.
FRARH[6] – reserved
FRARH[5] – Highest 1bit of frame rate adjust control byte. See explanation below.
FRARH[4] – reserved
FRARH[3] – Y channel brightness adjustment enable. When COMF[2]=1 active.
FRARH[2] – reserved
FRARH[1] – “1” When in Frame exposure mode, only One frame data output.
FRARH[0] – reserved
Frame rate adjust low
FRARL[7:0] – Lowest 8 bit of frame rate adjust control byte. Frame rate adjustment
Version 1.0
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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
2C
2D
Rsvd 2C
COMJ
88
03
RW
RW
2E
VCOFF
80
RW
2F – 32
33
Rsvd 2F–32
CPP
××
00
–
RW
34
BIAS
A2
RW
35-37
38
Rsvd 35-37
COMK
80
81
RW
RW
39
COML
00
RW
March 4, 2000
resolution is 0.21%. Control byte is 10 bit. Every LSB equal decrease frame rate
0.21%. Range is 0.21% - 109%. IF frame rate adjustment enable, COME[7] must set
to “0”.
Reserved
Common control J
COMJ[7:5] – reserved
COMJ[4] – Enable auto black expanding mode.
COMJ[3] – “1” update white balance update only if AGC/AEC is stable. “0” update
white balance independent with AEC/AGC.
COMJ[2] – Band filter enable. After adjust frame rate to match indoor light frequency,
this bit enable a different exposure algorithm to cut light band induced by fluorescent
light.
COMJ[1] – reserved
COMJ[0] –U and V offset separate mode. “1” U and V use separate offsets. “0” U and
V use same offset defined by register [2E].
V channel offset adjustment
VCOFF[7] – Offset adjustment direction: “0” = Add V[6:0]; “1” = Subtract V[6:0].
VCOFF[6:0] – V channel digital output offset adjustment. Range: +128 ~ -128. If
COMG[2]=0, this register will be updated by internal circuit. Write to this register
through I2C has no effect. If COMG[2] =1, V channel offset adjustment will use the
stored value which can be changed through I2C. If COMF[1] =1, this register has no
effect to digital output data. If output RGB raw data, this register will adjust R/G/B
data.
Note: This function is not available on the OV6130 image sensor.
Reserved
Color processing parameter control
CPP[7:6] – reserved
CPP[5] – Luminance gamma on/off. “1” - luminance gamma on; “0” - luminance
gamma is 1.
CPP[4:0] – reserved
Bias adjustment
BIAS[7:6] – A/D reference level adjustment. “00” - 110% internal full signal range;
“01” - 120%, “10” - 130%, “11” - 140%.
BIAS[5:0] – reserved
Reserved
Common control K
COMK[7] – HREF edge latched by PCLK falling edge. “0” HREF edge is 10 ns after
PCLK rising edge.
COMK[6] – Output port drive current additional 2x control bit.
COMK[5] – reserved.
COMK[4] – ZV port Vertical timing selection. “1” VSYNC output ZV port vertical
sync signal. “0” = normal TV vertical sync signal.
COMK[3] – Quick stable mode when camera mode change. After relative control bit
set, the first VS will be the stable image with suitable AEC/AWB setting. “0” - slow
mode, after mode change need more field/frame to get stable AEC/AWB setting
image.
COMK[2] – reserved
COMK[1] – AWB stable time selection when in slow mode. “1” - 4 times less time
needed to get stable AWB setting when in slow AWB mode.
COMK[0] – reserved.
Note: COMK[1] (AWB stable Time) is not programmable on the OV6130 image sensor.
Common control L
COML[7] – reserved
COML[6] – PCLK output timing selection. “1” - PCLK valid only when HREF is high;
“0” - PCLK is free running.
COML[5] – reserved.
COML[4] – “1” select CHSYNC output from HREF port. “0” normal
COML[3] – “1” select HREF output from CHSYNC port. “0” normal
Version 1.0
27
SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
3A
HSST
0F
RW
3B
HSEND
3C
RW
3C
COMM
21
RW
3D
COMN
08
RW
3E
COMO
80
RW
3F
COMP
02
RW
40-4C
4D
Rsvd 40-4C
YMXA
××
02
–
RW
4E
ARL
A0
RW
March 4, 2000
COML[2] – Tristate all control signal output (FODD, CHSYNC, HREF, PCLK)
COML[1] – Highest 1 bit of horizontal sync starting position, combined with register
[3A]
COML[0] – Highest 1 bit of horizontal sync ending position, combined with register
[3B]
Horizontal sync start position
HSST[7:0] – lower 8 bit of horizontal sync starting position, combined with register bit
of COML[1], total 9 bit control. range: [00] -- [FF]. HSEND[8:0] must be less than
HSST[8:0]
Horizontal sync end position
HEND[7:0] – lower 8 bit of horizontal sync ending position, combined with register bit
of COML[0], total 9 bit control. range: [00] - [FF]. HSEND[8:0] must be larger than
HSST[8:0]
Common control M
COMM[7:5] – reserved.
COMM[4] – AEC/AGC change mode selection
COMM[3] – AEC/AGC change mode selection
COMM[2] – AEC/AGC change fastest mode
COMM[1] – AEC/AGC change fast mode
COMM[0] – AEC/AGC change slowest mode
Common Control N
COMN[7] – Enable one frame drop when AEC change to keep data valid when
Banding filter mode enable.
COMN[6:4] – reserved
COMN[3] – Enable 50 Hz PAL video timing, VTO analog signal can be displayed on
TV
COMN[2] – reserved
COMN[1] – Tri-state Y and UV digital video ports in power down mode.
COMN[0] – reserved
Common control O
COMO[7] – Input main clock divided by 2 or 4 selection. “1” -- 2; “0” -- 4
COMO[6:5] – reserved
COMO[4] – Select 4-bit nibble mode output
COMO[3] – reserved
COMO[2] – Enable Minimum exposure time is 4 line. Default is 1 line
COMO[1:0] – reserved
Common control P
COMP[7] – reserved
COMP[6] – Output main clock output from FODD port
COMP[5] – reserved
COMP[4] – Soft chip power down enable, can be waked up by disable this bit
COMP[3:2] – reserved
COMP[1] – ITU-656 output control
COMP[0] – Reset internal timing circuit without reset AEC/AGC/AWB value
Reserved
YUV matrix control (Main)
YMXA[7:5] – reserved
YMXA[4:3] – YUV/YCrCB selection:
“00” U = u, V = v
“01” U = 0.938u, V = 0.838v
“10” U = 0.563u, V = 0.714v
“11” U = 0.5u, V = 0.877v
YMXA[2:0] – Reserved
Note: This function is not available on the OV6130 image sensor.
AEC/AGC reference level
ARL[7:5] – Voltage reference selection (Higher voltage = brighter final stable image)
“000” = Lowest reference level
“111” = Highest reference level
ARL[4:0] – Reserved
Version 1.0
28
SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
4F
YMXB
00
RW
50-53
54
Rsvd 50-53
COMQ
××
09
–
RW
55-56
57
Rsvd 55-56
DBL
××
81
RW
RW
58
59
Rsvd 58
OFC
F5
00
RW
RW
5A
SC
28
RW
5B
SAWB
00
RW
5C
Rsvd 5C
13
RW
March 4, 2000
YUV matrix control (Secondary)
YMXB[7:6] – Y channel delay selection: 0 ~ 3tp
YMXB[5] – reserved.
YMXB[4] – UV 2tp delay selection
YMXB[3] – reserved.
YMXB[2] – Enable UV average mode.
YMXB[1:0] – Color killer control. “00” no color kill, “11” strongest.
Note: This function is not available on the OV6130 image sensor.
Reserved
Common control Q
COMQ[7] – reserved.
COMQ[6] – Central 1/4 image area rather whole image used to calculate AWB. “0”
uses whole image area to calculate AWB.
COMQ[5] – reserved.
COMQ[4] - Select smart AWB. AWB algorithm will not count pixels with strong color.
COMQ[3] – Enable AWB using manual input AWB registers when AWB is switched
from manual to automatic control.
COMQ[2] – reserved.
COMQ[1:0] – Select the maximum AGC.
“00” maximum gain=6dB, step 1/16
“01” maximum gain=12dB, step 1/16
“10” maximum gain=6dB, step 1/16
“11” maximum gain=18dB, step 1/8
Reserved
Internal charge pump control
DBL[7] – “0” disables internal charge pump. “1” enables internal charge pump.
DBL[6:4] – selects the driving capability of internal charge pump. “000” is the smallest
and “111” is the strongest.
DBL[3] – “1” no VSYNC in the field that is dropped.
DBL[2:0] – reserved.
Reserved
Dark current compensation
OFC[7] – reserved
OFC[6] – sign bit of the offset. “0” positive offset and “1” negative offset.
OFC[5:0] – add an offset before AGC to compensate the dark current.
Smart color control
SC[7] – reserved
SC[6] – select smart color. “1” indicates the color saturation will decrease with the
increase of AGC.
SC[5] – select the minimum color saturation in smart color option. “0” the minimum
saturation is 40% of normal value. “1” the minimum saturation is 50% of normal
value.
SC[4:0] – reserved.
Smart AWB control
SAWB[7:4] – reserved
SAWB[3:2] – Lowest chrominance level to be available for AWB control.
SAWB[1:0] – highest chrominance level to be available for AWB control.
Reserved.
Version 1.0
29