ETC OV9625

Omni
ision
Advanced Information
Preliminary Datasheet
TM
OV9625 Color CMOS SXGA (1.3 MPixel) CAMERACHIPTM
OV9121 B&W CMOS SXGA (1.3 MPixel) CAMERACHIPTM
Applications
Version 1.3, September 15, 2003
D3
D2
D1
D0
DGND
DVDD
ADGND
ADVDD
VrAD2
28
27
26
25
24
23
22
21
20
19
18 ASUB
D5
32
17 AGND
D6
33
16 AVDD
D7
34
15 VcCHG
D8
35
14 FSIN
D9
36
DOVDD
37
12 EXPSTB
DOGND
38
11 SCCB_E
HREF
39
10 RESET
CHSYNC
40
9
NC
VSYNC
41
8
FREX
NC
42
7
PWDN
13 VGA
43
44
45
46
47
48
1
2
3
4
5
6
VrHIGH
NBIT
DEVDD
DEGND
VrLOW
OV9625/OV9121
SVDD
CLCC-48
29
31
SGND
OV09121-C00A (B&W with
microlens, SXGA, VGA)
CLCC-48
30
PCLK
VcCHG
OV09625-C00A (Color, SXGA,
VGA)
Package
D4
Figure 1 OV9625/OV9121 Pin Diagram
Ordering Information
Product
1280 x 1024
640 x 480
2.5VDC + 10%
3.3VDC + 10%
3.3VDC + 10%
< 50 mA
< 10 µA
Raw RGB Data
1/2"
15 fps
30 fps
1.0 V/Lux-sec
54 dB
60 dB (due to ADC limitations)
Progressive
N/A
Up to 1050:1
Up to 500:1
5.2 µm x 5.2 µm
28 mV/s
< 0.03% of VPEAK-TO-PEAK
6.66 mm x 5.32 mm
.560 in. x .560 in.
SIO_C
•
•
•
Optical Black Level Calibration (BLC)
Improved micro lens design to decrease shading
Video or snapshot operations
Programmable/Auto Exposure and Gain Control
Programmable/Auto White Balance Control
Horizontal and vertical sub-sampling (4:2 and 4:2)
Programmable image windowing
Variable frame rate control
On-chip R/G/B channel and luminance average
counter
Internal/External frame synchronization
SCCB slave interface
Power-on reset and power-down mode
SXGA
VGA
Core
Power Supply
Analog
I/O
Power
Active
Requirements
Standby
Output Formats (10-bit)
Lens Size
Max. Image
SXGA
Transfer Rate
VGA
Sensitivity
S/N Ratio
Dynamic Range
Scan Mode
Gamma Correction
SXGA
Electronics
Exposure
VGA
Pixel Size
Dark Current
Fixed Pattern Noise
Image Area
Package Dimensions
Array Size
XCLK1
•
•
•
•
•
•
•
•
•
Key Specifications
SIO_D
Features
Digital still cameras
PC camera/dual mode
Video conference applications
Machine vision
Security cameras
Biometrics
XCLK2
Both devices incorporate a 1280 x 1024 (SXGA) image
array and an on-chip 10-bit A/D converter capable of
operating at up to 15 frames per second (fps) at full
resolution and an improved micro lens design to decrease
shading. Proprietary sensor technology utilizes advanced
algorithms to cancel Fixed Pattern Noise (FPN), eliminate
smearing, and drastically reduce blooming. The control
registers allow for flexible control of timing, polarity, and
CameraChip operation, which, in turn, allows the engineer
a great deal of freedom in product design.
•
•
•
•
•
•
NC
The OV9625 (color) and OV9121 (black and white) are
high-performance 1.3 mega-pixel CAMERACHIPSTM for
digital still image and video camera products.
NC
General Description
Proprietary to OmniVision Technologies
1
CMOS SXGA (1.3 MPixel) CAMERACHIP™
OV9625/OV9121
Omni
ision
Functional Description
Figure 2 shows the functional block diagram of the OV9625/OV9121 image sensor. The OV9625/OV9121 includes:
•
Image Sensor Array (1280 x 1024 resolution)
•
Gain Control
•
Channel Balance
•
10-Bit Analog-to-Digital Converter
•
Black Level Compensation
•
SCCB Interface
•
Digital Video Port
•
Timing Generator
Figure 2 Functional Block Diagram
D[9:0]
PCLK
Row Select
Column Sense Amps
10-Bit
A/D
Channel
Balance
AMP
Black Level
Compensation
Digital
Video
Port
HREF
HSYNC
VSYNC
Image Array
(1312 x 1036)
Gain
Control
Balance
Control
Control
Register
Bank
PLL
XCLK
2
SCCB Slave
Interface
Timing Generator and Control Logic
RESET
PWDN
FSI
VGA
Proprietary to OmniVision Technologies
FREX
EXPSTB
SIO_C
SIO_D SCCB_E
Version 1.3, September 15, 2003
Omni
Functional Description
ision
Image Sensor Array
10-Bit Analog-to-Digital Converter
The OV9625/OV9121 sensor is a 1/2-inch format CMOS
imaging device. The sensor contains 1,359,232 pixels.
Figure 3 shows the active regions of sensor array.
The balanced signal then will be digitized by the on-chip
10-bit ADC. It can operate at up to 12 MHz, and is fully
synchronous to the pixel clock. The actual conversion rate
is determined by the frame rate.
G
Black Level Compensation
1311
B
1310
G
1309
B
1308
G
1307
B
1306
G
5
B
4
3
1
0
Column
R
o 0 B G
w 1 G R
2
Figure 3 Sensor Array Region
B
G
Dummy
G
R
G
R
G
R
G
R
G
R
Dummy
2
B
G
B
G
B
G
B
G
B
G
B
G
Dummy
3
G
R
G
R
G
R
G
R
G
R
G
R
Dummy
4
Optical
Black
5
B
G
B
G
B
G
B
G
B
G
B
G
Dummy
7 G
R
G
R
G
R
G
R
G
R
G
R
Dummy
8
B
G
B
G
B
G
B
G
B
G
B
G
Dummy
9 G
R
G
R
G
R
G
R
G
R
G
R
Dummy
10
B
G
B
G
B
G
B
G
B
G
B
G
11
G
R
G
R
G
R
G
R
G
R
G
R
6
1024
Active
Lines
1032
B
G
B
G
B
G
B
G
B
G
B
G
1033
G
R
G
R
G
R
G
R
G
R
G
R
1034
B
G
B
G
B
G
B
G
B
G
B
G
Dummy
1035
G
R
G
R
G
R
G
R
G
R
G
R
Dummy
The color filters are Bayer pattern. The primary color
BG/GR array is arranged in line-alternating fashion. Of the
1,359,232 pixels, 1,310,720 are active. The other pixels
are used for black level calibration and interpolation.
The sensor array design is based on a field integration
read-out system with line-by-line transfer and an
electronic shutter with a synchronous pixel read-out
scheme.
Gain Control
When the column sample/hold circuit has sampled one
row of pixels, the pixel data will shift out one-by-one into
an analog amplifier. The amplifier gain can either be
programmed by the user or controlled by the internal
automatic gain control circuit (AGC). The gain adjustment
range is 0-24 dB.
After the pixel data has been digitized, black level
calibration can be performed before the data is output.
The black level calibration block subtracts the average
signal level of optical black pixels to compensate for the
dark current in the pixel output. Black level calibration can
be disabled by the user.
Windowing
OV9625/OV9121 allows the user to define window size or
region of interest (ROI), as required by the application.
Window size setting (in pixels) ranges from 2 x 4 to
1280 x 1024 (SXGA) or 2 x 2 to 640 x 480 (VGA), and can
be anywhere inside the 1312 x 1036 boundary. Note that
modifying window size or window position does not alter
the frame or pixel rate. The windowing control merely
alters the assertion of the HREF signal to be consistent
with the programmed horizontal and vertical ROI. The
default window size is 1280 x 1024. See Figure 4 and
registers HREFST, HREFEND, VSTRT, VEND, and
COMM for details. The maximum output window size is
1292 columns by 1024 rows.
Note that after writing to register COMH (0x12) to change
the sensor mode, registers related to the sensor’s
cropping window will be reset back to its default value.
Figure 4 Windowing
Column
Start
Column
End
HREF
R Column
o
w
Channel Balance
Version 1.3, September 15, 2003
HREF
Row Start
The amplified signals are then balanced with a channel
balance block. In this block, Red/Blue channel gain is
increased or decreased to match Green channel
luminance level and gamma correction is performed. The
adjustment range is 54 dB. This function can be done
manually by the user or with the internal automatic white
balance controller (AWB).
Display
Window
Row End
Sensor Array
Boundary
Proprietary to OmniVision Technologies
3
CMOS SXGA (1.3 MPixel) CAMERACHIP™
OV9625/OV9121
Sub-sampling Mode
Figure 5 Pixel Array
Column #
i+1 i+2 i+3 i+4 i+5 i+6 i+7 i+8 i+9
n
B
G
B
G
B
G
B
G
B
G
n+1
G
R
G
R
G
R
G
R
G
R
n+2
B
G
B
G
B
G
B
G
B
G
n+3
G
R
G
R
G
R
G
R
G
R
n+4
B
G
B
G
B
G
B
G
B
G
n+5
G
R
G
R
G
R
G
R
G
R
n+6
B
G
B
G
B
G
B
G
B
G
n+7
G
R
G
R
G
R
G
R
G
R
Row #
ision
Slave Operation Mode
Default resolution for the OV9625/OV9121 is 1280 x 1024
pixels, with all active pixels being output (see Figure 5).
The OV9625/OV9121 can be programmed to output in
640 x 480 (VGA) sized images for applications where
higher resolution image capture is not required.
i
Omni
The OV9625/OV9121 can be programmed to operate in
slave mode (default is master mode).
When used as a slave device, the OV9625/OV9121
changes the HSYNC and VSYNC outputs to input pins for
use as horizontal and vertical synchronization input
triggers supplied by the master device. The master device
must provide the following signals:
1.
System clock MCLK to XCLK1 pin
2.
Horizontal sync MHSYNC to CHSYNC pin
3.
Vertical frame sync MVSYNC to VSYNC pin
See Figure 7 for slave mode connections and Figure 8 for
detailed timing considerations. In this mode, the clock for
all devices should be the same. Otherwise, the devices
will suffer from flickering at line frequency.
Figure 7 Slave Mode Connection
D[9:0]
For VGA resolution, the following sub-sampling method is
available:
Progressive Sub-sampling
The entire array is sub-sampled for maximal image
quality. Both horizontal and vertical pixels are
sub-sampled to an aspect ration of 4:2 as illustrated in
Figure 6.
CHSYNC
MHSYNC
VSYNC
MVSYNC
XCLK1
MCLK
OV9625
(OV9121)
Master
Device
Figure 8 Slave Mode Timing
Figure 6 Sub-Sampling Mode
T frame
VSYNC
n+1
G R
B G
G R
i+9
i+8
i+7
i+6
i+4
i+5
G
i+3
B
i+2
i
Row n
i+1
Column
T VS
B G
G R
T line
HSYNC
MCLK
T HS
Tclk
n+2
NOTE:
n+3
1) THS > 6 Tclk, Tvs > Tline
2) Tline = 1520 x Tclk (SXGA); Tline = 800 x Tclk (VGA)
3) Tframe = 1050 x Tline (SXGA); Tframe = 500 x Tline (VGA)
n+4
B
G
B G
B G
n+5
G R
G R
G R
n+6
n+7
Channel Average Calculator
Skipped Pixels
OV9625/OV9121 provides average output level data for
the R/G/B channels along with frame-averaged luminance
level. Access to the data is via the serial control port.
Average values are calculated from 128 pixels per line (64
in VGA).
4
Proprietary to OmniVision Technologies
Version 1.3, September 15, 2003
Omni
Functional Description
ision
Reset
The RESET pin (pin 10) is active high. There is an internal
pull-down (weak) resistor in the sensor so the default
status of the RESET pin is low.
Figure 9 RESET Timing Diagram
RESET
1ms
4096 External Clock
Two methods of power-down or standby operation are
available with the OV9625/OV9121.
•
Hardware power-down may be selected by pulling
the PWDN pin (pin 7) high (+3.3VDC). When this
occurs, the OV9625/OV9121 internal device clock is
halted and all internal counters are reset. The current
draw is less than 10 µA in this standby mode.
•
Software power-down can be effected by setting the
COMC[4] register bit high. Standby current will be
less then 1 mA when in software power-down. All
register content is maintained in standby mode.
There are two ways for a sensor reset:
1.
2.
Hardware reset - Pulling the RESET pin high and
keeping it high for at least 1 ms. As shown in
Figure 9, after a reset has been initiated, the sensor
will be most stable after the period shown as 4096
External Clock.
Software reset - Writing 0x80 to register 0x12 (see
“COMH” on page 20) for a software reset. If a
software reset is used, a reset operation done twice
is recommended to make sure the sensor is stable
and ready to access registers. When performing a
software reset twice, the second reset should be
initiated after the 4096 External Clock period as
shown in Figure 9.
Power-Down Mode
The PWDN pin (pin 7) is active high. There is an internal
pull-down (weak) resistor in the sensor so the default
status of the PWDN pin is low.
Figure 10 PWDN Timing Diagram
SCCB Interface
OV9625/OV9121 provides an on-chip SCCB serial control
port that allows access to all internal registers, for
complete control and monitoring of OV9625/OV9121
operation.
Refer to OmniVision Technologies Serial Camera Control
Bus (SCCB) Specification for detailed usage of the SCCB
interface.
Video Output
RGB Raw Data Output
The OV9625 CAMERACHIP offers 10-bit RGB raw data
output.
B&W Output
The OV9121 offers 10-bit luminance signal data output.
PWDN
Sensor Power Down
Version 1.3, September 15, 2003
Proprietary to OmniVision Technologies
5
OV9625/OV9121
CMOS SXGA (1.3 MPixel) CAMERACHIP™
Digital Video Port
The OV9625/OV9121 digital video port can be
programmed to work in either master or slave mode.
OV9625/OV9121 has a 10-bit digital video port. The MSB
and LSB can be swapped with the control registers.
Figure 11 shows some examples of connections with
external devices.
Figure 11 Connection Examples
D9
D8
D7
ision
Line/Pixel Timing
MSB/LSB Swap
MSB D9
Omni
LSB D9
D0
D8
D8
D1
D7
D7
D2
D6
D6
D6
D3
D5
D5
D5
D4
D4
D4
D4
D5
D3
D3
D3
D6
D2
D2
D2
D7
D1
D1
D1
D8
LSB D0
D0
MSB D0
D9
In both master and slave modes, pixel data output is
synchronous with PCLK (or MCLK if port is a slave),
HREF and VSYNC. The default PCLK edge for valid data
is the negative edge but may be programmed with register
COMK[4] (see “COMK” on page 22) for the positive edge.
Basic line/pixel output timing is illustrated in Figure 14 and
Figure 15.
To minimize image capture circuitry and conserve
memory space, PCLK output can be programmed with
register COMK[5] (see “COMK” on page 22) to be
qualified by the active video period as defined by the
HREF signal. See Figure 12 for details.
Figure 12 PCLK Output Only at Valid Pixels
PCLK
PCLK active edge negative
HREF
PCLK
PCLK active edge positive
OV9625
(OV9121)
External
Device
Default 10-bit Connection
OV9625
(OV9121)
Swap 10-bit Connection
MSB D9
D7
LSB D9
D8
D6
D8
D7
D5
D7
D0
D6
D4
D6
D1
D5
D3
D5
D2
D4
D2
D4
D3
D3
D1
D3
D4
D2
D0
D2
D5
D1
D1
D6
LSB D0
MSB D0
D7
OV9625
(OV9121)
External
Device
Default 8-bit Connection
OV9625
(OV9121)
VSYNC
External
Device
External
Device
Swap 8-bit Connection
Pixel Output Pattern
Table 1 shows the output data order from the
OV9625/OV9121. The data output sequence following the
first HREF and after VSYNC is: B0,0 G0,1 B0,2 G0,3…
B0,1278 G0,1279. After the second HREF, the output is G1,0
R1,1 G1,2 R1,3… G1,1278 R1,1279…, etc. If the
OV9625/OV9121 is programmed to output VGA
resolution data, horizontal and vertical sub-sampling will
occur. The default output sequence for the first line of
output will be: B0,0 G0,1 B0,4 G0,5… B0,1276 G0,1277. The
second line of output will be: G1,0 R1,1 G1,4 R1,5… G1,1276
R1,1277.
Table 1
Data Pattern
R/C
0
1
2
3
...
1278
1279
0
B0,0
G0,1
B0,2
G0,3
...
B0,1278
G0,1279
1
G1,0
R1,1
G1,2
R1,3
...
G1,1278
R1,1279
2
B2,0
G2
B2,2
G2,3
...
B2,1278
G2,1279
3
G3,0
R3,1
G3,2
R3,3
...
G3,1278
R3,1279
.
.
.
.
6
Proprietary to OmniVision Technologies
1022
B1022,0 G1022,1 B1022,2 G1022,3
B1022,1278 G1022,1279
1023
G1023,0 R1023,1 G1023,2 R1023,3
G1023,1278 R1023,1279
Version 1.3, September 15, 2003
Omni
Functional Description
ision
Timing Generator
In general, the timing generator controls the following
functions:
•
Frame Exposure Mode Timing
•
Frame Rate Timing
•
Frame Rate Adjust
Frame Exposure Mode Timing
OV9625/OV9121 supports frame exposure mode.
Typically the frame exposure mode must work with the aid
of an external shutter.
The frame exposure pin, FREX (pin 8) is the frame
exposure mode enable pin and EXPSTB (pin 12) serves
as the exposure start trigger for the sensor. There are two
ways to set Frame Exposure mode:
•
Control both FREX and EXPSTB pins - Frame
Exposure mode can be set by pulling both FREX and
EXPSTB pins high at the same time (see Figure 19).
•
Control FREX only and keep EXPSTB low - In this
case, the pre-charge time is tline and sensor
exposure time is the period after pre-charge until the
shutter closes (see Figure 18).
When the external master device asserts the FREX pin
high, the sensor array is quickly pre-charged and stays in
reset mode until the EXPSTB pin is pulled low by the
external master (sensor exposure time can be defined as
the period between EXPSTB low to shutter close). After
the FREX pin is pulled low, the video data stream is then
clocked to the output port in a line-by-line manner. After
completing one frame of data output, OV9625/OV9121
will output continuous live video data unless in single
frame transfer mode. Figure 18 and Figure 19 show the
detailed timing for this mode.
For frame exposure, register AEC (0x10) must be set to
0xFF and register GAIN (0x00) should be no larger than
0x10 (maximum 2x gain).
Version 1.3, September 15, 2003
Frame Rate Timing
Default frame timing is illustrated in Figure 16 and
Figure 17. Refer to Table 2 for the actual pixel rate at
different frame rates.
Table 2
Frame and Pixel Rates
Frame Rage (fps)
15
10
7.5
6
5
PCLK (MHz)
24
16
12
9.6
8
NOTE: Based on 24 MHz external clock and internal PLL
on, frame rate is adjusted by the main clock divide method.
Frame Rate Adjust
OV9625/OV9121 offers three methods of frame rate
adjustment.
1.
Clock prescaler (see “CLKRC” on page 20)
By changing the system clock divide ratio, the frame
rate and pixel rate will change together. This
method can be used for dividing the frame/pixel rate
by: 1/2, 1/3, 1/4 … 1/64 of the input clock rate.
2.
Line adjustment (see “COML” on page 24 and see
“FRARL” on page 25)
By adding dummy pixel timing in each line, the
frame rate can be changed while leaving the pixel
rate as is.
3.
Vertical sync adjustment
By adding dummy line periods to the vertical sync
period (see “ADDVSL” on page 25 and see
“ADDVSH” on page 25), the frame rate can be
altered while the pixel rate remains the same.
After changing registers COML (0x2A) and FRARL (0x2B)
to adjust the dummy pixels, it is necessary to write to
register COMH (0x12) or CLKRC (0x11) to reset the
counter. Generally, OmniVision suggests users write to
register COMH (0x12) (to change the sensor mode) as the
last one. However, if you want to adjust the cropping
window, it is necessary to write to those registers after
changing register COMH (0x12). To use COMH to reset
the counter, it is necessary to generate a pulse on
resolution control register bit COMH[6].
Proprietary to OmniVision Technologies
7
CMOS SXGA (1.3 MPixel) CAMERACHIP™
OV9625/OV9121
Omni
ision
Pin Description
Table 3
Pin Description
Pin Number
8
Name
Pin Type
Function/Description
01
SVDD
Power
3.3 V power supply for the pixel array
02
VrHIGH
Analog
Sensor high reference - bypass to ground using a 0.1 µF capacitor
03
NBIT
Analog
Sensor bit line reference - bypass to ground using a 0.1 µF capacitor
04
DEVDD
Power
3.3 V power supply for the sensor array decoder
05
DEGND
Power
Ground for the sensor array decoder
06
VrLOW
Analog
Sensor low reference - bypass to ground using a 0.1 µF capacitor
07
PWDN
Input (0)a
Power down mode enable, active high
08
FREX
Input (0)
Snapshot trigger, used to activate a snapshot sequence
09
NC
10
RESET
Input (0)
Chip reset, active high
11
SCCB_E
Input (0)
SCCB interface enable, active low
12
EXPSTB
Input (0)
Snapshot exposure start trigger
0:
Sensor starts exposure - only effective in snapshot mode
1:
Sensor stays in reset mode
13
VGA
Input (0)
Sensor Resolution Selection
0:
SXGA resolution (1280 x 1024)
1:
VGA resolution (640 x 480)
14
FSIN
Input (0)
Frame synchronization input
15
VcCHG
Analog
Sensor reference - bypass to ground using a 1 µF capacitor
16
AVDD
Power
3.3 V power supply for analog circuits
17
AGND
Power
Ground for analog circuits
18
ASUB
Power
Ground for analog circuit substrate
19
VrAD2
Analog
A/D converter reference - bypass to ground using a 0.1 µF capacitor
20
ADVDD
Power
3.3 V power supply for A/D converter
21
ADGND
Power
Ground for A/D converter
22
DVDD
Power
2.5 V power supply for digital circuits
23
DGND
Power
Ground for digital circuits
24
D0
Output
Digital video output bit[0]
25
D1
Output
Digital video output bit[1]
26
D2
Output
Digital video output bit[2]
27
D3
Output
Digital video output bit[3]
28
D4
Output
Digital video output bit[4]
—
No connection
Proprietary to OmniVision Technologies
Version 1.3, September 15, 2003
Omni
Pin Description
ision
Table 3
Pin Description (Continued)
Pin Number
a.
Name
Pin Type
Function/Description
29
XCLK1
Input
Crystal clock input
30
XCLK2
Output
Crystal clock output
31
PCLK
Output
Pixel clock output
32
D5
Output
Digital video output bit[5]
33
D6
Output
Digital video output bit[6]
34
D7
Output
Digital video output bit[7]
35
D8
Output
Digital video output bit[8]
36
D9
Output
Digital video output bit[9]
37
DOVDD
Power
3.3 V power supply for digital video port
38
DOGND
Power
Ground for digital video port
39
HREF
Output
Horizontal reference output
40
CHSYNC
Output
Horizontal synchronization output when chip is in master mode.
41
VSYNC
Output
Vertical synchronization output when chip is in master mode.
42
NC
—
No connection
43
NC
—
No connection
44
NC
—
No connection
45
SIO_D
I/O
SCCB serial interface data I/O
46
SIO_C
Input
47
VcCHG
Analog
Sensor reference - bypass to ground using a 1 µF capacitor
48
SGND
Power
Ground for pixel array.
SCCB serial interface clock input
Input (0) represents an internal pull-down low resistor.
Version 1.3, September 15, 2003
Proprietary to OmniVision Technologies
9
OV9625/OV9121
CMOS SXGA (1.3 MPixel) CAMERACHIP™
Omni
ision
Electrical Characteristics
Table 4
Absolute Maximum Ratings
Ambient Storage Temperature
-40ºC to +125ºC
Supply Voltages (with respect to Ground)
VDD-A
3.3V
VDD-C
2.5V
VDD-IO
3.3V
All Input/Output Voltages (with respect to Ground)
-0.3V to VDD-IO+1V
Lead Temperature, Surface-mount process
+230ºC
ESD Rating, Human Body model
2000V
NOTE:
Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may
result in permanent device damage.
Table 5
DC Characteristics (0°C < TA < 70°C)
Symbol
Parameter
Min
Typ
Max
Unit
VDD-A
Supply voltage (DEVDD, ADVDD, AVDD, SVDD)
3.0
3.3
3.6
V
VDD-IO
Supply voltage (DOVDD)
3.0
3.3
3.6
V
VDD-C
Supply voltage (DVDD)
2.25
2.5
2.75
V
IDD1
Active (Operating) Current
40
60
mA
IDD2
Standby Current
1
mA
IDD3
Standby Current
10
µA
Supply
Digital Inputs
VIL
Input voltage LOW
VIH
Input voltage HIGH
CIN
Input capacitor
0.8
2
V
V
10
pF
Digital Outputs (standard loading 25 pF, 1.2 K: to 3 V)
VOH
Output voltage HIGH
VOL
Output voltage LOW
2.4
V
0.6
V
SCCB Inputs
10
VIL
SIO_C and SIO_D
-0.5
0
1
V
VIH
SIO_C and SIO_D
2.5
3.3
VDD + 0.5
V
Proprietary to OmniVision Technologies
Version 1.3, September 15, 2003
Omni
Electrical Characteristics
ision
Table 6
AC Characteristics (TA = 25°C, VDD = 3V)
Symbol
Parameter
Min
Typ
Max
Unit
ADC Parameters
B
Analog bandwidth
12
MHz
DLE
DC differential linearity error
0.5
LSB
ILE
DC integral linearity error
1
LSB
Settling time for hardware reset
<1
ms
Settling time for software reset
<1
ms
Settling time for VGA/XSGA mode change
<1
ms
<300
ms
Settling time for register setting
Table 7
Timing Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
8
24
48
MHz
2
ns
55
%
Oscillator and Clock Input
fOSC
Frequency (XCLK1, XCLK2)
tr, tf
Clock input rise/fall time
Clock input duty cycle
Version 1.3, September 15, 2003
45
50
Proprietary to OmniVision Technologies
11
OV9625/OV9121
CMOS SXGA (1.3 MPixel) CAMERACHIP™
Omni
ision
Timing Specifications
Figure 13 SCCB Timing Diagram
tF
t HIGH
tR
t HD:DAT
t SU:DAT
tLOW
SIO_C
t SU:STA
t HD:STA
t SU:STO
SIO_D
IN
t BUF
tAA
t DH
SIO_D
OUT
SCCB_E
Table 8
SCCB Timing Specifications
Symbol
12
Parameter
Min
Typ
Max
Unit
400
KHz
fSIO_C
Clock Frequency
tLOW
Clock Low Period
1.3
Ps
tHIGH
Clock High Period
600
ns
tAA
SIO_C low to Data Out valid
100
tBUF
Bus free time before new START
1.3
Ps
tHD:STA
START condition Hold time
600
ns
tSU:STA
START condition Setup time
600
ns
tHD:DAT
Data-in Hold time
0
Ps
tSU:DAT
Data-in Setup time
100
ns
tSU:STO
STOP condition Setup time
600
ns
tR, tF
SCCB Rise/Fall times
tDH
Data-out Hold time
Proprietary to OmniVision Technologies
900
300
50
ns
ns
ns
Version 1.3, September 15, 2003
Omni
Timing Specifications
ision
Figure 14 SXGA Line/Pixel Output Timing
tp
t pr
t pf
PCLK or
MCLK
t dphf
t dphr
HREF
t hd
t su
D[9:0]
P1279
Invalid
Data
P0
P1
P2
P 1278
P1279
t dpd
Figure 15 VGA Line/Pixel Output Timing
tp
t pr
t pf
PCLK or
MCLK
t dphf
t dphr
HREF
t hd
t su
D[9:0]
P639
Invalid
Data
P0
P1
P2
P638
P639
t dpd
Version 1.3, September 15, 2003
Proprietary to OmniVision Technologies
13
OV9625/OV9121
CMOS SXGA (1.3 MPixel) CAMERACHIP™
Omni
ision
Figure 16 SXGA Frame Timing
1050 x tline
VSYNC
4 x tline
tline = 1520tp
12396tp
21284tp
240tp
HREF
1280tp
Invalid Data
D[9:0]
P0 - P1279
Row 0
Row 1
Row 2
Row 1023
Figure 17 VGA Frame Timing
500 x tline
VSYNC
4 x tline
tline = 800tp
6558tp
6402tp
160tp
HREF
640tp
D[9:0]
Invalid Data
P0 - P639
Row 0
Row 1
Row 2
Row 479
The specifications shown in Table 9 apply for DVDD = +2.5V, DOVDD = +3.3V, TA = 25°C, sensor working at 15 fps,
external loading = 30 pF.
Table 9
Pixel Timing Specification
Symbol
14
Parameter
Min
Typ
Max
Unit
20.83
ns
tp
PCLK period
tpr
PCLK rising time
10
ns
tpf
PCLK falling time
5
ns
tdphr
PCLK negative edge to HREF rising edge
0
5
ns
tdphf
PCLK negative edge to HREF negative edge
0
5
ns
tdpd
PCLK negative edge to data output delay
0
5
ns
tsu
Data bus setup time
15
ns
thd
Data bus hold time
8
ns
Proprietary to OmniVision Technologies
Version 1.3, September 15, 2003
Omni
Timing Specifications
ision
Figure 18 Frame Exposure Timing with EXPSTB Staying Low
Shutter Open
Shutter
FREX
t line
Exposure Time
Sensor
Precharge
Sensor Timing
t dfvr
t dfvf
t dvsc
VSYNC
t dvh
tdhv
HREF
D[9:0]
Row X
Row 0
Row 1
No following live video
frame if set to transfer
single frame
Row 1199
Figure 19 Frame Exposure Timing with EXPSTB Asserted
Shutter Open
Shutter
FREX
t des
tdef
EXPSTB
t pre
Exposure Time
Sensor
Precharge
Sensor Timing
t dfvr
t dfvf
t dvsc
VSYNC
t dvh
tdhv
HREF
D[9:0]
Row X
Table 10
Row 0
Row 1
No following live video
frame if set to transfer
single frame
Row 1199
Frame Exposure Timing Specifications
Symbol
Min
Typ
Max
1520 (SXGA)
tline
tvs
tdfvr
Unit
tp
800 (VGA)
tp
4
tline
8
9
tp
tdfvf
4
tline
tdvsc
2
tline
tdhv
tdvh
tdes
NOTE
21044 (SXGA)
tp
6402 (VGA)
tp
12396 (SXGA)
tp
6558 (VGA)
tp
1500 (SXGA)
tp
780 (VGA)
tp
1) FREX must stay high long enough to ensure the entire sensor has been reset.
2) Shutter must be closed no later then 3040tp (1600tp for VGA) after VSYNC falling edge.
Version 1.3, September 15, 2003
Proprietary to OmniVision Technologies
15
CMOS SXGA (1.3 MPixel) CAMERACHIP™
OV9625/OV9121
Omni
ision
OV9625/OV9121 Light Response
Figure 20 OV9625/OV9121 Light Response
OV-9620spectrum
response
Normalized Spectrum
Response
200
200
180
180
160
160
140
140
Efficiency
Sensitivity
120
120
100
100
80
80
60
60
40
40
1180
1180nm
1100
1100nm
1060nm
1060
1020
1020nm
980
980nm
940
940nm
900
900nm
860nm
860
820
820nm
780
780nm
740
740nm
700
700nm
660nm
660
620
620nm
580nm
580
540
540nm
500
500nm
460nm
460
420
420nm
380nm
380
00
300nm
300
20
20
Wavelength
(nm)
Wavelength
R
G
B
1150
1.00
1.00
0.90
0.90
0.80
0.80
0.70
0.70
0.60
0.60
0.50
0.50
0.40
0.40
0.30
0.30
0.20
0.20
0.10
0.10
0.00
0.00
40
0400
45
0
450
50
0
500
55
0
550
60
0
65 600
0
70 650
0
75 700
0
80 750
0
85 800
0
90 850
0
95 900
0
10 950
00
10 1000
50
11
01050
0
11
51100
0
Efficiency
Efficiency
Monochrome
Response
Monochrome
Response
Wavelength
Wavelength
16
Proprietary to OmniVision Technologies
Version 1.3, September 15, 2003
Omni
Register Set
ision
Register Set
Table 11 provides a list and description of the Device Control registers contained in the OV9625/OV9121. The device slave
addresses are 60 for write and 61 for read.
Table 11
Address
(Hex)
Device Control Register List
Register
Name
Default
(Hex)
R/W
Description
AGC – Gain Control
00
GAIN
00
RW
Bit[7:6]: Reserved
Bit[5:0]: Gain control gain setting
•
Range: 1x to 8x
Set COMI[0] = 0 (see “COMI” on page 21) to disable AGC
01
BLUE
80
RW
Blue gain control MSB, 8 bits (LSB 2 bits in COMA[3:2], see “COMA” on
page 17)
Note: This function is not available on the B&W OV9121.
02
RED
80
RW
Red gain control MSB, 8 bits (LSB 2 bits in COMA[1:0], see “COMA” on
page 17)
Note: This function is not available on the B&W OV9121.
Common Control A
03
COMA
40
RW
Bit[7:4]:
Bit[3:2]:
Bit[1:0]:
AWB update threshold
BLUE channel lower 2 bits gain control
RED channel lower 2 bits gain control
Note: This function is not available on the B&W OV9121.
Common Control B
Bit[7,4]:
04
COMB
00
RW
Bit[6:5]:
Bit[3]:
Bit[2:0]:
AWB – Update speed select
00: Slow
01: Slowest
10: Fast
11: Fast
AWB – Step select
00: 1023 steps
01: 255 steps
10: 511 steps
11: 255 steps
Reserved
AEC lower 3 bits, AEC[2:0] (see “AEC” on page 19 for
most significant 8 bits, AEC[10:3])
05
BAVG
00
RW
B Channel Average
06
GbAVG
00
RW
G Channel Average - picked G pixels in the same line with B pixels.
07
GrAVG
00
RW
G Channel Average - picked G pixels in the same line with R pixels.
08
RAVG
00
RW
R Channel Average
Version 1.3, September 15, 2003
Proprietary to OmniVision Technologies
17
OV9625/OV9121
Table 11
Address
(Hex)
CMOS SXGA (1.3 MPixel) CAMERACHIP™
Omni
ision
Device Control Register List
Register
Name
Default
(Hex)
R/W
Description
Common Control C
Bit[7:5]: Reserved
Bit[4]:
Sleep or power-down mode enable
0: Normal
1: Sleep mode
Bit[3:2]: Crystal oscillator output current
00: Weakest
11: Strongest
Bit[1:0]: Output Drive Select
00: Weakest
01: Double capability
10: Double capability
11: Triple drive current
09
COMC
0C
RW
0A
PIDH
96
R
Product ID Number MSB (Read only)
0B
PIDL
B1
R
Product ID Number LSB (Read only)
Common Control D
0C
COMD
28
RW
Bit[7]:
Reserved
Bit[6]:
Swap MSB and LSB at the output port
Bit[5:2]: Reserved
Bit[1]:
Sensor precharge voltage selection
0: Selects internal reference as precharge voltage
1: Selects SVDD as precharge voltage
Bit[0]:
Snapshot option
0: Enable live video output after snapshot sequence
1: Output single frame only
Common Control E
Bit[7]:
Bit[6]:
0D
18
COME
00
RW
Proprietary to OmniVision Technologies
Reserved
Anti-blooming control
0: Anti-blooming ON
1: Anti-blooming OFF
Bit[5:3]: Reserved
Bit[2]:
Clock output power-down pin status
0: Maintain internal default states at power-down
1: Tri-state the VSYNC and CHSYNC pins upon
power-down
Bit[1]:
Reserved
Bit[0]:
Digital port output
0: Enable data port output
1: Disable data port output
Version 1.3, September 15, 2003
Omni
Register Set
ision
Table 11
Address
(Hex)
Device Control Register List
Register
Name
Default
(Hex)
R/W
Description
Common Control F
Bit[7]:
0E
COMF
01
RW
System clock selection
0: Use 24 MHz system clock
1: Use 48 MHz system clock
Bit[6:3]: Reserved
Bit[2]:
Port output range selection
0: Output data range is [001] to [3FE]
1: Output data range is [000] to [3FF]
Bit[1]:
Reserved
Bit[0]:
AEC option
0: Disable this function
1: Enable larger AEC step increase with correct
exposure time
Common Control G
Bit[7]:
0F
COMG
47
RW
Optical black output selection
0: Disable
1: Enable
Bit[6]:
Black level calibrate selection
0: Use electrical black reference
1: Use optical black pixels to calibrate
Bit[5:4]: Reserved
Bit[3]:
Channel offset adjustment
0: Disable offset adjustment
1: Enable offset adjustment, B/Gb/Gr/R channel offset
levels stored in registers RBIAS (see “BBIAS” on
page 24), GbBIAS (see “GbBIAS” on page 24),
GrBIAS (see “GrBIAS” on page 24) and RBIAS (see
“RBIAS” on page 25).
Bit[2]:
Bit[1]:
Bit[0]:
Data range selection
0: Data range limited to [010] to [3F0]
1: Full range
ADC black level calibration bias selection
0: 040
1: 010
ADC black level calibration enable
0: Disable
1: Enable
Automatic Exposure Control Most Significant 8 bits for AEC[10:3] (least
significant 3 bits, AEC[2:0], in register COMB[2:0] - see “COMB” on
page 17).
10
AEC
43
RW
AEC[10:0]: Exposure time
TEX = tLINE x AEC[10:0]
Set COMI[2] = 0 (see “COMI” on page 21) to disable the AEC.
Version 1.3, September 15, 2003
Proprietary to OmniVision Technologies
19
OV9625/OV9121
Table 11
Address
(Hex)
CMOS SXGA (1.3 MPixel) CAMERACHIP™
Omni
ision
Device Control Register List
Register
Name
Default
(Hex)
R/W
Description
Clock Rate Control
Bit[7]:
11
CLKRC
00
RW
Bit[6]:
Bit[5:0]:
Internal PLL ON/OFF selection
0: PLL disabled
1: PLL enabled
Digital video port master/slave selection
0: Master mode, sensor provides PCLK
1: Slave mode, external PCLK input from XCLK1 pin
Clock divider
CLK = XCLK1/(decimal value of CLKRC[5:0] + 1)
Common Control H
Bit[7]:
SRST
1: Initiates soft reset. All register are set to factory
default values after which the chip resumes normal
operation
Bit[6]:
Resolution selection
0: SXGA
1: VGA
Average luminance value pixel counter ON/OFF
0: OFF
1: ON
Reserved
Master/slave selection
0: Master mode
1: Slave mode
Window output selection
0: Output only pixels defined by window registers
1: Output all pixels
Color bar test pattern
0: OFF
1: ON
Reserved
Bit[5]:
12
COMH
20
RW
Bit[4]:
Bit[3]:
Bit[2]:
Bit[1]:
Bit[0]:
20
Proprietary to OmniVision Technologies
Version 1.3, September 15, 2003
Omni
Register Set
ision
Table 11
Address
(Hex)
Device Control Register List
Register
Name
Default
(Hex)
R/W
Description
Common Control I
Bit[7]:
Bit[6]:
Bit[5]:
Bit[4]:
13
COMI
07
RW
Bit[3]:
Bit[2]:
Bit[1]:
Bit[0]:
AEC speed selection
0: Normal
1: Faster AEC correction
AEC speed/step selection
0: Small steps (slow)
1: Big steps (fast)
Banding filter ON/OFF
0: OFF
1: ON, set minimum exposure to 1/120s
Banding filter option
0: Set to 0, if system clock is 48 MHz and the PLL is
ON.
1: Set to 1, if system clock is 24 MHz and the PLL is ON
or if the system clock is 48 MHz and the PLL is OFF.
Reserved
AGC auto/manual control selection
0: Manual
1: Auto
AWB auto/manual control selection
0: Manual
1: Auto
Exposure control
0: Manual
1: Auto
Common Control J
Bit[7:6]:
AGC gain ceiling
00: 2x
01: 4x
10: 8x
11: 8x
Bit[5:4]: Reserved
Bit[3]:
Auto banding filter
0: Banding filter is always ON/OFF depending on
COMI[5] setting (see “COMI” on page 21)
14
COMJ
76
RW
Bit[2]:
Bit[1]:
Bit[0]:
Version 1.3, September 15, 2003
1: Automatically disable banding filter if light is low
VSYNC drop option
0: VSYNC is always output
1: VSYNC is dropped if frame data is dropped
Frame data drop option
0: Disable data drop
1: Drop data frame if exposure is not within tolerance.
In AEC mode, data is normally dropped when data is
out of range
Freeze current Exposure and Gain values
0: Normal
1: Freeze
Proprietary to OmniVision Technologies
21
OV9625/OV9121
Table 11
Address
(Hex)
CMOS SXGA (1.3 MPixel) CAMERACHIP™
Omni
ision
Device Control Register List
Register
Name
Default
(Hex)
R/W
Description
Common Control K
Bit[7]:
Bit[6]:
Bit[5]:
Bit[4]:
15
COMK
00
RW
Bit[3]:
Bit[2]:
Bit[1]:
Bit[0]:
16
RSVD
XX
–
CHSYNC pin output swap
0: CHSYNC
1: HREF
HREF pin output swap
0: HREF
1: CHSYNC
PCLK output selection
0: PCLK always output
1: PCLK output qualified by HREF
PCLK edge selection
0: Data valid on PCLK falling edge
1: Data valid on PCLK rising edge
HREF output polarity
0: Output positive HREF
1: Output negative HREF, HREF negative for data valid
Reserved
VSYNC polarity
0: Positive
1: Negative
HSYNC polarity
0: Positive
1: Negative
Reserved
Horizontal Window Start Most Significant 8 bits, LSB in register
COMM[1:0] (see “COMM” on page 26).
17
HREFST
1D
(13 in
VGA)
RW
HREFST[9:0]: Selects the beginning of the horizontal window,
each LSB represents two pixels. Adjustment steps
must be 2 pixels.
Note:
1. HFREFST[9:0] should be less than HREFEND[9:0].
2. For maximum output window size of 1292x1024, minimum value of
this register is 0x1C.
Horizontal Window end most significant 8 bits, LSB in register
COMM[3:2] (see “COMM” on page 26).
18
22
HREFEND
BD
(63 in
VGA)
RW
Proprietary to OmniVision Technologies
HREFEND[9:0]: Selects the end of the horizontal window, each
LSB represents two pixels. Adjustment steps
must be 2 pixels.
Note:
1. HREFEND[9:0] should be larger than HREFST[9:0].
2. For maximum output window size of 1292x1024, maximum value of
this register is 0xBD.
Version 1.3, September 15, 2003
Omni
Register Set
ision
Table 11
Address
(Hex)
Device Control Register List
Register
Name
Default
(Hex)
R/W
Description
Vertical Window line start most significant 8 bits, LSB in register
COMM[4] (see “COMM” on page 26).
Bit[8:0]:
19
VSTRT
01
(02 in
VGA)
RW
Selects the start of the vertical window, each LSB
represents four scan lines in SXGA or two scan lines in
VGA.
Note:
1. VSTRT[8:0] should be less than VEND[8:0].
2. For maximum output window size of 1292x1024, minimum value of
this register is 0x01.
Vertical Window line end most significant 8 bits, LSB in register
COMM[5] (see “COMM” on page 26).
Bit[8:0]:
1A
VEND
81
(7A in
VGA)
RW
Selects the end of the vertical window, each LSB
represents four scan lines in SXGA and two scan lines in
VGA.
Note:
1. VEND[8:0] should be larger than VSTRT[8:0].
2. For maximum output window size of 1292x1024, maximum value of
this register is 0x81.
Pixel Shift
Bit[7:0]:
Pixel delay count. Provides a method to fine tune the
output timing of the pixel data relative to the HREF pulse.
It physically shifts the video data output time in units of
pixel clock counts. The largest delay count is [FF] and is
equal to 255 x PCLK.
1B
PSHFT
00
RW
1C
MIDH
7F
R
Manufacturer ID Byte – High
(Read only = 0x7F)
1D
MIDL
A2
R
Manufacturer ID Byte – Low
(Read only = 0xA2)
1E-1F
RSVD
XX
–
Reserved
B Channel Offset Adjustment - auto controlled by internal circuit if
COMG[0] = 1 (see “COMG” on page 19)
20
BOFF
10
RW
Bit[7]:
Offset direction
Bit[6:0]:
0: Add BOFF[6:0]
1: Subtract BOFF[6:0]
B channel offset adjustment value
Gb Channel Offset Adjustment - auto controlled by internal circuit if
COMG[0] = 1 (see “COMG” on page 19)
21
GbOFF
0F
RW
Bit[7]:
Offset direction
Bit[6:0]:
0: Add GbOFF[6:0]
1: Subtract GbOFF[6:0]
Gb channel offset adjustment value
Gr Channel Offset Adjustment - auto controlled by internal circuit if
COMG[0] = 1 (see “COMG” on page 19)
22
GrOFF
Version 1.3, September 15, 2003
EF
RW
Bit[7]:
Offset direction
Bit[6:0]:
0: Add GrOFF[6:0]
1: Subtract GrOFF[6:0]
Gr channel offset adjustment value
Proprietary to OmniVision Technologies
23
OV9625/OV9121
Table 11
Address
(Hex)
CMOS SXGA (1.3 MPixel) CAMERACHIP™
Omni
ision
Device Control Register List
Register
Name
Default
(Hex)
R/W
Description
R Channel Offset Adjustment - auto controlled by internal circuit if
COMG[0] = 1 (see “COMG” on page 19)
23
ROFF
EF
RW
Bit[7]:
Offset direction
Bit[6:0]:
0: Add ROFF[6:0]
1: Subtract ROFF[6:0]
R channel offset adjustment value
Luminance Signal High Range for AEC/AGC Operation
24
AEW
A0
RW
25
AEB
88
RW
AEC/AGC values will decrease in auto mode when average
luminance is greater than AEW[7:0]
Luminance Signal Low Range for AEC/AGC Operation
AEC/AGC values will increase in auto mode when average
luminance is less than AEB[7:0].
Fast Mode Large Step Range Thresholds - effective only in AEC/AGC
fast mode (COMI[7] = 1, see “COMI” on page 21)
26
VV
F4
RW
Bit[7:4]:
High threshold
Bit[3:0]: Low threshold
AEC/AGC may change in larger steps when luminance average is
greater than VV[7:4] or less than VV[3:0].
B Channel Offset Manual Adjustment Value - effective only when
COMG[3] = 1 (see “COMG” on page 19).
27
BBIAS
80
RW
Bit[7]:
Offset direction
Bit[6:0]:
0: Add BBIAS[6:0]
1: Subtract BBIAS[6:0]
B channel offset adjustment value
Gb Channel Offset Manual Adjustment Value - effective only when
COMG[3] = 1 (see “COMG” on page 19).
28
GbBIAS
80
RW
Bit[7]:
Offset direction
Bit[6:0]:
0: Add GbBIAS[6:0]
1: Subtract GbBIAS[6:0]
Gb channel offset adjustment value
Gr Channel Offset Manual Adjustment Value - effective only when
COMG[3] = 1 (see “COMG” on page 19).
29
GrBIAS
80
RW
Bit[7]:
Offset direction
Bit[6:0]:
0: Add GrBIAS[6:0]
1: Subtract GrBIAS[6:0]
Gr channel offset adjustment value
Common Control L
Bit[7]:
2A
COML
00
RW
Bit[6:5]:
Bit[4]:
Bit[3:2]:
Bit[1:0]:
24
Proprietary to OmniVision Technologies
Line interval adjustment. Interval adjustment value is in
COML[6:5] and FRARL[7:0] (see “FRARL” on page 25).
0: Disabled
1: Enabled
Line interval adjust value MSB 2 bits
Reserved
HSYNC timing end point adjustment MSB 2 bits
HSYNC timing start point adjustment MSB 2 bits
Version 1.3, September 15, 2003
Omni
Register Set
ision
Table 11
Address
(Hex)
Device Control Register List
Register
Name
Default
(Hex)
R/W
Description
Line Interval Adjustment Value LSB 8 bits
2B
FRARL
00
RW
The frame rate will be adjusted by changing the line interval. Each LSB
will add 2/1520 Tframe in SXGA and 2/800 Tframe in VGA mode to the
frame period.
R Channel Offset Manual Adjustment Value - effective only when
COMG[3] = 1 (see “COMG” on page 19).
2C
RBIAS
80
RW
Bit[7]:
Offset direction
Bit[6:0]:
0: Add RBIAS[6:0]
1: Subtract RBIAS[6:0]
R channel offset adjustment value
VSYNC Pulse Width LSB 8 bits
2D
ADDVSL
00
RW
Bit[7:0]:
Line periods added to VSYNC width. Default VSYNC
output width is 4 x tline. Each LSB count will add 1 x tline
to the VSYNC active period.
VSYNC Pulse width MSB 8 bits
2E
2F
ADDVSH
YAVG
00
00
RW
RW
Bit[7:0]:
Line periods added to VSYNC width. Default VSYNC
output width is 4 x tline. Each MSB count will add
256 x tline to the VSYNC active period.
Luminance Average
This register will auto update when COMH[5] = 1 (see “COMH” on
page 20). Average Luminance is calculated from the B/Gb/Gr/R
channel average as follows:
(BAVG[7:0] + GbAVG[7:0] + GrAVG[7:0] +RAVG[7:0])/4
HSYNC Position and Width Start Point Lower 8 bits
30
HSDY
08
RW
This register and COML[1:0] (see “COML” on page 24) define the
HSYNC start position, each LSB will shift HSYNC start point by 1 pixel
period.
HSYNC Position and Width End Point Lower 8 bits
31
HEDY
Version 1.3, September 15, 2003
30
RW
This register and COML[3:2] (see “COML” on page 24) define the
HSYNC start position, each LSB will shift HSYNC start point by 1 pixel
period.
Proprietary to OmniVision Technologies
25
OV9625/OV9121
Table 11
Address
(Hex)
CMOS SXGA (1.3 MPixel) CAMERACHIP™
Omni
ision
Device Control Register List
Register
Name
Default
(Hex)
R/W
Description
Common Control M
32
COMM
0A
(0Ffor
VGA)
RW
Bit[7:6]: Reserved
Bit[5]:
Vertical window end position LSB (MSBs in register
VEND[7:0] - see “VEND” on page 23)
Bit[4]:
Vertical window start position LSB (MSBs in register
VSTRT[7:0] - see “VSTRT” on page 23)
Bit[3:2]: Horizontal window end position LSBs (MSBs in register
HREFST[7:0] - see “HREFEND” on page 22)
Bit[1:0]: Horizontal window start position LSBs (MSBs in register
HREFST[7:0] - see “HREFST” on page 22)
Note: For maximum output window size of 1292x1024, value of this
register should be 0x0D.
33
CHLF
28
RW
34
RSVD
XX
–
35
VBLM
90
RW
Reference Voltage Control
RW
Sensor Precharge Voltage Control
Bit[7]:
Reserved
Bit[6:4]: Sensor precharge voltage control
000: Lowest voltage
111: Highest voltage
Bit[3:0]: Sensor array common reference control
000: Lowest voltage
111: Highest voltage
36
26
Current Control
Bit[7:6]: Sensor current control
00: Minimum
11: Maximum
Bit[5]:
Sensor current range control
0:
CHLF[7:6] current control at normal range
1:
CHLF[7:6] current at half range
Bit[4]:
Sensor current double ON/OFF
0:
Normal
1:
Double current
Bit[3]:
Sensor buffer current control
0:
Normal
1:
Half current
Bit[2]:
Column buffer current control
0:
Normal
1:
Half current
Bit[1]:
Analog DSP current control
0:
Normal
1:
Half current
Bit[0]:
ADC current control
0:
Normal
1:
Half current
VCHG
17
Proprietary to OmniVision Technologies
Reserved
Version 1.3, September 15, 2003
Omni
Register Set
ision
Table 11
Address
(Hex)
37
38
Device Control Register List
Register
Name
Default
(Hex)
ADC
ACOM
04
12
R/W
Description
RW
ADC Reference Control
Bit[7:4]: Reserved
Bit[3]:
ADC input signal range
0:
Input signal x 1
1:
Input signal x 0.7
Bit[2:0]: ADC range control
000: Minimum
111: Maximum
RW
Analog Common Control
Bit[7]:
Analog gain control
0:
Normal
1:
Gain increase 1.5x
Bit[6]:
Analog black level calibration control
0:
Analog BLC ON
1:
Analog BLC OFF
Bit[5:0]: Reserved
NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.
Version 1.3, September 15, 2003
Proprietary to OmniVision Technologies
27
CMOS SXGA (1.3 MPixel) CAMERACHIP™
OV9625/OV9121
Omni
ision
Package Specifications
The OV9625/OV9121 uses a 48-pin ceramic package. Refer to Figure 21 for package information and Figure 22 for the array
center on the chip.
Figure 21 OV9625/OV9121 Package Specifications
.088 ± .011
.065 ± .007
.030 ± .002
.015 ± .002
.020 ± .002
.560 SQ + .012 / - .005
.430 SQ ± .005
.350 SQ ± .005
42
31
.440 ± .005
.06 + .010 / - .005
.040 ± .003
42
31
.032 MIN
.040 TYP
43
42
31
30
43
30
43
30
.022 ± .004
.001 to .005 TYP
.488
± .004
48
1
48
1
Pin 1
Index
Image
Plane
6
6
19
18
7
48
1
0.0287
.012 TYP
REF
18
7
R .0075
(4 CORNERS)
Table 12
18
R .0075
(48 PLCS)
6
7
.085 TYP
OV9625/OV9121 Package Dimensions
Dimensions
Millimeters (mm)
Inches (in.)
14.22 + 0.30 / -0.13 SQ
.560 + .012 / - .005 SQ
Package Height
2.23 + 0.28
.088 + .011
Substrate Height
0.51 + 0.05
.020 + .002
8.89 + 0.13 SQ
.350 + .005 SQ
Castellation Height
1.14 + 0.13
.045 + .005
Pin #1 Pad Size
0.51 x 2.16
.020 x .085
Pad Size
0.51 x 1.02
.020 x .040
Pad Pitch
1.02 + 0.08
.040 + .003
1.524 + 0.25 / -0.13
.06 + .010 / - .005
11.18 + 0.13
.440 + .005
12.40 + 0.10 SQ / 13.00 + 0.10 SQ
.488 + .004 SQ / .512 + .004 SQ
0.55 + 0.05
.022 + .002
Package Size
Cavity Size
Package Edge to First Lead Center
End-to-End Pad Center-Center
Glass Size
Glass Height
28
.020 TYP
19
19
Proprietary to OmniVision Technologies
Version 1.3, September 15, 2003
Omni
Package Specifications
ision
Sensor Array Center
Figure 22 OV9625/OV9121 Sensor Array Center
Package
Package Center
(0, 0)
Die
Sensor
Array
Positional Tolerances
Die shift (x,y) = 0.15 mm (6 mils) max.
Die tilt = 1 degrees max.
Die rotation = 3 degrees max.
1
Pin 1
Array Center
(15.7 µm, -271.6 µm)
(0.62 mil, -10.69 mil)
Important:
Most optical systems invert and mirror the image so the chip is usually
mounted on the board with pin 1 (SVDD) down as shown.
NOTE: Picture is for reference only, not to scale.
Version 1.3, September 15, 2003
Proprietary to OmniVision Technologies
29
OV9625/OV9121
CMOS SXGA (1.3 MPixel) CAMERACHIP™
Omni
ision
Note:
•
All information shown herein is current as of the revision and publication date. Please refer
to the OmniVision web site (http://www.ovt.com) to obtain the current versions of all
documentation.
•
OmniVision Technologies, Inc. reserves the right to make changes to their products or to
discontinue any product or service without further notice (It is advisable to obtain current product
documentation prior to placing orders).
•
Reproduction of information in OmniVision product documentation and specifications is
permissible only if reproduction is without alteration and is accompanied by all associated
warranties, conditions, limitations and notices. In such cases, OmniVision is not responsible
or liable for any information reproduced.
•
This document is provided with no warranties whatsoever, including any warranty of
merchantability, non-infringement, fitness for any particular purpose, or any warranty
otherwise arising out of any proposal, specification or sample. Furthermore, OmniVision
Technologies Inc. disclaims all liability, including liability for infringement of any proprietary
rights, relating to use of information in this document. No license, expressed or implied, by
estoppels or otherwise, to any intellectual property rights is granted herein.
•
‘OmniVision’, ‘CameraChip’ are trademarks of OmniVision Technologies, Inc. All other trade,
product or service names referenced in this release may be trademarks or registered trademarks of
their respective holders. Third-party brands, names, and trademarks are the property of their
respective owners.
For further information, please feel free to contact OmniVision at [email protected].
OmniVision Technologies, Inc.
1341 Orleans Drive
Sunnyvale, CA USA
(408) 542-3000
30
Proprietary to OmniVision Technologies
Version 1.3, September 15, 2003