PLL500-17 Low Phase Noise VCXO (17MHz to 36MHz) FEATURES • • VCXO output for the 17MHz to 36MHz range Low phase noise (-130 dBc @ 10kHz offset at 35.328MHz). CMOS output with OE tri-state control. 17 to 36MHz fundamental crystal input. Integrated high linearity variable capacitors. 12mA drive capability at TTL output. +/- 150 ppm pull range, max 5% linearity. Low jitter (RMS): 2.5ps period jitter. 2.5 to 3.3V operation. Available in 8-Pin SOIC, 6-pin SOT23 packages, or DIE. PIN CONFIGURATION XIN 1 VDD* 2 VIN 3 GND 4 PLL500-17 • • • • • • • • BLOCK DIAGRAM 8 XOUT 7 OE^ 6 VDD* 5 CLK ^: Denotes internal Pull-up *: Only one VDD pin needs to be connected DESCRIPTION FREQUENCY RANGE MULTIPLIER FREQUENCY No PLL 17 – 36 MHz XIN XOUT OUT 1 GND 2 CLK 3 PLL500-17 The PLL500-17 is a low cost, high performance and low phase noise VCXO for the 17 to 36MHz range, providing less than -130dBc at 10kHz offset at 35.328MHz. The very low jitter (2.5 ps RMS period jitter) makes this chip ideal for applications requiring voltage controlled frequency sources. Input crystal can range from 17 to 36MHz (fundamental resonant mode). 6 XIN 5 VDD 4 VIN 8-pin SOIC OUTPUT BUFFER CMOS 6-pin SOT XTAL OSC VARICAP OE VCON 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/29/05 Page 1 PLL500-17 Low Phase Noise VCXO (17MHz to 36MHz) DIE PAD LAYOUT 32 mil DIE SPECIFICATIONS (812,986) 8 1 XOUT XIN OE^ 7 39 mil 2 VDD VDD 6 3 VCON Name Value Size Reverse side Pad dimensions Thickness 39 x 32 mil GND 80 micron x 80 micron 10 mil CLK 5 4 GND DIE ID: PLL500-17: C500A0404-04A Y (0,0) X Note: ^ denotes internal pull up PIN ASSIGNMENT (8-pin SOIC package) AND PAD DESCRIPTION (8-pin SOIC package) Name Pin# XIN VDD VCON GND CLK VDD Die Pad Position Type Description 768.599 605.029 331.756 140.379 203.866 455.726 I P I P O P 715.472 626.716 I 476.906 888.881 I Crystal input pin. VDD power supply pin. Only one VDD pin is necessary. Frequency control voltage input pin. Ground pin. Output clock pin. VDD power supply pin. Only one VDD pin is necessary. Output Enable input pin. Disables the output when low. Internal pull-up enables output by default if pin is not connected to low. Crystal output pin. Ref Clock input. X (µm) Y (µm) 1 2 3 4 5 6 94.183 94.157 94.183 94.193 715.472 715.307 OE 7 XOUT 8 * OE (Output Enable) pin is not available in SOT-26 package, the output will always be enabled by the build in pull-up resister. PIN ASSIGNMNET AND DESCRIPTION (6-pin SOIC package) Name Pin# Type Description XOUT 1 I Crystal Output pin. Ref. Clock input. GND 2 P Ground pin. CLK 3 O Output clock pin. VCON 4 I Frequency control voltage input pin. VDD 5 P VDD power supply pin. XIN 6 I Crystal input pin. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/29/05 Page 2 PLL500-17 Low Phase Noise VCXO (17MHz to 36MHz) ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. V DD VI VO TS TA TJ -0.5 -0.5 -65 -40 Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model MAX. UNITS 4.6 V DD +0.5 V DD +0.5 150 85 125 260 2 V V V °C °C °C °C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. AC Electrical Specifications PARAMETERS SYMBOL CONDITIONS Input Crystal Frequency MIN. TYP. 17 Output Clock Rise/Fall Time Output Clock Duty Cycle 0.8V ~ 2.0V with 10 pF load 1.15 0.3V ~ 3.0V with 15 pF load 3.7 Measured @ 1.4V 45 50 MAX. UNITS 36 MHz ns 55 ±50 Short Circuit Current % mA 3. Voltage Control Crystal Oscillator PARAMETERS VCXO Stabilization Time * SYMBOL T VCXOSTB VCXO Tuning Range CLK output pullability VCXO Tuning Characteristic Pull range linearity Power Supply Rejection VCON pin input impedance VCON modulation BW PWSRR CONDITIONS From power valid F XIN = 12 – 25MHz; XTAL C 0 /C 1 < 250 0V ≤ VCON ≤ 3.3V VCON=1.65V, ±1.65V Frequency change with VDD varied +/- 10% 0V ≤ VCON ≤ 3.3V, -3dB MIN. TYP. MAX. UNITS 10 ms 300 ppm 100 5 ppm ppm/V % +1 ppm ±150 -1 2000 45 kΩ kHz Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 4. Jitter and Phase Noise Specifications 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/29/05 Page 3 PLL500-17 Low Phase Noise VCXO (17MHz to 36MHz) PARAMETERS CONDITIONS RMS Period Jitter (1 sigma – 1000 samples) Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier MIN. With capacitive decoupling between VDD and GND. 36MHz @100Hz offset 36MHz @1kHz offset 36MHz @10kHz offset 36MHz @100kHz offset 36MHz @1MHz offset TYP. MAX. UNITS 2.5 ps -80 -110 -130 -138 -145 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 5. DC Specifications PARAMETERS Supply Current, Dynamic, with Loaded Outputs Operating Voltage Output Low Voltage at CMOS level Output High Voltage at CMOS level Output drive current Short Circuit Current VCXO Control Voltage SYMBOL I DD CONDITIONS MIN. F XIN = 36MHz Output load of 15pF V DD TYP. MAX. UNITS 5 6 mA 3.63 V 0.4 V 2.25 V OLC I OL = +4mA V OHC I OH = -4mA V DD – 0.4 For V OL <0.4V or V OH >2.4V 8 V 9.5 V DD mA mA V MAX. UNITS 36 MHz pF 200 µW µW pF - ±50 VCON 0 6. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating (VCON = 1.65V) Maximum Sustainable Drive Level Operating Drive Level C0 C0/C1 ESR SYMBOL MIN. F XIN C L (xtal) 17 TYP. 8.5 50 RS 5 250 30 Ω Note: The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/29/05 Page 4 PLL500-17 Low Phase Noise VCXO (17MHz to 36MHz) PACKAGE INFORMATION 8 PIN ( dimensions in mm ) Narrow SOIC Symbol Min. Max. A 1.47 1.73 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 4.95 E 3.80 4.00 H 5.80 6.20 L 0.38 1.27 e 1.27 BSC E H D A A 1 C L e B 6-pin SOT (Dimensions in mm) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/29/05 Page 5 PLL500-17 Low Phase Noise VCXO (17MHz to 36MHz) ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL500-17 X X R NONE= TUBE R=TAPE and REEL Part Number Package S=SOIC T= SOT D=Die Temperature C=Commercial I= Industrial Part / Order Number Marking Package Option PLL500-17DC P500-17DC P500-17 P500-17 P500-17L P500-17L P500-17 P500-17 P500-17L P500-17L Die (Waffle Pack) 8-Pin SOIC (Tube) 8-Pin SOIC (Tape and Reel) 8-Pin SOIC (Tube) 8-Pin SOIC (Tape and Reel) 6-Pin SOT (Tube) 6-Pin SOT (Tape and Reel) 6-Pin SOT (Tube) 6-Pin SOT (Tape and Reel) PLL500-17SC PLL500-17SC-R PLL500-17SCL PLL500-17SCL-R PLL500-17TC PLL500-17TC-R PLL500-17TCL PLL500-17TCL-R PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/21/05 Page 6