PLL PLL502

Preliminary
PLL502-12
96MHz – 200MHz Low Phase Noise LVDS VCXO (12 – 25MHz Crystals)
FEATURES
•
•
•
•
•
Low phase noise output for the 96MHz to
200MHz range (-125 dBc at 10kHz offset).
LVDS output.
12 to 25MHz crystal input.
Integrated crystal load capacitor: no external
load capacitor required.
Output Enable selector.
Wide pull range (min. +/-190 ppm)
3.3V operation.
Available in 16 Pin TSSOP or SOIC.
DESCRIPTION
The PLL502-12 is a monolithic low jitter and low
phase noise (-125dBc/Hz @ 10kHz offset) VCXO IC
with LVDS output, for 96MHz to 200MHz output
range. It allows the control of the output frequency
with an input voltage (VIN), using a low cost crystal.
The chip provides a pullable output at a frequency of
F XIN x 8. This makes the PLL502-12 ideal for a wide
range of applications, including 155.52MHz for
SONET.
VDD
1
16
VDD
VDD
2
15
GND_BUF
XIN
3
14
CLKBAR
XOUT
4
13
VDD_BUF
OE
5
12
CLK
VIN
6
11
GND_BUF
GND
7
10
GND
GND
8
9
GND
PLL 502-12
•
•
•
PIN CONFIGURATION
F OUT = F XIN x 8
OE (Pin 5)
0
1 (Default)
Output State
Tri-state
Output enabled
BLOCK DIAGRAM
VCO
Divider
Reference
Divider
XIN
XOUT
XTAL
OSC
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
CLKBAR
CLK
OE
VARICAP
VIN
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 7/15/02 Page 1
Preliminary
PLL502-12
96MHz – 200MHz Low Phase Noise LVDS VCXO (12 – 25MHz Crystals)
PIN DESCRIPTIONS
Name
Number
Type
Description
VDD
1,2,16
P
+3.3V Power supply connectors.
XIN
3
I
Crystal input pin.
XOUT
4
I
Crystal output pin.
OE
5
I
Output enable input pin. Disables (tri-state) output when low. Internal
pull-up enables output by default if pin is not connected to low.
VIN
6
I
Frequency control voltage input pin.
GND
7,8,9,10
P
GND Power connectors.
GND_BUF
11,15
P
GND connector for output buffers.
CLK
12
O
True clock output pin.
VDD_BUF
13
P
+3.3V Power supply connector for output buffers.
CLKB
14
O
Complementary clock output pin.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
SYMBOL
MIN.
V DD
MAX.
UNITS
7
V
Input Voltage, dc
VI
V SS - 0.5
V DD + 0.5
V
Output Voltage, dc
VO
V SS - 0.5
V DD + 0.5
V
Storage Temperature
TS
-65
150
°C
Ambient Operating Temperature*
TA
-40
85
°C
Junction Temperature
TJ
125
°C
260
°C
2
kV
Lead Temperature (soldering, 10s)
Input Static Discharge Voltage Protection
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for INDUSTRIAL grade only.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 7/15/02 Page 2
Preliminary
PLL502-12
96MHz – 200MHz Low Phase Noise LVDS VCXO (12 – 25MHz Crystals)
2. Crystal Specifications
PARAMETERS
SYMBOL
Crystal Resonator
Frequency
Crystal Loading Rating
Crystal Pullability
CONDITIONS
MIN.
Parallel Fundamental
Mode
F XIN
12
At VIN = 1.65V
C L (xtal)
TYP.
MAX.
UNITS
25
MHz
9.5
pF
C 0 /C 1 (xtal)
AT cut
250
-
RE
AT cut
30
Ω
Recommended ESR
Note: Crystal Loading rating: 9.5pF is the loading the crystal sees from the VCXO chip at VIN = 1.65V. It is assumed that the crystal will be at nominal
frequency at this load. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may
reduce the pull range.
3. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
SYMBOL
T VCXOSTB
CONDITIONS
MIN.
From power valid
TYP.
MAX.
10
UNITS
ms
VCXO Tuning Range
F XIN = 12 - 25MHz;
XTAL C 0 /C 1 < 250
380
ppm
CLK output pullability
0V ≤ VCON ≤ 3.3V
±190
ppm
Linearity
5
VCXO Tuning Characteristic
10
115
VCON pin input impedance
VCON modulation BW
%
ppm/V
2000
kΩ
25
kHz
0V ≤ VCON ≤ 3.3V, -3dB
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
4. General Electrical Specifications
PARAMETERS
SYMBOL
Supply Current, Dynamic
(with Loaded Outputs)
I DD
Operating Voltage
V DD
Output Clock Duty Cycle
CONDITIONS
MIN.
TYP.
LVDS
3.13
@ 1.25V (LVDS)
Short Circuit Current
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
45
50
±50
MAX.
UNITS
60
mA
3.47
V
55
%
mA
Rev 7/15/02 Page 3
Preliminary
PLL502-12
96MHz – 200MHz Low Phase Noise LVDS VCXO (12 – 25MHz Crystals)
5. Jitter and Phase Noise specification
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Integrated jitter RMS at 155MHz
With capacitive decoupling
between VDD and GND.
With capacitive decoupling
between VDD and GND. Over
10,000 cycles.
Integrated 12 kHz to 20 MHz
Phase Noise relative to carrier
155MHz @10Hz offset
-60
dBc/Hz
Phase Noise relative to carrier
155MHz @100Hz offset
-90
dBc/Hz
Phase Noise relative to carrier
155MHz @1kHz offset
-112
dBc/Hz
Phase Noise relative to carrier
155MHz @10kHz offset
-125
dBc/Hz
Phase Noise relative to carrier
155MHz @100kHz offset
-123
dBc/Hz
Period jitter RMS at 155MHz
Accumulated jitter RMS at
155MHz
9
ps
TBM
ps
3
4
ps
Note: Phase Noise measured at VIN = 0V
6. LVDS Electrical Characteristics
PARAMETERS
Output Differential Voltage
V DD Magnitude Change
SYMBOL
MIN.
TYP.
MAX.
UNITS
V OD
247
355
454
mV
∆V OD
-50
50
mV
1.6
V
Output High Voltage
V OH
Output Low Voltage
V OL
Offset Voltage
CONDITIONS
1.4
R L = 100 Ω
(see figure)
0.9
1.1
V OS
1.125
1.2
1.375
V
Offset Magnitude Change
∆V OS
0
3
25
mV
Power-off Leakage
I OXD
±1
±10
uA
Output Short Circuit Current
I OSD
-5.7
-8
mA
V out = V DD or GND
V DD = 0V
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
V
Rev 7/15/02 Page 4
Preliminary
PLL502-12
96MHz – 200MHz Low Phase Noise LVDS VCXO (12 – 25MHz Crystals)
7. LVDS Switching Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Differential Clock Rise Time
tr
0.2
0.7
1.0
ns
Differential Clock Fall Time
tf
R L = 100 Ω
C L = 10 pF
(see figure)
0.2
0.7
1.0
ns
LVDS Levels Test Circuit
LVDS Switching Test Circuit
OUT
OUT
CL = 10pF
50Ω
VOD
VOS
VDIFF
RL = 100Ω
50Ω
CL = 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
0V (Differential)
OUT
80%
V DIFF
80%
0V
20%
20%
tR
tF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 7/15/02 Page 5
Preliminary
PLL502-12
96MHz – 200MHz Low Phase Noise LVDS VCXO (12 – 25MHz Crystals)
PACKAGE INFORMATION
16 PIN Narrow SOIC, TSSOP ( mm )
SOIC
TSSOP
Symbol
Min.
Max.
Min.
Max.
A
1.35
1.75
-
1.20
A1
0.10
0.25
0.05
0.15
B
0.33
0.51
0.19
0.30
C
0.19
0.25
0.09
0.20
D
9.80
10.00
4.90
5.10
E
3.80
4.00
4.30
H
5.80
6.20
L
0.40
1.27
e
E
H
D
4.50
6.40 BSC
0.45
1.27 BSC
0.75
A
A1
C
0.65 BSC
L
B
e
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL502-12 S C XX
PART NUMBER
REVISION CODE
(when applicable)
TEMPERATURATURE
C=COMMERCIAL
M=MILITARY
I=INDUSTRAL
PACKAGE TYPE
S=SOIC, O=TSSOP
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 7/15/02 Page 6