SCLS035E − MARCH 1984 − REVISED NOVEMBER 2004
D Wide Operating Voltage Range of 2 V to 6 V
D Operation From Very Slow Input
D
D
Transitions
Same Pinouts as ’HC08
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 20-µA Max ICC
Typical tpd = 14 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Allow Design of Either RC or Crystal
Oscillator Circuits
Temperature-Compensated Threshold
Levels
High Noise Immunity
1A
1B
1Y
2A
2B
2Y
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
4B
4A
4Y
3B
3A
3Y
SN54HC7001 . . . FK PACKAGE
(TOP VIEW)
1B
1A
NC
VCC
4B
D
D
D
D
D
D
D
SN54HC7001 . . . J OR W PACKAGE
SN74HC7001 . . . D, N, OR NS PACKAGE
(TOP VIEW)
description/ordering information
1Y
NC
2A
NC
2B
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4A
NC
4Y
NC
3B
2Y
GND
NC
3Y
3A
Each circuit functions as a quadruple AND gate.
They
perform
the
Boolean
function
Y + A • B or Y + A ) B in positive logic.
Because of the Schmitt action, the inputs have
different input threshold levels for positive- and
negative-going signals.
4
These circuits are temperature compensated and
can be triggered from the slowest of input ramps
and still give clean jitter-free output signals.
NC − No internal connection
ORDERING INFORMATION
PDIP − N
−40°C
−40
C to 85
85°C
C
−55°C
−55
C to 125
125°C
C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING
Tube of 25
SN74HC7001N
Tube of 50
SN74HC7001D
Reel of 2500
SN74HC7001DR
Reel of 250
SN74HC7001DT
SOP − NS
Reel of 2000
SN74HC7001NSR
HC7001
CDIP − J
Tube of 25
SNJ54HC7001J
SNJ54HC7001J
CFP − W
Tube of 150
SNJ54HC7001W
SNJ54HC7001W
LCCC − FK
Tube of 55
SNJ54HC7001FK
SOIC − D
SN74HC7001N
HC7001
SNJ54HC7001FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
!"#$%& "!&'& &(!)$'!& "#))%& ' !( *#+,"'!& '%- )!#" "!&(!)$ !
*%"("'!& *%) % %)$ !( %.' &)#$%& '&') /'))'&0)!#"!& *)!"%&1 !% &! &%"%'),0 &",#% %&1 !( ',,
*')'$%%)POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCLS035E − MARCH 1984 − REVISED NOVEMBER 2004
FUNCTION TABLE
(each gate)
INPUTS
A
B
OUTPUT
Y
H
H
H
L
X
L
X
L
L
logic diagram, each gate (positive logic)
A
Y
B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC7001
SN74HC7001
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
5
6
2
5
6
V
VCC
VI
Supply voltage
2
Input voltage
0
0
0
VCC
VCC
V
Output voltage
VCC
VCC
0
VO
TA
−55
125
−40
85
°C
Operating free-air temperature
V
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
&(!)$'!& "!&"%)& *)!#" & % (!)$'2% !)
%1& *'% !( %2%,!*$%&- ')'"%)" '' '& !%)
*%"("'!& ')% %1& 1!',- %.' &)#$%& )%%)2% % )1 !
"'&1% !) "!&&#% %% *)!#" /!# &!"%-
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCLS035E − MARCH 1984 − REVISED NOVEMBER 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
VT+
VT−
MAX
SN74HC7001
MIN
MAX
2V
0.7
1.2
1.5
0.7
1.5
0.7
1.5
4.5 V
1.55
2.5
3.15
1.55
3.15
1.55
3.15
6V
2.1
3.3
4.2
2.1
4.2
2.1
4.2
2V
0.3
0.6
1
0.3
1
0.3
1
4.5 V
0.9
1.6
2.45
0.9
2.45
0.9
2.45
6V
1.2
2
3.2
1.2
3.2
1.2
3.2
UNIT
V
V
0.6
1.2
0.2
1.2
0.2
1.2
0.4
0.9
2.1
0.4
2.1
0.4
2.1
6V
0.5
1.3
2.5
0.5
2.5
0.5
2.5
2V
1.9
1.998
1.9
1.9
IOH = −20 µA
4.5 V
4.4
4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
IOH = −4 mA
IOH = −5.2 mA
4.5 V
3.98
4.3
3.7
3.84
6V
5.48
5.8
5.2
5.34
2V
0.002
0.1
0.1
0.1
IOL = 20 µA
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
2
40
20
µA
10
10
10
pF
IOL = 4 mA
IOL = 5.2 mA
VI = VCC or 0
VI = VCC or 0,
MIN
0.2
VI = VIH or VIL
II
ICC
SN54HC7001
2V
VI = VIH or VIL
VOL
TA = 25°C
TYP
MAX
4.5 V
VT+ − VT−
VOH
MIN
IO = 0
6V
Ci
2 V to 6 V
3
V
V
V
V
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
TYP
MAX
SN54HC7001
SN74HC7001
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
60
130
195
163
tpd
A or B
Y
4.5 V
18
26
39
33
6V
14
22
33
28
2V
28
75
110
95
4.5 V
8
15
22
19
6V
6
13
19
16
tt
Any
MIN
MAX
MIN
MAX
UNIT
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per gate
No load
TYP
20
UNIT
pF
&(!)$'!& "!&"%)& *)!#" & % (!)$'2% !)
%1& *'% !( %2%,!*$%&- ')'"%)" '' '& !%)
*%"("'!& ')% %1& 1!',- %.' &)#$%& )%%)2% % )1 !
"'&1% !) "!&&#% %% *)!#" /!# &!"%-
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SCLS035E − MARCH 1984 − REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
Input
VCC
50%
50%
0V
CL = 50 pF
(see Note A)
tPLH
In-Phase
Output
LOAD CIRCUIT
50%
10%
tPHL
90%
90%
tr
Input
50%
10%
90%
90%
tr
VCC
50%
10% 0 V
tPHL
Out-of-Phase
Output
90%
tf
VOH
50%
10%
VOL
tf
tPLH
50%
10%
tf
50%
10%
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time, with one input transition per measurement.
D. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74HC7001D
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC7001DE4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC7001DR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC7001DRE4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC7001DT
ACTIVE
SOIC
D
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC7001DTE4
ACTIVE
SOIC
D
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC7001N
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TBD
Call TI
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
Lead/Ball Finish
MSL Peak Temp (3)
SN74HC7001N3
OBSOLETE
PDIP
N
14
SN74HC7001NE4
ACTIVE
PDIP
N
14
Call TI
SN74HC7001NSR
ACTIVE
SO
NS
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC7001NSRE4
ACTIVE
SO
NS
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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