THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS DS 3292 -1 SP8716/8/9 520MHz LOW CURRENT TWO-MODULUS DIVIDERS SP8716 ÷ 40/41, SP8718 ÷ 64/65, SP8719 ÷ 80/81 are 50mW programmable dividers with a maximum specified operating frequency of 520MHz over the temperature range -40 °C to + 85 °C. The signal (clock) inputs are biased internally and require to be capacitor coupled. The output stage is of an unusual low power design featuring dynamic pull-up, and optimised for driving CMOS. The 0 to 1 output edge should be used to give the best loop delay performance. MODULUS CONTROL UNIT 1 8 Vcc OUTPUT Vcc 2 7 NO CONNECTION OUTPUT 3 6 INPUT 0V 4 5 INPUT DECOUPLING SP 8716/8/9 DP8, MP8 FEATURES Figure : 1 Pin connections - top view DC to 520MHz Operation -40°C to +85°C Temperature Range Control Inputs and Outputs are CMOS Compatible QUICK REFERENCE DATA ABSOLUTE MAXIMUM RATINGS Supply voltage pin 2 or 8): Storage temperature range: Supply Voltage 5.0V ± 0.25V Supply Current 10.5mA typ. Max. Junction temperature: Max. clock I/P voltage: Vcc 8 Vcc 2 7k SIGNAL INPUT 6 5 ÷P/P + 1 3 OUTPUT 1.5k 4 0V 1k 1 MODULUS CONTROL INPUT Figure 2 : Functional diagram 300 8V -55°C to +150°C +175°C 2.5V p-p SP8716/8/9 ELECTRICAL CHARACTERISTICS Test conditions (unless otherwise stated):] Supply voltage: Vcc = +4/95 to 5.45V, Temperature: Tamb = -40°C to +85°C Value Characteristics Symbol Min. Max. frequency fmax 520 Min. frequency (sinewave input) fmin Power supply current ICC Output high voltage VOH Units Max. VOL Control input high voltage VINH 3.3 Control input low voltage VINL 0 Control input high current VINH Control input low current VINL Notes MHz Input 100-280mV p-p 1 30 MHz Input 400-800mV p-p 2 11.9 mA CL = 3pF; pins 2, 8 linked 1 V IL = -0.2mA 1 1 V IL = 0.2mA 1 8 V ÷P 1 1.7 V ÷P +1 1 0.41 mA VINH = 8V 1 mA VINL = 0V 1 ns CL = 10pF 2 (Vcc - 1.2) Output low voltage Conditions -0.20 Clock to output delay tp Set-up time ts 10 ns CL = 10pF 2 Release time tr 10 ns CL = 10pF 2 28 NOTES 1. Tested at 25°C only 2. Guaranteed but not tested NOTE The set-up time ts is defined as the minimum time that can elapse between a L → H transition of the control input and the next L → H clock pulse transition to ensure that the ÷P mode is obtained. The release time tr is defined as the minimum time that can elapse between a H → L transition of the control input and the next L → H clock pulse transition to ensure that the ÷(P +1) mode is obtain INPUT AMPLITUDE (mV p-p) Figure 3 : Timing diagram 1000 800 GUARANTEED * OPERATING WINDOW 600 400 280mV 200 520mV 0 30 100 200 300 400 500 FREQUENCY IN MHz Figure 4 : Typical input characteristics *Tested as specified in table of Electrical Characteristics SP8716/8/9 OPERATING NOTES 1. The inputs are biased internally and coupled to a signal source with suitable capacitors. 2. If no signal is present the devices will self-oscillate. If this is undesirable it may be prevented by connecting a 15k resistor from one input to pin 4 (ground). This will reduce the sensitivity. 3. The circuits will operate down to DC but slew rate must be better than 100V/,us. 4. The output stage is of an unusual design and is intended to interface with CMOS. External pull-up resistors or circuits must not be used. 5. This device is NOT suitable for driving TTL or its derivatives. Vcc CONTROL INPUT OUTPUT Figure 6 : Typical input impedance 1 8 2 7 3 6 4 5 50 MONITOR 50 SIGNAL SOURCE 1n 1n 0V Figure 5: Toggle frequency test circuit