PurePath Digital TAS5615 www.ti.com SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 160 W STEREO/300W MONO PurePath™ HD Analog-Input Power Stage Check for Samples: TAS5615 FEATURES 1 • 23 • • • • • • Active Enabled Integrated Feedback Provides: (PurePath™ HD Technology) – Signal Bandwidth up to 80 kHz for High-Frequency Content From High-Definition Sources – Ultralow 0.03% THD at 1 W into 8 Ω – 0.03% THD Across All Frequencies for Natural Sound at 1 W – 80-dB PSRR (BTL, No Input Signal) – >100-dB (A weighted) SNR – Click- and Pop-Free Start-Up – Minimal External Components Compared to Discrete Solutions Multiple Configurations Possible on the Same PCB: – Mono Parallel Bridge-Tied Load (PBTL) – 2.1 Single-Ended (SE) Stereo Pair and Bridge-Tied Load (BTL) Subwoofer – Quad Single-Ended (SE) Outputs Total Output Power at 10% THD+N – 300 W in Mono PBTL Configuration – 160 W per Channel in Stereo BTL – 80 W per Channel in Quad Single-Ended High Efficiency Power Stage (> 90%) With 120 mΩ Output MOSFETs Two Thermally Enhanced Package Options: – PHD (64-Pin QFP) – DKD (44-Pin PSOP3) Self-Protection Design (Including Undervoltage, Overtemperature, Clipping, and Short-Circuit Protection) With Error Reporting EMI Compliant When Used With Recommended System Design DESCRIPTION The TAS5615 is a high-performance analog input class-D amplifier with integrated closed-loop feedback technology (known as PurePath™ HD technology). It has the ability to drive up to 160 W (1) stereo into 8-Ω speakers from a single 50-V supply. PurePath HD technology enables traditional AB-amplifier performance (<0.03% THD) levels while providing the power efficiency of traditional class-D amplifiers. Ultralow 0.03% THD+N is flat across all frequencies, ensuring that the amplifier does not add uneven distortion characteristics, and helps maintain a natural sound. The efficiency of this class-D amplifier is greater than 90%. Undervoltage protection, overtemperature, clipping, short-circuit and overcurrent protection are all integrated, safeguarding the device and speakers against fault conditions that could damage the system. 3 ´ OPA1632 ♫♪ TM ANALOG AUDIO INPUT PurePath HD TAS5615 (2.1 Configuration) ♫♪ ♫♪ ±15 V 12 V 25 V–50 V TM PurePath HD Class-G Power Supply Ref. Design 110 VAC ® 240 VAC APPLICATIONS • • • • Mini Combo System AV Receivers DVD Receivers Active Speakers (1) Achievable output power levels are dependent on the thermal configuration of the target application. A high performance thermal interface material between the package exposed heatslug and the heat sink should be used to achieve high output power levels 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PurePath HD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2010, Texas Instruments Incorporated TAS5615 SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DEVICE INFORMATION Terminal Assignment The TAS5615 is available in two thermally enhanced packages: PurePath HD™ • 64-Pin QFP (PHD) Power Package • 44-Pin PSOP3 package (DKD) The package type contains a heat slug that is located on the top side of the device for convenient thermal coupling to the heat sink. DKD PACKAGE (TOP VIEW) 64-pins QFP package 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 GND_A GND_B GND_B OUT_B OUT_B PVDD_B PVDD_B BST_B BST_C PVDD_C PVDD_C OUT_C OUT_C GND_C GND_C GND_D OTW2 CLIP READY M1 M2 M3 GND GND GVDD_C GVDD_D BST_D OUT_D OUT_D PVDD_D PVDD_D GND_D 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PSU_REF VDD OC_ADJ RESET C_STARTUP INPUT_A INPUT_B VI_CM GND AGND VREG INPUT_C INPUT_D FREQ_ADJ OSC_IO+ OSC_IOSD OTW READY M1 M2 M3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 pins PACKAGE (TOP VIEW) OC_ADJ RESET C_STARTUP INPUT_A INPUT_B VI_CM GND AGND VREG INPUT_C INPUT_D FREQ_ADJ OSC_IO+ OSC_IOSD OTW1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDD PSU_REF NC NC NC NC GND GND GVDD_B GVDD_A BST_A OUT_A OUT_A PVDD_A PVDD_A GND_A PHD PACKAGE (TOP VIEW) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 GVDD_AB BST_A PVDD_A PVDD_A OUT_A OUT_A GND_A GND_B OUT_B PVDD_B BST_B BST_C PVDD_C OUT_C GND_C GND_D OUT_D OUT_D PVDD_D PVDD_D BST_D GVDD_CD PIN ONE LOCATION PHD PACKAGE Electrical Pin 1 Pin 1 Marker White Dot 2 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TAS5615 TAS5615 www.ti.com SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 MODE SELECTION PINS MODE PINS M3 M2 M1 ANALOG INPUT OUTPUT CONFIGURATION 0 0 0 Differential 2 × BTL AD mode 0 0 1 — — Reserved 0 1 0 Differential 2 × BTL BD mode 1 × BTL +2 × SE 4 × SE 0 1 1 Differential Single-ended 1 0 0 Single-ended 1 (1) 0 1 1 1 0 1 1 1 Differential 1 × PBTL DESCRIPTION AD mode, BTL differential AD mode INPUT_C (1) INPUT_D (1) 0 0 AD mode 1 0 BD mode Reserved INPUT_C and _D are used to select between a subset of AD and BD mode operations in PBTL mode (1 = VREG and 0 = AGND). PACKAGE HEAT DISSIPATION RATINGS (1) PARAMETER TAS5615PHD TAS5615DKD RqJC (°C/W) – 2 BTL or 4 SE channels 3.63 2.52 RqJC (°C/W) – 1 BTL or 2 SE channel(s) 5.95 3.22 RqJC (°C/W) – 1 SE channel 9.9 6.9 49 mm2 80 mm2 Pad area (1) (2) (2) JC is junction-to-case, CH is case-to-heat sink RqH is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heat sink and both channels active. The RqCH with this condition is 1.22°C/W for the PHD package and 1.02°C/W for the DKD package. Table 1. ORDERING INFORMATION (1) (1) TA PACKAGE DESCRIPTION 0°C–70°C TAS5615PHD 64-pin HTQFP 0°C–70°C TAS5615DKD 44-pin PSOP3 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TAS5615 3 TAS5615 SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) TAS5615 UNIT VDD to AGND –0.3 to 13.2 V GVDD to AGND –0.3 to 13.2 V PVDD_X to GND_X (2) –0.3 to 69.0 V (2) –0.3 to 69.0 V BST_X to GND_X (2) –0.3 to 82.2 V BST_X to GVDD_X (2) –0.3 to 69.0 V VREG to AGND –0.3 to 4.2 V GND_X to GND –0.3 to 0.3 V GND_X to AGND –0.3 to 0.3 V OC_ADJ, M1, M2, M3, OSC_IO+, OSC_IO–, FREQ_ADJ, VI_CM, C_STARTUP, PSU_REF to AGND –0.3 to 4.2 V OUT_X to GND_X INPUT_X RESET, SD, OTW1, OTW2, CLIP, READY to AGND –0.3 to 5 V –0.3 to 7.0 V Continuous sink current (SD, OTW1, OTW2, CLIP, READY) Operating junction temperature range, TJ Storage temperature, Tstg Electrostatic discharge (1) (2) (3) Human-body model (3) 9 mA 0 to 150 °C –40 to 150 °C ±2 kV ±500 V (all pins) Charged-device model (3) (all pins) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions. Failure to follow good anti-static ESD handling during manufacture and rework contributes to device malfunction. Make sure the operators handling the device are adequately grounded through the use of ground straps or alternative ESD protection. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MAX UNIT PVDD_x Half-bridge supply DC supply voltage MIN NOM 25 50 52.5 V GVDD_x Supply for logic regulators and gate-drive circuitry DC supply voltage 10.8 12 13.2 V VDD Digital regulator supply voltage DC supply voltage 10.8 12 13.2 V 7 8.0 RL(BTL) RL(SE) Output filter according to schematics in the application information section. Load impedance Ω 3.5 4.0 RL(PBTL) 3.5 4.0 LOUTPUT(BTL) 14 15 14 15 14 15 385 400 415 315 333 350 260 300 335 LOUTPUT(SE) Output filter inductance Minimum output inductance at IOC LOUTPUT(PBTL) Nominal PWM frame rate selectable for AM interference AM1 avoidance; 1% resistor tolerance AM2 fPWM Nominal; master mode RFREQ_ADJ PWM frame-rate programming resistor VFREQ_ADJ Voltage on FREQ_ADJ pin for slave mode operation TJ Junction temperature 4 mH 9.9 10 10.1 AM1; master mode 19.8 20 20.2 AM2; master mode 29.7 30 30.3 Slave mode kΩ 3.3 0 Submit Documentation Feedback kHz 150 °C Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TAS5615 TAS5615 www.ti.com SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 PIN FUNCTIONS PIN NAME FUNCTION (1) DESCRIPTION PHD NO. DKD NO. AGND 8 10 P Analog ground BST_A 54 43 P HS bootstrap supply (BST), external 0.033-mF capacitor to OUT_A required BST_B 41 34 P HS bootstrap supply (BST), external 0.033-mF capacitor to OUT_B required BST_C 40 33 P HS bootstrap supply (BST), external 0.033-mF capacitor to OUT_C required BST_D 27 24 P HS bootstrap supply (BST), external 0.033-mF capacitor to OUT_D required /CLIP 18 – O Clipping warning; open drain; active-low C_STARTUP 3 5 O Startup ramp requires a charging capacitor of 4.7 nF to AGND. FREQ_ADJ 12 14 I PWM frame-rate programming pin requires resistor to AGND. 7, 23, 24, 57, 58 9 P Ground GND_A 48, 49 38 P Power ground for half-bridge A GND_B 46, 47 37 P Power ground for half-bridge B GND_C 34, 35 30 P Power ground for half-bridge C GND_D 32, 33 29 P Power ground for half-bridge D GVDD_A 55 – P Gate-drive voltage supply requires 0.1-mF capacitor to GND_A. GVDD_B 56 – P Gate-drive voltage supply requires 0.1-mF capacitor to GND_B. GVDD_C 25 – P Gate-drive voltage supply requires 0.1-mF capacitor to GND_C. GVDD_D 26 - P Gate-drive voltage supply requires 0.1-µF capacitor to GND_D. GVDD_AB – 44 P Gate-drive voltage supply requires 0.22-mF capacitor to GND_A/GND_B. GVDD_CD – 23 P Gate-drive voltage supply requires 0.22-mF capacitor to GND_C/GND_D. INPUT_A 4 6 I Input signal for half bridge A INPUT_B 5 7 I Input signal for half bridge B INPUT_C 10 12 I Input signal for half bridge C INPUT_D 11 13 I Input signal for half bridge D M1 20 20 I Mode selection M2 21 21 I Mode selection M3 22 22 I Mode selection NC 59–62 – – No connect; pins may be grounded. OC_ADJ 1 3 O Analog overcurrent-programming pin requires resistor to ground: 64 pin QFP package (PHD) = 22 kΩ 44 pin PSOP3 Package (DKD) = 24 kΩ OSC_IO+ 13 15 I/O Oscillaotor master/slave output/input OSC_IO– 14 16 I/O Oscillaotor master/slave output/input /OTW – 18 O Overtemperature warning signal, open-drain, active-low /OTW1 16 – O Overtemperature warning signal, open-drain, active-low /OTW2 17 – O Overtemperature warning signal, open-drain, active-low OUT_A 52, 53 39, 40 O Output, half bridge A OUT_B 44, 45 36 O Output, half bridge B OUT_C 36, 37 31 O Output, half bridge C OUT_D 28, 29 27, 28 O Output, half bridge D 63 1 P PSU reference requires close decoupling of 330 pF to AGND. PVDD_A 50, 51 41, 42 P Power supply input for half-bridge A requires close decoupling of 2.2-mF capacitor to GND_A. PVDD_B 42, 43 35 P Power supply input for half-bridge B requires close decoupling of 2.2-mF capacitor to GND_B. PVDD_C 38, 39 32 P Power supply input for half-bridge C requires close decoupling of 2.2-mF capacitor to GND_C. GND PSU_REF (1) I = Input, O = Output, P = Power Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TAS5615 5 TAS5615 SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 www.ti.com PIN FUNCTIONS (continued) PIN NAME FUNCTION (1) DESCRIPTION PHD NO. DKD NO. 30, 31 25, 26 P Power supply input for half-bridge D requires close decoupling of 2.2-mF capacitor to GND_D. READY 19 19 O Normal operation; open drain; active-high RESET 2 4 I Device reset input, active-low; requires 47-kΩ pullup resistor to VREG SD 15 17 O Shutdown signal, open-drain, active-low VDD 64 2 P Power supply for internal voltage regulator requires a 10-mF capacitor with a 0.1-mF capacitor to GND for decoupling. VI_CM 6 8 O Analog comparator reference node requires close decoupling of 1 nF to GND. VREG 9 11 P Internal regulator supply filter pin requires 0.1-mF capacitor to GND. PVDD_D 6 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TAS5615 TAS5615 www.ti.com SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 TYPICAL SYSTEM BLOCK DIAGRAM Input DC Blocking Caps ANALOG_IN_A ANALOG_IN_B OSC_IO+ OSC_IO- VI_CM CLIP READY C_STARTUP Oscillator Synchronization OTW1, OTW2, OTW SD RESET (2) PSU_REF Caps for External Filtering & Startup/Stop System microcontroller or Analog circuitry BST_A BST_B OUT_A INPUT_A Input H-Bridge 1 INPUT_B Output H-Bridge 1 2 OUT_B 2 Hardwire PWM Frame Rate Adjust & Master/Slave Mode Input DC Blocking Caps ANALOG_IN_C ANALOG_IN_D FREQ_ADJ OUT_C Input H-Bridge 2 Output H-Bridge 2 2 OUT_D 8 50V PVDD 12V PVDD Power Supply Decoupling SYSTEM Power Supplies GND 8 2nd Order L-C Output Filter for each H-Bridge BST_D OC_ADJ AGND VDD VREG BST_C GND M3 GVDD_A, B, C, D M2 GND_A, B, C, D M1 PVDD_A, B, C, D 2 Hardwire Mode Control 2nd Order L-C Output Filter for each H-Bridge 2-CHANNEL H-BRIDGE BTL MODE INPUT_C INPUT_D Bootstrap Caps Bootstrap Caps 4 GVDD, VDD, & VREG Power Supply Decoupling Hardwire OverCurrent Limit GND GVDD (12V)/VDD (12V) VAC Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TAS5615 7 TAS5615 SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM CLIP READY OTW1 OTW2 SD PROTECTION & I/O LOGIC M1 M2 M3 RESET C_STARTUP STARTUP CONTROL VDD POWER-UP RESET UVP VREG VREG AGND TEMP SENSE GVDD_A GVDD_C GVDD_B OVER-LOAD PROTECTION GND GVDD_D CURRENT SENSE CB3C OC_ADJ OSC_SYNC_IO+ OSC_SYNC_IO- 4 OSCILLATOR PPSC 4 4 FREQ_ADJ PVDD_X OUT_X GND_X GVDD_A PSU_REF PWM ACTIVITY DETECTOR PVDD_X PSU_FF GND VI_CM BST_A PVDD_A PWM RECEIVER CONTROL TIMING CONTROL GATE-DRIVE OUT_A GND_A GVDD_B INPUT_A - ANALOG LOOP FILTER BST_B + PVDD_B INPUT_D ANALOG LOOP FILTER ANALOG LOOP FILTER - + ANALOG COMPARATOR MUX INPUT_C ANALOG LOOP FILTER ANALOG INPUT MUX INPUT_B PWM RECEIVER + CONTROL TIMING CONTROL GATE-DRIVE OUT_B GND_B GVDD_C BST_C PVDD_C PWM RECEIVER CONTROL TIMING CONTROL GATE-DRIVE + OUT_C GND_C - GVDD_D BST_D PVDD_D PWM RECEIVER CONTROL TIMING CONTROL GATE-DRIVE OUT_D GND_D 8 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TAS5615 TAS5615 www.ti.com SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 AUDIO CHARACTERISTICS (BTL) PCB and system configuraton are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 8 Ω, fS = 400 kHz, ROC = 22 kΩ, TC = 75°C, output filter: LDEM = 15 mH, CDEM = 680 nF, mode = 010, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX RL = 8 Ω, 10% THD+N, clipped output signal 160 RL = 8 Ω, 1% THD+N, unclipped output signal 125 UNIT PO Power output per channel THD+N Total harmonic distortion + noise 1W 0.05 % Vn Output integrated noise A-weighted, AES17 filter, input capacitor grounded 260 mV |VOS| Output offset voltage Inputs ac-coupled to AGND SNR Signal-to-noise ratio (1) 100 dB DNR Dynamic range 100 dB 2.3 W Pidle (1) (2) Power dissipation due to idle losses (IPVDD_X) PO = 0, 4 channels switching 40 (2) W 150 mV SNR is calculated relative to 1% THD+N output level. Actual system idle losses also are affected by core losses of output inductors. AUDIO SPECIFICATION (Single-Ended Output) PCB and system configuraton are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 4 Ω, fS = 400 kHz, ROC = 22 kΩ, TC = 75°C, output filter: LDEM = 15 mH, CDEM = 330 nF, MODE = 100, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX RL = 4 Ω, 10% THD+N, clipped output signal 75 RL = 4 Ω, 1% THD+N, unclipped output signal 60 UNIT PO Power output per channel THD+N Total harmonic distortion + noise 1W 0.05 % Vn Output integrated noise A-weighted 350 mV SNR Signal-to-noise ratio (1) A-weighted 93 dB DNR Dynamic range A-weighted 93 dB Pidle Power dissipation due to idle losses (IPVDD_X) PO = 0, 4 channels switching (2) 1.15 W (1) (2) W SNR is calculated relative to 1% THD+N output level. Actual system idle losses are affected by core losses of output inductors. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TAS5615 9 TAS5615 SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 www.ti.com AUDIO SPECIFICATION (PBTL) PCB and system configuraton are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 4 Ω, fS = 400 kHz, ROC = 22 kΩ, TC = 75°C, output filter: LDEM = 15 mH, CDEM = 680 nF, MODE = 101-BD, unless otherwise noted. PARAMETER PO TEST CONDITIONS Power output per channel MIN TYP MAX RL = 4 Ω, 10% THD+N, clipped output signal 300 RL = 6 Ω, 10% THD+N, clipped output signal 210 RL = 8 Ω, 10% THD+N, clipped output signal 160 RL = 4 Ω, 1% THD+N, unclipped output signal 240 RL = 6 Ω, 1% THD+N, unclipped output signal 160 RL = 8 Ω, 1% THD+N, unclipped output signal 125 UNIT W THD+N Total harmonic distortion + noise 1W 0.05 % Vn Output integrated noise A-weighted 260 mV SNR Signal-to-noise ratio (1) A-weighted 100 dB DNR Dynamic range A-weighted 100 dB Pidle Power dissipation due to idle losses (IPVDD_X) PO = 0, 4 channels switching (2) 2.3 W (1) (2) SNR is calculated relative to 1% THD+N output level. Actual system idle losses are affected by core losses of output inductors. ELECTRICAL CHARACTERISTICS PVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, TC (case temperature) = 75°C, fS = 400 kHz, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION VREG Voltage regulator, only used as reference node VI_CM Analog comparator reference node IVDD VDD supply current IGVDD_x Gate-supply current per half-bridge IPVDD_x Half-bridge idle current VDD = 12 V 3 3.3 3.6 V 1.5 1.75 1.9 V Operating, 50% duty cycle 22.5 Idle, reset mode 22.5 50% duty cycle mA 8 Reset mode mA 1.5 50% duty cycle without output filter or load Reset mode, no switching 7 mA 610 mA 33 kΩ 5 V ANALOG INPUTS RIN Input resistance VIN Maximum input voltage swing READY = HIGH IIN Maximum input current 342 mA G Voltage gain (VOUT/VIN) 23 dB OSCILLATOR Nominal, master mode fOSC_IO+ AM1, master mode FPWM × 10 AM2, master mode VIH High-level input voltage VIL Low-level input voltage 3.85 4 4.15 3.15 3.33 3.5 2.6 3 3.35 1.86 MHz V 1.45 V 120 200 mΩ 120 200 mΩ OUTPUT-STAGE MOSFETs RDS(on) 10 Drain-to-source resistance, low side (LS) TJ = 25°C, includes metallization resistance, Drain-to-source resistance, high side (HS) GVDD = 12 V Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TAS5615 TAS5615 www.ti.com SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 ELECTRICAL CHARACTERISTICS (continued) PVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, TC (case temperature) = 75°C, fS = 400 kHz, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I/O PROTECTION Undervoltage protection limit, GVDD_x and VDD Vuvp,G Vuvp,hyst (1) 9.5 V 0.6 V (1) Overtemperature warning 1 95 100 105 °C OTW2 (1) Overtemperature warning 2 115 125 135 °C OTWHYST Temperature drop needed below OTW temperture for OTW to be inactive after OTW event. OTW1 (1) OTE (1) Overtemperature error OTEOTWdifferential OTEHYST 25 (1) OLPC IOC (1) 145 155 °C 165 °C OTE-OTW differential 30 °C A reset must occur for SD to be released following an OTE event 25 °C fPWM = 400 kHz 2.6 ms Resistor – programmable, nominal continious current in 1-Ω load, 64 pin QFP package (PHD), ROCP = 22 kΩ 10 A Resistor – programmable, nominal continious current in 1-Ω load, 44 pin PSOP3 package (DKD), ROCP = 24 kΩ 10 A 10 A 150 ns 3 mA Overload protection counter Overcurrent limit protection IOC_LATCHED Overcurrent limit protection Resistor – programmable, continious current in 1-Ω load, ROCP = 47 kΩ IOCT Overcurrent response time Time from switching transition to flip-state induced by overcurrent IPD Output pulldown current of each half Connected when RESET is active to provide bootstrap charge. Not used in SE mode. STATIC DIGITAL SPECIFICATIONS VIH High-level input voltage VIL Low-level input voltage Leakage Input leakage current INPUT_X, M1, M2, M3, RESET 1.9 V 1.45 V 100 mA kΩ OTW/SHUTDOWN (SD) RINT_PU Internal pullup resistance, OTW1 to VREG, OTW2 to VREG, SD to VREG VOH High-level output voltage VOL Low-level output voltage IO = 4 mA FANOUT Device fanout OTW1, OTW2, SD, CLIP, READY No external pullup (1) Internal pullup resistor External pullup of 4.7 kΩ to 5 V 20 26 32 3 3.3 3.6 4.5 V 5 200 30 500 mV devices Specified by design. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TAS5615 11 TAS5615 SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 www.ti.com TYPICAL CHARACTERISTICS, BTL CONFIGURATION TOTAL HARMONIC+NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE THD+N - Total Harmonic Distortion + Noise - % 10 5 TC = 75°C PO - Output Power - W 2 1 0.5 0.2 0.1 8W 0.05 0.02 0.01 0.005 20m 100m 200m 1 2 10 20 PO - Output Power - W 100 200 Figure 1. Figure 2. UNCLIPPED OUTPUT POWER vs SUPPLY VOLTAGE SYSTEM EFFICIENCY vs OUTPUT POWER 150 140 100 TC = 75°C 90 130 8W 80 110 70 100 Efficiency - % PO - Output Power - W 120 90 80 180 TC = 75°C 170 160 THD+N at 10% 150 140 130 120 110 8W 100 90 80 70 60 50 40 30 20 10 0 25 27 29 31 33 35 37 39 41 43 45 47 49 PVDD - Supply Voltage - V 8W 70 60 50 60 50 40 30 40 30 20 TC = 75°C THD+N at 10% 20 10 0 25 27 29 31 33 35 37 39 41 43 45 47 49 PVDD - Supply Voltage - V 10 0 0 Figure 3. 12 40 80 120 160 200 240 280 2 Channels Output Power - W 320 Figure 4. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TAS5615 TAS5615 www.ti.com SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued) 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 OUTPUT POWER vs CASE TEMPERATURE 200 TC = 75°C THD+N at 10% THD+N at 10% 180 160 PO - Output Power - W Power Loss - W SYSTEM POWER LOSS vs OUTPUT POWER 8W 8W 140 120 100 80 60 40 20 0 40 80 120 160 200 240 280 2 Channels Output Power - W 320 0 10 20 30 Figure 5. 40 50 60 70 80 90 100 110 120 TC - Case Temperature - °C Figure 6. NOISE AMPLITUDE vs FREQUENCY 0 -20 Noise Amplitude - dB -40 TC = 75°C, VREF = 32.7 V, Sample Rate = 48 kHz, FFT Size = 16384 -60 -80 -100 -120 -140 -160 0 2 4 6 8 10 12 14 16 f - Frequency - kHz Figure 7. 18 20 22 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TAS5615 13 TAS5615 SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 www.ti.com TYPICAL CHARACTERISTICS, SE CONFIGURATION TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE 5 2 PO - Output Power - W THD+N - Total Harmonic Distortion + Noise - % 10 1 0.5 0.2 0.1 0.05 4W 6W 8W 0.02 0.01 0.005 20m 100m 200m 1 2 10 20 PO - Output Power - W 100 90 85 TC = 75°C 80 THD+N at 10% 75 70 4W 65 60 55 6W 50 45 40 35 30 8W 25 20 15 10 5 0 25 27 29 31 33 35 37 39 41 43 45 47 49 PVDD - Supply Voltage - V Figure 8. Figure 9. OUTPUT POWER vs CASE TEMPERATURE PO - Output Power - W 100 95 THD+N at 10% 90 4W 85 80 75 70 65 6W 60 55 50 8W 45 40 35 30 25 20 15 10 5 0 10 20 30 40 50 60 70 80 90 100 110 120 TC - Case Temperature - °C Figure 10. 14 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TAS5615 TAS5615 www.ti.com SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 TYPICAL CHARACTERISTICS, PBTL CONFIGURATION TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TC = 75°C 5 4W 2 6W 1 PO - Output Power - W THD+N - Total Harmonic Distortion + Noise - % 10 OUTPUT POWER vs SUPPLY VOLTAGE 8W 0.5 0.2 0.1 0.05 0.02 0.01 0.005 20m 100m 200m 1 2 10 20 100 200 500 PO - Output Power - W 340 T = 75°C C 320 THD+N at 10% 300 280 4W 260 240 220 6W 200 180 8W 160 140 120 100 80 60 40 20 0 25 27 29 31 33 35 37 39 41 43 45 47 49 PVDD - Supply Voltage - V Figure 11. Figure 12. OUTPUT POWER vs CASE TEMPERATURE 400 THD+N at 10% 360 4W PO - Output Power - W 320 280 6W 240 8W 200 160 120 80 40 0 10 20 30 40 50 60 70 80 90 100 110 120 TC - Case Temperature - °C Figure 13. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TAS5615 15 TAS5615 SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 www.ti.com APPLICATION INFORMATION PCB MATERIAL RECOMMENDATION FR-4 glass epoxy material with 2 oz. (70 mm) is recommended for use with the TAS5615. The use of this material can provide for higher power output, improved thermal performance, and better EMI margin, due to lower PCB trace inductance. PVDD CAPACITOR RECOMMENDATION The large capacitors used in conjunction with each full bridge are referred to as the PVDD capacitors. These capacitors should be selected for proper voltage margin and adequate capacitance to support the power requirements. In practice, with a well-designed system power supply, 1000 mF, 63 V will support more applications. The PVDD capacitors should be low-ESR type because they are used in a circuit associated with high-speed switching. DECOUPLING CAPACITOR RECOMMENDATIONS In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good audio performance, good-quality decoupling capacitors should be used. In practice, X7R should be used in this application. The voltage of the decoupling capacitors should be selected in accordance with good design practices. Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the selection of the 2.2 mF that is placed on the power supply to each half-bridge. It must withstand the voltage overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple current created by high power output. A minimum voltage rating of 63 V is required for use with a 50-V power supply. SYSTEM DESIGN RECOMMENDATIONS The following schematics and PCB layouts illustrate best practices in the use of the TAS5615. 16 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TAS5615 R_RIGHT_N IN_RIGHT_P IN_LEFT_N IN_LEFT_P /RESET 10uF C16 10uF C14 10uF C12 10uF C10 C17 100pF C15 100pF C13 100pF C11 100pF C18 100pF READY /CLIP /OTW2 /OTW1 /SD OSC_IO- OSC_IO+ 100R R13 100R R12 100R R11 100R R10 100R R18 GND VREG GND R19 47k GND GND GND GND GND 10k R21 100nF C22 R20 VREG 1nF C21 4.7nF 22.0k C20 GND 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GND /OTW1 /SD OSC_IO- OSC_IO+ FREQ_ADJ INPUT_D INPUT_C VREG AGND GND VI_CM INPUT_B INPUT_A C_STARTUP /RESET OC_ADJ GND C26 100nF C30 100nF GND 3.3R 61 C23 330pF C25 10uF 64 VDD 63 18 /OTW2 17 PSU_REF /CLIP 62 19 NC READY 60 NC M1 GND 20 NC 21 59 C31 100nF U10 VREG C33 100nF GND GND GND C32 100nF TAS5615PHD NC M3 22 M2 58 GND GND 23 GVDD_C R31 C40 33nF 3.3R 3.3R R33 R32 C43 33nF C63 2.2uF GND_D GND_C GND_C OUT_C OUT_C PVDD_C PVDD_C BST_C BST_B PVDD_B PVDD_B OUT_B OUT_B GND_B GND_B GND_A GND C60 2.2uF 26 3.3R GVDD_D 54 27 53 BST_A BST_D 56 GVDD_B 55 GVDD_A OUT_A OUT_D 28 52 OUT_A OUT_D 29 51 PVDD_A PVDD_D 30 50 PVDD_A PVDD_D 49 GND_A GND_D 31 57 GND GND 24 Product Folder Link(s) :TAS5615 25 Copyright © 2009–2010, Texas Instruments Incorporated 32 R30 48 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 GND C62 2.2uF C61 2.2uF GND L13 15uH 15uH L12 C42 33nF C41 33nF L11 15uH L10 15uH 1000uF C65 C53 680nF C52 680nF GND C51 680nF C50 680nF C72 1nF GND C73 1nF GND 1000uF C66 C71 1nF GND C70 1nF R73 3.3R C77 10nF C76 10nF R72 3.3R GND GND GND C68 47uF 63V R71 3.3R C75 10nF C74 10nF R70 3.3R C67 1000uF GND GND C69 2.2uF GND C64 1000uF GND PVDD GND PVDD GVDD/VDD (+12V) OUT_RIGHT_P + - GND OUT_RIGHT_M C78 10nF R74 3.3R OUT_LEFT_P + - OUT_LEFT_M PVDD GVDD/VDD (+12V) www.ti.com SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 TAS5615 Figure 14. Typical Differential Input BTL Application With BD Modulation Filters Submit Documentation Feedback 17 READY /CLIP /OTW2 /OTW1 /SD OSC_IO- OSC_IO+ IN_N IN_P /RESET 10uF 10uF 100R 100R 100R GND GND GND 100pF 100pF 100pF GND VREG 47k VREG GND GND GND GND GND 10k 100nF VREG 1nF 4.7nF 22.0k GND GND 1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 /OTW1 /SD OSC_IO- OSC_IO+ FREQ_ADJ INPUT_D INPUT_C VREG AGND GND VI_CM INPUT_B INPUT_A C_STARTUP /RESET OC_ADJ 330pF GND GND GND GND GND GND 100nF GND 100nF GND GND 100nF TAS5615PHD VREG 33nF 3.3R 3.3R 33nF GVDD_D 26 54 BST_A BST_D 27 100nF 59 3.3R 53 OUT_A OUT_D 28 100nF 55 GVDD_A 3.3R 52 OUT_A OUT_D 29 10uF 64 VDD /OTW2 17 63 PSU_REF /CLIP 18 60 61 62 NC READY 19 NC M1 20 NC M3 22 NC 58 GND GND 23 M2 57 GND GND 24 Product Folder Link(s) :TAS5615 25 Submit Documentation Feedback 21 56 GVDD_B GVDD_C 49 GND_A GND_D 51 PVDD_A PVDD_D 30 50 PVDD_A PVDD_D 31 18 32 VDD (+12V) 2.2uF 100V GND_D GND_C GND_C OUT_C OUT_C PVDD_C PVDD_C BST_C BST_B PVDD_B PVDD_B OUT_B OUT_B GND_B GND_B GND_A GND 2.2uF 100V 48 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 GND 2.2uF 100V 2.2uF 100V GND 33nF 33nF 15uH 15uH 15uH 15uH 1000uF 63V 1000uF 63V 680nF 250V GND 680nF 250V 1000uF 63V 1000uF 63V GND GND 1nF 100V 1nF 100V GND GND 47uF 63V GND 3.3R 10nF 100V 10nF 100V 3.3R GND + OUT_LEFT_P GND OUT_LEFT_M 10nF 100V 3.3R GND 2.2uF 100V GVDD (+12V) PVDD PVDD GVDD (+12V) TAS5615 SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 www.ti.com Figure 15. Typical Differential (2N) PBTL Application With BD Modulation Filters Copyright © 2009–2010, Texas Instruments Incorporated TAS5615 www.ti.com SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 3.3R VDD (+12V) 3.3R GVDD (+12V) 100nF 100nF 10uF 100nF 33nF 15uH A GND GND GND GND PVDD VREG 2.2uF 51 49 50 54 53 52 55 58 57 56 61 60 59 64 330 pF 63 /RESET 62 47k 100R GND GND GND 22.0k 1 GND 10uF 10nF 2 100pF 3 GND 100R 4 GND 5 GND_A PVDD_A PVDD_A OUT_A OUT_A BST_A GVDD_A GVDD_B NC GND GND NC NC NC VDD GND 100R IN_A PSU_REF 100pF OC_ADJ GND_A /RESET GND_B C_STARTUP GND_B INPUT_A OUT_B INPUT_B OUT_B 48 47 46 GND B 44 2.2uF IN_B 6 10uF VI_CM PVDD_B 15uH 45 33nF 43 100pF 1nF 7 GND 100nF VREG 8 GND 100R GND 9 IN_C GND 10uF 10 GND PVDD_B AGND BST_B TAS5615PHD VREG BST_C INPUT_C PVDD_C INPUT_D PVDD_C 42 PVDD 41 3.3R 47uF 63V 40 2.2uF 39 10nF 100pF 11 38 10k 2.2uF 12 100R GND 13 GND IN_D 14 10uF 100pF 15 16 FREQ_ADJ OUT_C OSC_IO+ OUT_C OSC_IO- GND_C /SD GND_C /OTW1 GND_D 33nF 37 15uH GND GND 36 GND C 35 34 GND 33 GND_D PVDD_D PVDD_D 30 31 32 OUT_D OUT_D 29 28 BST_D GVDD_D GVDD_C 26 OSC_IO+ 27 25 GND M3 GND 24 23 22 M2 M1 /CLIP READY 20 21 17 18 19 /OTW2 GND OSC_IO2.2uF PVDD /SD GND /OTW1 VREG 15uH /OTW2 D 33nF /CLIP GND 3.3R GVDD (+12V) READY 3.3R 100nF 100nF 10nF 100V 3.3R PVDD R_COMP 50 V 140 kOhm 49 V 160 kOhm GND 3.3R OUT_A_M A 100nF 100V R_COMP 10k PVDD 10nF 100V GND GND - 330nF 250V 100nF 100V R_COMP 10k PVDD - 330nF 250V + 48 V 180 kOhm <48 V 187 kOhm 470uF 50V 10k 470uF 50V 10k 100nF 100V 1% + GND 470uF 50V 10k 470uF 50V 10k 100nF 100V 1% GND OUT_A_P 1% GND OUT_B_M B OUT_B_P 3.3R GND 1% 3.3R GND 100V 10nF 100V 10nF GND 10nF 100V 3.3R GND 3.3R OUT_C_M C 100nF 100V R_COMP 10k PVDD - 330nF 250V 10k 100nF 100V R_COMP 10k PVDD 470uF 50V 10k 1% 100nF 100V 1% GND - 330nF 250V + 470uF 50V 10k 470uF 50V 10k 1% 1% 100nF 100V GND OUT_C_P 3.3R GND GND OUT_D_M D + 470uF 50V GND 10nF 100V OUT_D_P 3.3R GND 100V 10nF GND 100V 10nF GND Figure 16. Typical SE Application Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TAS5615 19 READY /CLIP /OTW2 /OTW1 /SD OSC_IO- OSC_IO+ IN_RIGHT IN_LEFT IN_CENTER_N IN_CENTER_P /RESET 10uF 10uF 10uF 10uF 160 kOhm 180 kOhm 187 kOhm 48 V <48 V 49 V R_COMP 140 kOhm 100pF 100pF 100pF 100pF 50 V GND GND GND GND GND 100pF PVDD 100R 100R 100R 100R 100R 47k VREG GND GND GND GND GND 10k 100nF VREG 1nF 10nF 22.0k GND GND 1 2 16 15 14 13 12 11 10 9 8 7 6 5 4 3 /OTW1 /SD OSC_IO- OSC_IO+ FREQ_ADJ INPUT_D INPUT_C VREG AGND GND VI_CM INPUT_B INPUT_A C_STARTUP /RESET OC_ADJ 330pF GND GND 61 VREG GND 59 100nF GND GND GND 100nF TAS5615PHD GND 33nF 3.3R 3.3R 33nF GVDD_D 26 GND GND 27 100nF BST_A BST_D 54 OUT_A OUT_D 28 10uF 53 OUT_A OUT_D 29 100nF 52 30 100nF 55 GVDD_A 3.3R 51 PVDD_A PVDD_D VDD (+12V) 57 GND GND 64 VDD /OTW2 17 63 PSU_REF /CLIP 18 56 GVDD_B GVDD_C 60 62 NC READY 19 NC M1 20 NC 21 NC M3 22 M2 58 GND GND 23 Product Folder Link(s) :TAS5615 24 Submit Documentation Feedback 25 49 GND_A GND_D 50 PVDD_A PVDD_D 31 20 32 3.3R 2.2uF 100V GND_D GND_C GND_C OUT_C OUT_C PVDD_C PVDD_C BST_C BST_B PVDD_B PVDD_B OUT_B OUT_B GND_B GND_B GND_A GND 2.2uF 100V 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 GND 2.2uF 100V 2.2uF 100V GND 15uH PVDD 15uH PVDD 33nF 33nF GND 470uF 50V 470uF 50V 10k 1% 470uF 50V GND 10k 1% 10k 1% R_COMP 10k 1% GND R_COMP GND 47uF 63V 470uF 50V 1000uF 63V GND 10k 10k 10nF 100V 3.3R GND 2.2uF 100V 15uH 680nF 250V GND 680nF 250V 15uH GND 330nF 250V GND GND 330nF 250V GND 100V 10nF 100nF 100V 100nF 100V 10nF 100V 100V 10nF 100nF 100V 100nF 100V 10nF 100V 1nF 100V 1nF 100V 1000uF 63V 3.3R GND 3.3R 3.3R GND 3.3R 3.3R 10nF 100V 10nF 100V 3.3R GND + GVDD (+12V) PVDD OUT_RIGHT_P + - OUT_RIGHT_M OUT_LEFT_P + - OUT_LEFT_M PVDD OUT_CENTER_P GND OUT_CENTER_M PVDD GVDD (+12V) TAS5615 SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 www.ti.com Figure 17. Typical 2.1 System Differential-Input BTL and Unbalanced-Input SE Application Copyright © 2009–2010, Texas Instruments Incorporated TAS5615 www.ti.com SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 THEORY OF OPERATION POWER SUPPLIES To facilitate system design, the TAS5615 needs only a 12-V supply in addition to the (typical) 50-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge. In order to provide outstanding electrical and acoustical characteristics, the PWM signal path, including gate drive and output stage, is designed as identical, independent half-bridges. For this reason, each half-bridge has separate gate-drive supply (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X). Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Although supplied from the same 12-V source, it is highly recommended to separate GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on the printed-circuit board (PCB) by RC filters (see application diagram for details). These RC filters provide the recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible. In general, inductance between the power supply pins and decoupling capacitors must be avoided. (See reference board documentation for additional information.) For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching frequencies in the range from 300 kHz to 400 kHz, it is recommended to use 33-nF ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned-on during the remaining part of the PWM cycle. Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is decoupled with a 2.2-mF ceramic capacitor placed as close as possible to each supply pin. It is recommended to follow the PCB layout of the TAS5615 reference design. For additional information on recommended power supply and required components, see the application diagrams in this data sheet. The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 50-V power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical as facilitated by the internal power-on-reset circuit. Moreover, the TAS5615 is fully protected against erroneous power-stage turnon due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are non-critical within the specified range (see the Recommended Operating Conditions table of this data sheet). SYSTEM POWER-UP/POWER-DOWN SEQUENCE Powering Up The TAS5615 does not require a power-up sequence. The outputs of the H-bridges remain in a high-impedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is recommended to hold RESET in a low state while powering up the device. This allows an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output. Powering Down The TAS5615 does not require a power-down sequence. The device remains fully operational as long as the gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TAS5615 21 TAS5615 SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 www.ti.com ERROR REPORTING The SD, OTW, OTW1 and OTW2 pins are active-low, open-drain outputs. Their function is for protection-mode signaling to a PWM controller or other system-control device. Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW and OTW2 go low when the device junction temperature exceeds 125°C and OTW1 goes low when the junction temperature exceeds 100°C (see the following table). SD OTW1 0 0 OTW2, OTW DESCRIPTION 0 Overtemperature (OTE) or overload (OLP) or undervoltage (UVP). Junction temperature higher than 125°C (overtemperature warning) 0 0 1 Overload (OLP) or undervoltage (UVP). Junction temperature higher than 100°C (overtemperature warning) 0 1 1 Overload (OLP) or undervoltage (UVP). Junction temperature lower than 100°C 1 0 0 Junction temperature higher than 125°C (overtemperature warning) 1 0 1 Junction temperature higher than 100°C (overtemperature warning) 1 1 1 Junction temperature lower than 100°C and no OLP or UVP faults (normal operation) Note that asserting either RESET low forces the SD signal high, independent of faults being present. TI recommends monitoring the OTW signal using the system microcontroller and responding to an overtemperature warning signal by, e.g., turning down the volume to prevent further heating of the device resulting in device shutdown (OTE). To reduce external component count, an internal pullup resistor to 3.3 V is provided on both SD and OTW outputs. Level compliance for 5-V logic can be obtained by adding external pullup resistors to 5 V (see the Electrical Characteristics section of this data sheet for further specifications). DEVICE PROTECTION SYSTEM The TAS5615 contains advanced protection circuitry carefully designed to facilitate system integration and ease of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as short circuits, overload, overtemperature, and undervoltage. The TAS5615 responds to a fault by immediately setting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other than overload and overtemperature error (OTE), the device automatically recovers when the fault condition has been removed, i.e., the supply voltage has increased. The device functions on errors, as shown in the following table BTL MODE PBTL MODE SE MODE LOCAL ERROR IN TURNS OFF LOCAL ERROR IN TURNS OFF LOCAL ERROR IN TURNS OFF A A+B A A+B+C+D A A+B B B C+D C C D D B C D C+D Bootstrap UVP does not shut down according to the table, it shuts down the respective half-bridge. PIN-TO-PIN SHORT CIRCUIT PROTECTION (PPSC) The PPSC detection system protects the device from permanent damage in the case that a power output pin (OUT_X) is shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent after the demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is performed at start-up, i.e., when VDD is supplied; consequently, a short to either GND_X or PVDD_X after system start-up does not activate the PPSC detection system. When PPSC detection is activated by a short on the output, all half-bridges are kept in a Hi-Z state until the short is removed; the device then continues the start-up sequence and starts switching. The detection is controlled globally by a two-step sequence. The first step ensures that there are no shorts from OUT_X to GND_X; the second step tests that there are no shorts from OUT_X to PVDD_X. The total duration of this process is roughly proportional to the capacitance of the 22 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TAS5615 TAS5615 www.ti.com SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 output LC filter. The typical duration is < 15 ms/mF. While the PPSC detection is in progress, SD is kept low, and the device does not react to changes applied to the RESET pin. If no shorts are present, the PPSC detection passes, and SD is released. A device reset does not start a new PPSC detection. PPSC detection is enabled in BTL and PBTL output configurations; the detection is not performed in SE mode. To make sure not to trip the PPSC detection system, it is recommended not to insert resistive load to GND_X or PVDD_X. OVERTEMPERATURE PROTECTION The two different package options have individual overtemperature protection schemes. PHD Package The TAS5615 PHD package option has a three-level temperature-protection system that asserts an active-low warning signal (OTW1) when the device junction temperature exceeds 100°C (typical), (OTW2) when the device junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted. Thereafter, the device resumes normal operation. DKD Package The TAS5615 DKD package option has a two-level temperature-protection system that asserts an active-low warning signal (OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted. Thereafter, the device resumes normal operation. UNDERVOLTAGE PROTECTION (UVP) AND POWER-ON RESET (POR) The UVP and POR circuits of the TAS5615 fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully operational when the GVDD_X and VDD supply voltages reach levels stated in the Electrical Characteristics table. Although GVDD_X and VDD are independently monitored, a supply-voltage drop below the UVP threshold on any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and SD being asserted low. The device automatically resumes operation when all supply voltages have increased above the UVP threshold. DEVICE RESET When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance (Hi-Z) state. In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high-impedance state when asserting the reset input low. Asserting the reset input low removes any fault information to be signalled on the SD output, i.e., SD is forced high. A rising-edge transition on reset input allows the device to resume operation after an overload fault. To ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the falling edge of SD. SYSTEM DESIGN CONSIDERATION A rising-edge transition on the reset input allows the device to execute the start-up sequence and starts switching. Apply only audio when the state of READY is high; that starts and stops the amplifier without having audible artifacts in the output transducers. If an overcurrent protection event is introduced, the READY signal goes low; hence, filtering is needed if the signal is intended for audio muting in non-microcontroller systems. The CLIP signal indicates that the output is approaching clipping. The signal can be used to decrease either an audio volume or an intelligent power supply controlling a low and a high rail. The device inverts the audio signal from input to output. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TAS5615 23 TAS5615 SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 www.ti.com The VREG pin is not recommended to be used as a voltage source for external circuitry. OSCILLATOR The oscillator frequency can be trimmed by external control of the FREQ_ADJ pin. To reduce interference problems while using a radio receiver tuned within the AM band, the switching frequency can be changed from nominal to lower values. These values should be chosen such that the nominal and the lower-value switching frequencies together result in the fewest cases of interference throughout the AM band. Switching frequencies can be selected by the value of the FREQ_ADJ resistor connected to AGND in master mode. For slave-mode operation, turn of the oscillator by pulling the FREQ_ADJ pin to VREG. This configures the OSC_I/O pins as inputs and must be slaved from an external clock. PRINTED CIRCUIT BOARD RECOMMENDATION Use an unbroken ground plane to have a good low-impedance and -inductance return path to the power supply for power and audio signals. PCB layout, audio performance and EMI are linked closely together. The circuit contains high, fast-switching currents; therefore, care must be taken to prevent damaging voltage spikes. Routing of the audio input should be kept short and together with the accompanied audio source ground. It is important to keep a solid local ground area underneath the device to minimize ground bounce. Netlist for this printed circuit board is generated from the schematic in Figure 14. 24 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TAS5615 TAS5615 www.ti.com SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 Note T1: PVDD decoupling bulk capacitors C60–C64 should be as close as possible to the PVDD and GND_X pins; the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without going through vias. No vias or traces should be blocking the current path. Note T2: Close decoupling of PVDD with low-impedance X7R ceramic capacitors is placed under the heat sink and close to the pins. Note T3: Heat sink must have a good connection to PCB ground. Note T4: Output filter capacitors, preferably metal film types, must be linear in the applied voltage range. Figure 18. Printed Circuit Board – Top Layer Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TAS5615 25 TAS5615 SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010 www.ti.com Note B1: It is important to have a direct low-impedance return path for high current back to the power supply. Keep impedance low from top to bottom side of PCB through a lot of ground vias. Note B2: Bootstrap low-impedance X7R ceramic capacitors placed on bottom side providing a short low-inductance current loop. Note B3: Return currents from bulk capacitors and output filter capacitors. Figure 19. Printed Circuit Board – Bottom Layer REVISION HISTORY Changes from Original (June 2009) to Revision A • Page Deleted Product Preview from the PHD package ................................................................................................................. 3 Changes from Revision A (September 2009) to Revision B Page • Changed pin location diagram .............................................................................................................................................. 2 • Replaced chip graphic in pinout diagram ............................................................................................................................. 2 • Changed several frame-rate specifications in the Recommended Operating Conditions .................................................... 4 • Changed specifications for oscillator frequencies in the Electrical Characteristics ............................................................ 10 • Changed response time for overload protection counter in Electrical Characteristics ....................................................... 11 • Revised component values on pins 6 and 63 in Typical SE Application illustration ........................................................... 19 26 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TAS5615 PACKAGE OPTION ADDENDUM www.ti.com 31-Mar-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TAS5615DKD ACTIVE HSSOP DKD 44 29 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR TAS5615DKDR ACTIVE HSSOP DKD 44 500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR TAS5615PHD ACTIVE HTQFP PHD 64 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-5A-260C-24 HR TAS5615PHDR ACTIVE HTQFP PHD 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-5A-260C-24 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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