SCHS319A − NOVEMBER 2002 − REVISED NOVEMBER 2004
D Inputs Are TTL-Voltage Compatible
D Speed of Bipolar F, AS, and S, With
E OR M PACKAGE
(TOP VIEW)
Significantly Reduced Power Consumption
1A
1Y
2A
2Y
3A
3Y
GND
D Greater Noise Immunity Than Standard
D
D
D
D
Inverters
Operates With Much Slower Than Standard
Input Rise and Fall Slew Rates
±24-mA Output Drive Current
− Fanout to 15 F Devices
SCR Latchup-Resistant CMOS Process and
Circuit Design
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
6A
6Y
5A
5Y
4A
4Y
description/ordering information
The CD74ACT14 contains six independent inverters. This device performs the Boolean function Y = A.
Each circuit functions as an independent inverter, but because of the Schmitt action, the inverters have different
input threshold levels for positive-going (VT+) and negative-going (VT−) signals.
ORDERING INFORMATION
PDIP − E
−55°C
125°C
−55
C to 125
C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SOIC − M
Tube
CD74ACT14E
Tube
CD74ACT14M
Tape and reel
CD74ACT14M96
TOP-SIDE
MARKING
CD74ACT14E
ACT14M
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each inverter)
INPUT
A
OUTPUT
Y
H
L
L
H
logic diagram, each inverter (positive logic)
A
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
!" #!$% &"'
&! #" #" (" " ") !"
&& *+' &! #", &" ""%+ %!&"
", %% #""'
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1
SCHS319A − NOVEMBER 2002 − REVISED NOVEMBER 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
TA = 25°C
−55°C
TO 125°C
MIN
MAX
MIN
−40°C
TO 85°C
MAX
MIN
UNIT
MAX
VCC
VI
Supply voltage
4.5
5.5
4.5
5.5
4.5
5.5
V
Input voltage
0
0
0
VCC
VCC
V
Output voltage
VCC
VCC
0
VO
IOH
VCC
VCC
High-level output current
−24
−24
−24
mA
IOL
∆t/∆v
Low-level output current
24
24
24
mA
Input transition rise or fall rate
20
20
20
ns/V
0
0
V
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
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SCHS319A − NOVEMBER 2002 − REVISED NOVEMBER 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
−55°C
TO 125°C
−40°C
TO 85°C
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
VT+
Positive-going
threshold
5V
1.4
2
1.4
2
1.4
2
V
VT−
Negative-going
threshold
5V
0.8
1.3
0.8
1.3
0.8
1.3
V
∆VT
Hysteresis
(VT+ − VT−)
5V
0.4
0.4
0.4
VOH
VOL
VI = VT+
VI = VT−
II
ICC
VI = VCC or GND
VI = VCC or GND,
DICC‡
Ci
VI = VCC − 2.1 V
V
IOH = −50 µA
IOH = −24 mA
IOH = −50 mA†
4.5 V
4.4
4.4
4.4
4.5 V
3.94
3.7
3.8
IOH = −75 mA†
IOL = 50 µA
5.5 V
4.5 V
0.1
0.1
0.1
IOL = 24 mA
IOL = 50 mA†
IOL = 75 mA†
4.5 V
0.36
0.5
0.44
5.5 V
V
3.85
3.85
5.5 V
V
1.65
5.5 V
IO = 0
1.65
5.5 V
±0.1
±1
±1
µA
5.5 V
4
80
40
µA
2.4
3
2.8
mA
10
10
10
4.5 V to 5.5 V
pF
† Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
‡ Additional quiescent supply current per input pin, TTL inputs high, 1 unit load
ACT INPUT LOAD TABLE
INPUT
UNIT LOAD
A
0.21
Unit load is ∆ICC limit specified in
electrical characteristics table
(e.g., 2.4 mA at 25°C).
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V " 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
A
Y
−55°C
TO 125°C
−40°C
TO 85°C
MIN
MAX
MIN
MAX
3.6
14.5
3.7
13.2
2.4
9.5
2.4
8.6
UNIT
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
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TYP
UNIT
45
pF
3
SCHS319A − NOVEMBER 2002 − REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION
S1
R1 = 500 Ω
From Output
Under Test
2 × VCC
Open
GND
CL = 50 pF
(see Note A)
R2 = 500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
3V
1.5 V
Input
LOAD CIRCUIT
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
CLR
Input
3V
Reference
Input
3V
1.5 V
1.5 V
0V
0V
trec
Data
Input
3V
1.5 V
CLK
th
tsu
1.5 V
10%
90%
90%
tr
0V
VOLTAGE WAVEFORMS
RECOVERY TIME
3V
1.5 V
10% 0 V
tf
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
3V
Input
1.5 V
1.5 V
0V
tPLH
In-Phase
Output
50%
10%
90%
90%
tr
90%
1.5 V
1.5 V
0V
tPHL
tPHL
Out-of-Phase
Output
3V
Output
Control
VOH
50% VCC
10%
VOL
tf
tPLH
50% VCC
10%
tf
50%
10%
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLZ
tPZL
20% VCC
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
≈VCC
20% VCC
VOL
80% VCC
VOH
80% VCC
≈0 V
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
Phase relationships between waveforms are arbitrary.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time, with one input transition per measurement.
F. tPLH and tPHL are the same as tpd.
G. tPZL and tPZH are the same as ten.
H. tPLZ and tPHZ are the same as tdis.
Figure 1. Load Circuit and Voltage Waveforms
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CD74ACT14E
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
CD74ACT14EE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
CD74ACT14M
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74ACT14M96
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74ACT14M96E4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74ACT14ME4
ACTIVE
SOIC
D
14
CU NIPDAU
Level-1-260C-UNLIM
50
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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