TI BQ71525DCKRG4

TPS715xx
www.ti.com
SLVS338O – MAY 2001 – REVISED JUNE 2007
50 mA, 24 V, 3.2 µA Supply Current
Low-Dropout Linear Regulator in SC70 Package
FEATURES
•
•
•
•
•
•
•
•
•
•
DESCRIPTION
24-V Maximum Input Voltage
Low 3.2-µA Quiescent Current at 50 mA
Stable With Any Capacitor (≥ 0.47 µF)
50-mA Low-Dropout Regulator
Available in 1.8 V, 1.9 V, 2.3 V, 2.5 V, 3.0 V, 3.3
V, 3.45 V, 5.0 V, and Adjustable (1.2 V to 15 V)
Designed to Support MSP430 Families:
– 1.9 V version ensured to be higher than
minimum VIN of 1.8 V
– 2.3 V version ensured to meet 2.2 V
minimum VIN for FLASH on MSP430F2xx
– 3.45 V version ensured to be lower than
maximum VIN of 3.6 V
– Wide variety of fixed output voltage
options to match VIN to the minimum
required for desired MSP430 speed
Minimum/Maximum Specified Current Limit
5-Pin SC70/SOT-323 (DCK) Package
–40°C to +125°C Specified Junction
Temperature Range
For 80 mA Rated Current and Higher Power
Package, see TPS715Axx
The TPS715xx low-dropout (LDO) voltage regulators
offer the benefits of high input voltage, low-dropout
voltage, low-power operation, and miniaturized
packaging. The devices, which operate over an input
range of 2.5 V to 24 V, are stable with any capacitor
(≥ 0.47 µF). The low dropout voltage and low
quiescent current allow operations at extremely low
power levels. Therefore, the devices are ideal for
powering battery management ICs. Specifically,
since the devices are enabled as soon as the applied
voltage reaches the minimum input voltage, the
output is quickly available to power continuously
operating battery charging ICs.
The usual PNP pass transistor has been replaced by
a PMOS pass element. Because the PMOS pass
element behaves as a low-value resistor, the low
dropout voltage, typically 415 mV at 50 mA of load
current, is directly proportional to the load current.
The low quiescent current (3.2 µA typically) is stable
over the entire range of output load current (0 mA to
50 mA).
APPLICATIONS
•
•
•
Ultra Low Power Microcontrollers
Cellular/Cordless Handsets
Portable/Battery-Powered Equipment
DCK PACKAGE
(TOP VIEW)
FB/NC
1
GND
2
NC
3
IN
5
OUT
4
IN
Solar
Cell
TPS715xx
OUT
GND
MSP430
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2007, Texas Instruments Incorporated
TPS715xx
www.ti.com
SLVS338O – MAY 2001 – REVISED JUNE 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION (1)
VOUT (2)
PRODUCT
TPS715xxyyyz
(1)
(2)
XX is nominal output voltage (for example, 28 = 2.8 V, 285 = 2.85 V, 01 = Adjustable).
YYY is package designator.
Z is package quantity.
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Output voltages from 1.25 V to 5.4 V in 50 mV increments are available through the use of innovative factory EEPROM programming;
minimum order quantities may apply. Contact factory for details and availability.
ABSOLUTE MAXIMUM RATINGS
over operating temperature range (unless otherwise noted) (1) (2)
UNIT
VIN range
–0.3 V to +24 V
VOUT range
–0.3 V to +16.5 V
Peak output current
Internally limited
ESD rating, HBM
2 kV
ESD rating, CDM
500 V
Continuous total power dissipation
See Dissipation Rating Table
Junction temperature range, TJ
–40°C to +150°C
Storage temperature range, Tstg
–65°C to +150°C
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
RθJC°C/W
RθJA°C/W
DERATING FACTOR
ABOVE TA = +25°C
Low-K (1)
DCK
165
395
2.52 mW/°C
250 mW
140 mW
100 mW
High-K (2)
DCK
165
315
3.18 mW/°C
320 mW
175 mW
130 mW
(1)
(2)
2
TA≤ 25°C
TA = +70°C
TA = +85°C
POWER RATING POWER RATING POWER RATING
BOARD
The JEDEC Low-K (1s) board design used to derive this data was a 3 inch × 3 inch, two-layer board with 2 ounce copper traces on top
of the board.
The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch × 3 inch, multilayer board with 1 ounce internal power and
ground planes and 2 ounce copper traces on top and bottom of the board.
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SLVS338O – MAY 2001 – REVISED JUNE 2007
ELECTRICAL CHARACTERISTICS
Over operating junction temperature range (TJ = –40°C to +125°C), VIN = VOUT(NOM) + 1 V, IOUT = 1 mA, and COUT = 1 µF,
unless otherwise noted. Typical values are at TJ = +25°C.
PARAMETER
TEST CONDITIONS
Input voltage (1)
VIN
Ground pin
Over VIN, IOUT, and T
current (2)
IGND
TYP
UNIT
24
IO = 50 mA
3
24
1.2
15
V
–4.0
+4.0
%
VIN + 1.0 V ≤ VIN ≤ 24 V
100 µA ≤ IOUT ≤ 50 mA
0 ≤ IOUT ≤ 50 mA, TJ = –40°C to +85°C
3.2
4.2
0 mA ≤ IOUT ≤ 50 mA
3.2
4.8
0 mA ≤ IOUT ≤ 50 mA, VIN = 24 V
∆VOUT/∆IOUT
IOUT = 100 µA to 50 mA
22
Output voltage
line regulation (1)
∆VOUT/∆VIN
VOUT + 1 V < VIN ≤ 24 V
20
BW = 200 Hz to 100 kHz, COUT = 10 µF,
IOUT = 50 mA
Output noise voltage
Vn
Output current limit
ICL
Power-supply ripple rejection
PSRR
f = 100 kHz, COUT = 10 µF
Dropout voltage
VIN = VOUT(NOM)– 1 V
VDO
IOUT = 50 mA
V
µA
5.8
Load regulation
(1)
(2)
MAX
2.5
VOUT voltage range (TPS71501)
VOUT accuracy (1)
MIN
IO = 10 mA
mV
60
mV
µVrms
575
VOUT = 0 V, VIN ≥ 3.5 V
125
750
mA
VOUT = 0 V, VIN < 3.5 V
90
750
mA
60
415
dB
750
mV
Minimum VIN = VOUT + VDO or the value shown for Input voltage in this table, whichever is greater.
See Figure 1. The TPS715xx family employs a leakage null control circuit. This circuit is active only if output current is less than pass
FET leakage current. The circuit is typically active when output load is less than 5 µA, VIN is greater than 18 V, and die temperature is
greater than 100°C.
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SLVS338O – MAY 2001 – REVISED JUNE 2007
FUNCTIONAL BLOCK DIAGRAMS
V(OUT)
V(IN)
Current
Sense
Leakage Null
Control Circuit
ILIM
_
GND
R1
+
FB
R2
Vref = 1.205 V
Bandgap
Reference
Figure 1. Functional Block Diagram—Adjustable Version
V(OUT)
V(IN)
Current
Sense
Leakage Null
Control Circuit
ILIM
_
GND
Bandgap
Reference
R1
+
Vref = 1.205 V
R2
Figure 2. Functional Block Diagram—Fixed Version
Table 1. Terminal Functions
TERMINAL
NAME
NO.
FIXED
FB
4
DESCRIPTION
ADJ.
1
Adjustable version. This terminal is used to set the output voltage.
NC
1
No connection
GND
2
2
Ground
NC
3
3
No connection
IN
4
4
Input supply.
OUT
5
5
Output of the regulator, any output capacitor ≥ 0.47 µF can be used for stability.
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SLVS338O – MAY 2001 – REVISED JUNE 2007
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
3.320
3.32
VOUT − Output Voltage − V
3.305
3.300
3.295
3.290
10
20
30
40
3.28
3.27
3.26
VIN = 4.3 V
COUT = 1 µF
−40 −25 −10 5
20 35 50 65 80 95 110 125
TJ − Junction Temperature − °C
Figure 5.
OUTPUT SPECTRAL
NOISE DENSITY
vs
FREQUENCY
OUTPUT IMPEDANCE
vs
FREQUENCY
DROPOUT VOLTAGE
vs
OUTPUT CURRENT
600
VIN = 4.3 V
VOUT = 3.3 V
COUT = 1 µF
TJ = 25°C
16
6
IOUT = 50 mA
4
3
2
14
12
V DO − Dropout Voltage − mV
VIN = 4.3 V
VOUT = 3.3 V
COUT = 1 µF
IOUT = 1 mA
10
8
6
IOUT = 1 mA
4
2
1
0
100
1k
10 k
f − Frequency − Hz
100 k
VIN = 3.2 V
COUT = 1 µF
500
TJ = 125°C
400
TJ = 25°C
300
200
TJ = −40°C
100
IOUT = 50 mA
0
10
100
1k
10k
100k
1M
0
10 M
0
f − Frequency − Hz
10
20
30
40
IOUT − Output Current − mA
Figure 6.
Figure 7.
Figure 8.
TPS71501
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
POWER-SUPPLY
RIPPLE REJECTION
vs
FREQUENCY
1
600
IOUT = 50 mA
VIN = 3.2 V
0.8
V DO − Dropout Voltage − mV
0.9
TJ = 125°C
0.7
TJ = 25°C
0.6
0.5
0.4
TJ = −40°C
0.3
0.2
500
IOUT = 50 mA
400
300
200
IOUT = 10 mA
100
0.1
0
0
2.5
2
18
5
3
Figure 4.
8
7
3.5
Figure 3.
Zo − Output Impedance − Ω
Hz
µ V/
IOUT = 50 mA
3.29
VIN = 4.3 V
VOUT = 3.3 V
IOUT = 1 µF
4
3.30
3.25
−40 −25 −10 5 20 35 50 65 80 95 110 125
TJ − Junction Temperature − °C
50
IO − Output Current − mA
Output Spectral Noise Density −
IOUT = 1 mA
3
6
9
VIN − Input Voltage − V
Figure 9.
12
15
0
−40 −25 −10 5 20 35 50 65 80 95 110 125
TJ − Junction Temperature − °C
Figure 10.
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PSRR − Power Supply Ripple Rejection − dB
VOUT − Output Voltage − V
3.31
3.310
0
4.5
IGND − Ground Current − µ A
VIN = 4.3 V
COUT = 1 µF
TJ = 25°C
3.315
V DO − Dropout Voltage − V
QUIESCENT CURRENT
vs
JUNCTION TEMPERATURE
50
100
VIN = 4.3 V
VOUT = 3.3 V
COUT = 10 µF
TJ = 25°C
90
80
70
60
IOUT = 1 mA
50
40
30
20
IOUT = 50 mA
10
0
10
100
1k
10k
100k
1M
10 M
f − Frequency − Hz
Figure 11.
5
TPS715xx
www.ti.com
SLVS338O – MAY 2001 – REVISED JUNE 2007
TYPICAL CHARACTERISTICS (continued)
DVOUT − Change in
Output Voltage − mV
VIN − Input Voltage − V
VOUT − Output Voltage − V
6
5
4
3
VIN
2
VOUT
1
0
0
2
4
6
8 10 12 14
t − Time − ms
Figure 12.
6
16 18
20
VIN − Input Voltage − V
VOUT = 3.3 V
RL = 66 Ω
COUT = 10 µF
7
VOUT = 3.3 V
IOUT = 50 mA
COUT = 10 µF
100
50
0
−50
5.3
4.3
0
50 100 150 200 250 300 350 400 450 500
t − Time − µs
Figure 13.
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LOAD TRANSIENT RESPONSE
DVOUT - Change in
Output Voltage - mV
LINE TRANSIENT RESPONSE
IOUT - Output Current - mA
POWER-UP / POWER-DOWN
8
400
200
VIN = 4.3 V
VOUT = 3.3 V
COUT = 10 mF
0
-200
60
40
20
0
0 100 200 300 400 500 600 700 800 900 1000
ms
t − Time −
Figure 14.
TPS715xx
www.ti.com
SLVS338O – MAY 2001 – REVISED JUNE 2007
APPLICATION INFORMATION
The TPS715xx family of LDO regulators has been optimized for ultra-low power applications such as the
MSP430 microcontroller. Its ultra-low supply current maximizes efficiency at light loads, and its high input
voltage range makes it suitable for supplies such as unconditioned solar panels.
VIN
IN
C1
0.1 µF
TPS71533
OUT
GND
VOUT
0.47 µF
Figure 15. Typical Application Circuit (Fixed Voltage Version)
External Capacitor Requirements
Although not required, a 0.047-µF or larger input bypass capacitor, connected between IN and GND and located
close to the device, is recommended to improve transient response and noise rejection of the power supply as a
whole. A higher-value input capacitor may be necessary if large, fast-rise-time load transients are anticipated
and the device is located several inches from the power source.
The TPS715xx requires an output capacitor connected between OUT and GND to stabilize the internal control
loop. Any capacitor (including ceramic and tantalum) ≥ 0.47 µF properly stabilizes this loop. X7R type capacitors
are recommended but X5R and others may be used.
Power Dissipation and Junction Temperature
To ensure reliable operation, worst-case junction temperature should not exceed +125°C. This restriction limits
the power dissipation the regulator can handle in any given application. To ensure the junction temperature is
within acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD,
which must be less than or equal to PD(max).
The maximum-power-dissipation limit is determined using the following equation:
T max * T
A
P
+ J
D(max)
R
qJA
(1)
where:
• TJmax is the maximum allowable junction temperature.
• RθJA is the thermal resistance junction-to-ambient for the package (see the Dissipation Ratings table).
• TA is the ambient temperature.
The regulator dissipation is calculated using:
P D + ǒVIN*V OUTǓ I OUT
(2)
For a higher power package version of the TPS715xx, see the TPS715Axx.
Regulator Protection
The TPS715xx PMOS-pass transistor has a built-in back diode that conducts reverse current when the input
voltage drops below the output voltage (e.g., during power-down). Current is conducted from the output to the
input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting might be
appropriate.
The TPS715xx features internal current limiting. During normal operation, the TPS715xx limits output current to
approximately 500 mA. When current limiting engages, the output voltage scales back linearly until the
overcurrent condition ends. Take care not to exceed the power dissipation ratings of the package.
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TPS715xx
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APPLICATION INFORMATION (continued)
Programming the TPS71501 Adjustable LDO Regulator
The output voltage of the TPS71501 adjustable regulator is programmed using an external resistor divider as
shown in Figure 16. The output voltage operating range is 1.2 V to 15 V, and is calculated using:
ǒ1 ) R1
Ǔ
R2
V OUT + VREF
(3)
where:
• VREF = 1.205 V typ (the internal reference voltage)
Resistors R1 and R2 should be chosen for approximately 1.5-µA divider current. Lower value resistors can be
used for improved noise performance, but the solution consumes more power. Higher resistor values should be
avoided as leakage current into/out of FB across R1/R2 creates an offset voltage that artificially
increases/decreases the feedback voltage and thus erroneously decreases/increases VOUT. The recommended
design procedure is to choose R2 = 1 MΩ to set the divider current at 1.5 µA, and then calculate R1 using
Equation 4:
V OUT
R1 +
*1
R2
V REF
ǒ
Ǔ
(4)
OUTPUT VOLTAGE
PROGRAMMING GUIDE
VIN
IN
VOUT
OUT
TPS71501
R1
0.1µF
GND
CFB
0.47µF
FB
R2
VOUT + VREF
OUTPUT
VOLTAGE
R1
R2
1.8 V
0.499 MΩ
1 MΩ
2.8 V
1.33 MΩ
1 MΩ
5.0 V
3.16 MΩ
1 MΩ
ǒ1 ) R1
Ǔ
R2
Figure 16. TPS71501 Adjustable LDO Regulator Programming
Power the MSP430 Microcontroller
Several versions of the TPS715xx are ideal for powering the MSP430 microcontroller. Table 2 shows potential
applications of some voltage versions.
Table 2. Typical MSP430 Applications
DEVICE
VOUT (TYP)
TPS71519
1.9 V
APPLICATION
VOUT,
MIN
> 1.800 V required by many MSP430s. Allows lowest power consumption operation.
TPS71523
2.3 V
VOUT,
MIN
> 2.200 V required by some MSP430s FLASH operation.
TPS71530
3.0 V
VOUT,
MIN
> 2.700 V required by some MSP430s FLASH operation.
TPS715345
3.45 V
VOUT,
MIN
< 3.600 V required by some MSP430s. Allows highest speed operation.
The TPS715xx family offers many output voltage versions to allow designers to minimize the supply voltage for
the processing speed required of the MSP430. This minimizes the supply current consumed by the MSP430.
8
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PACKAGE OPTION ADDENDUM
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30-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
BQ71525DCKR
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
BQ71525DCKRG4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
BQ71533DCKR
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
BQ71533DCKRG4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS71501DCKR
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS71501DCKRG4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS71518DCKR
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS71518DCKRG4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS71519DCKR
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS71519DCKRG4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS71523DCKR
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS71523DCKRG4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS71525DCKR
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS71525DCKRG4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS71530DCKR
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS71530DCKRG4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS71533DCKR
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS71533DCKRG4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS715345DCKR
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS715345DCKRG4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS71550DCKR
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS71550DCKRG4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
Lead/Ball Finish
MSL Peak Temp (3)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-May-2007
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BQ71525DCKR
DCK
5
SITE 35
180
9
2.24
1.22
2.34
4
8
Q3
BQ71533DCKR
DCK
5
SITE 35
180
9
2.24
1.22
2.34
4
8
Q3
TPS71501DCKR
DCK
5
SITE 35
180
9
2.24
1.22
2.34
4
8
Q3
TPS71518DCKR
DCK
5
SITE 35
180
9
2.24
1.22
2.34
4
8
Q3
TPS71519DCKR
DCK
5
SITE 35
180
9
2.24
1.22
2.34
4
8
Q3
TPS71523DCKR
DCK
5
SITE 35
180
9
2.24
1.22
2.34
4
8
Q3
TPS71525DCKR
DCK
5
SITE 35
180
9
2.24
1.22
2.34
4
8
Q3
TPS71530DCKR
DCK
5
SITE 35
180
9
2.24
1.22
2.34
4
8
Q3
TPS71533DCKR
DCK
5
SITE 35
180
9
2.24
1.22
2.34
4
8
Q3
TPS715345DCKR
DCK
5
SITE 35
180
9
2.24
1.22
2.34
4
8
Q3
TPS71550DCKR
DCK
5
SITE 35
180
9
2.24
1.22
2.34
4
8
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2007
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
BQ71525DCKR
DCK
5
SITE 35
180.0
180.0
85.0
BQ71533DCKR
DCK
5
SITE 35
180.0
180.0
85.0
TPS71501DCKR
DCK
5
SITE 35
180.0
180.0
85.0
TPS71518DCKR
DCK
5
SITE 35
180.0
180.0
85.0
TPS71519DCKR
DCK
5
SITE 35
180.0
180.0
85.0
TPS71523DCKR
DCK
5
SITE 35
180.0
180.0
85.0
TPS71525DCKR
DCK
5
SITE 35
180.0
180.0
85.0
TPS71530DCKR
DCK
5
SITE 35
180.0
180.0
85.0
TPS71533DCKR
DCK
5
SITE 35
180.0
180.0
85.0
TPS715345DCKR
DCK
5
SITE 35
180.0
180.0
85.0
TPS71550DCKR
DCK
5
SITE 35
180.0
180.0
85.0
Pack Materials-Page 2
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