ETC MX98725

PRELIMINARY
MX98725
SINGLE CHIP FAST ETHERNET NIC CONTROLLER
1. FEATURES
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A single chip solution integrates 100/10 Base-T fast
Ethernet MAC, PHY and PMD
Fully comply to IEEE 802.3u specification
Operates over 100 meters of STP and category 5
UTP cable
Support full and half duplex operation in both 100
Base-TX and 10 Base-T mode
Fully comply to PCI spec. 2.1 with bus clock ranges
from 16MHz to 33MHz
Fully comply to Advanced Configuration and Power
Interface (ACPI) Rev 1.0
Fully comply to PCI Bus Power Management Interface spec. Rev 1.0
Magic Packet TM mode to support Remote-Power
On and Remote-Wake-Up.
100/10 Base-T NWAY auto negotiation function
Large on chip FIFOs for both transmit and receive
operations without external local memory
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Bus master architecture with linked host buffers
delivers the most optimized performance
32-bit bus master DMA channel provides ultra low
CPU utilization
Proprietary Adaptive Network Throughput Control
(ANTC) technology to optimize data integrity and
throughput
Support up to 256K bytes boot ROM and FLASH
interface
Three levels of loopback diagnostic capability
Support a variety of flexible address filtering modes
with 16 CAM address and 512 bits hash
MicroWire interface to EEPROM for customer's IDs
and configuration data
Single +5.0V power supply, standard CMOS technology, 160 pin PQFP package
( Magic Packet technology is a trademark of Advanced
Micro Device Corp.)
2. GENERAL DESCRIPTIONS
The MX98725 contains a PCI local bus glueless interface, a Direct Memory Access (DMA) buffer management unit, an IEEE802.3u-compliant Media Access Controller (MAC), large Transmit and Receive FIFOs, and
an on-chip 10 Base-T and 100 Base-TX transceiver simplifying system design and improving high speed signal
quality. Full-duplex operation are supported in both 10
Base-T and 100 Base-TX modes that increases the
controller's operating bandwidth up to 200Mbps.
Equipped with intelligent IEEE802.3u-compliant autonegotiation, the MX98725-based adapter allows a single
RJ-45 connector to link with the other IEEE802.3u-compliant device completely without any need to set configuration.
The MX98725, second generation of 100/10 Base-T
single chip MAC controller, is designed specifically to
meet future demand on Fast Ethernet networking system. Different from MX98715/715a3, MX98725 additionally supports ACPI, Remote-Wake-Up, Remote-PowerOn, and up to 256K Bytes Flash interface to enhance
product's added-on value.
The MX9725 controller is an IEEE802.3u compliant
single chip 32-bit full duplex, 10/100Mbps highly integrated Fast Ethernet combo solution, designed to address high performance local area networking (LAN)
system application requirements.
The bus master architecture delivers the performance
needed for today high speed and powerful processors
technology. In other words, the MX98725 not only keeps
CPU utilization low while maximizing data throughput,
but it also optimizes the PCI bandwidth providing the
highest PCI bandwidth utilization. To further reduce
ownership costs the MX98725 uses drivers that are
backward-compatible with the original MXIC MX98713
series controllers.
In MX98725, an innovative and proprietary design
"Adaptive Network Throughput Control" (ANTC) is builtin to configure itself automatically by MXIC's driver based
on the PCI burst throughput of different PCs. With this
proprietary design, MX98725 can always optimize its
operating bandwidth, network data integrity and throughput for different PCs.
P/N:PM0488
REV. 1.7, SEP. 15, 1998
1
MX98725
MXIC MX98725 features Remore-Wake-Up capability
and is compliant with the Advanced Configuration and
Power Interface (ACPI). This support enables a wide
range of wake-up capabilities, including the ability to customize which network packets the PC responds to, even
when it is in a low-power state. PCs and workstations
designed to take advantage of these capabilities can be
turned on remotely and serviced simultaneiously over
the network from one central server, helping organizations reduce their total cost of ownership of high-performance business PCs. With its on-chip support for both
little and big endian byte alignment, this controller can
also address non-PC applications.
For diskless applications of networking, remotely booting up is a necessary process. To update or modify the
code is such a complex process that network venders
or owners must provide a new EPROM, replace the existing EPROM on the network adaptor and then reboot
the computer. Thanks to the development of Flash
memory, MX98725 successfully incorporated Flash interface to provide remotely boot code update service
and that means network maintenance becomes effortless.
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
FCSB
FWEB
BPA8
BPA7
BPA6
BPA5
BPA4
BPA3
BPA2
BPA1(EEDI)
BPA0(EECK)
EECS
BPA16
BPA17
BPD0(EED)
BPD1
BPD2
BPD3
BPD4
BPD5
BPD6
BPD7
GND
GND
VDD
VDD
AD0
AD1
GND
AD2
AD3
VDD
VDD
AD4
AD5
GND
GND
AD6
AD7
GND
3. PIN CONFIGURATIONS
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
MX98725
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
CBEB0
AD8
AD9
GND
GND
AD10
AD11
AD12
VDD
VDD
AD13
AD14
GND
GND
AD15
CBEB1
PAR
SERRB
PERRB
VDD
STOPB
DEVSELB
TRDYB
IRDYB
GND
GND
FRAMEB
CBEB2
AD16
AD17
GND
AD18
AD19
VDD
VDD
AD20
AD21
GND
AD22
AD23
RTX2EQ
RTX
ADVV
AGND
AGND
AVDD
AGND
AVDD
AGND
RESERVED
LANEAKE
EXSTARTB
EN_PRO
PMEB
INTAB
RSTB
PCICLK
GNTB
REQB
AD31
AD30
GND
AD29
AD28
VDD
VDD
AD27
VDD
VDD
GND
GND
AD26
AD25
GND
GND
AD24
CBEB3
IDSEL
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
FOEB
BPA9
BPA10
BPA11
BPA12
VDD
VDD
GND
GND
BPA13
BPA14
BPA15
LED0
LED1
LED2
LED3
AVDD
AGND
ARDA
AVDD
CKREF
AGND
AGND
AVDD
AGND
AGND
AVDD
AVDD
RXIN
RXIP
AVDD
AVDD
AGND
AGND
AVDD
TXON
TXOP
AGND
AGND
CPK
P/N:PM0488
REV. 1.7, SEP. 15, 1998
2
MX98725
4. PIN DESCRIPTION ( 160 PIN PQFP )
( T/S : tri-state, S/T/S : sustended tri-state, I : input, O : output, O/D : open drain )
Pin Name
AD[31:0]
Type
T/S
Pin No.
20,21,23,24,
27,32,33,36,
41,37,38,42,
44,45,48,49,
51,52,66,69,
70,73,74,75,
78,79,82,83,
86,87,90,91,
93,94
37,53
65,80
CBEB[3:0]
T/S
FRAMEB
S/T/S
54
TRDYB
S/T/S
58
IRDYB
S/T/S
57
DEVSELB
S/T/S
59
IDSEL
I
38
PCICLK
RSTB
INTAB
SERRB
I
I
O/D
O/D
17
16
15
63
PERRB
S/T/S
62
160 Pin Function and Driver
PCI address/data bus: shared PCI address/data bus lines. Little or
big endian byte ordering are supported.
PCI command and byte enable bus: shared PCI bus command and
byte enable bus, during the address phase of the transaction, these
four bits provide the bus command. During the data phase, these four
bits provide the byte enable.
PCI FRAMEB signal: shared PCI cycle start signal, asserted to
indicate the beginning of a bus transaction. As long as FRAMEB is
asserted, data transfers continue.
PCI Target ready: issued by the target agent, a data phase is
completed on the rising edge of PCICLK when both IRDYB and
TRDYB are asserted.
PCI Master ready: indicates the bus master's ability to complete
the current data phase of the transaction. A data phase is completed on
any rising edge of PCICLK when both IRDYB and TRDYB are asserted.
PCI slave device select: asserted by the target of the current bus
access. When MX98725 is the initiator of current bus access, the target
must assert DEVSELB within 5 bus cycles, otherwise cycle is aborted.
PCI initialization device select: target specific device select signal for
configuration cycles issued by host.
PCI bus clock input: PCI bus clock range from 16MHz to 33MHz.
PCI bus reset: host system hardware reset.
PCI bus interrupt request signal: wired to INTAB line.
PCI bus system error signal: If an address parity error is detected and
CFCS bit 8 is enabled, SERRB and CFCS’s bit 30 will be asserted.
PCI bus data error signal: As a bus master, when a data parity error is
detected and CFCS bit 8 is enabled, CFCS bit 24 and CSR5 bit 13 will
be asserted. As a bus target, a data parity error will cause PERRB to be
asserted.
P/N:PM0488
REV. 1.7, SEP. 15, 1998
3
MX98725
Pin Name
PAR
Type
T/S
Pin No.
64
STOPB
S/T/S
60
REQB
GNTB
T/S
I
19
18
PMEB
EXSTARTB
O/D
O/D
14
12
LANWAKE
O
11
EN_RPO
BPA1
(EEDI)
I
O
13
111
BPA0
(EECK)
O
110
BPA[17:0]
O
BPD0
(EEDO)
T/S
107,108
110-118
123-125
130-132
106
BPD[7:0]
T/S
99-106
EECS
FWEB
FOEB
FCSB
RDA
RTX
RTX2EQ
CPK
RXIP
O
O
O
O
O
O
O
I
I
109
119
121
120
139
2
1
160
150
RXIN
I
149
160 Pin Function and Driver
PCI bus parity bit: shared PCI bus even parity bit for 32 bits AD bus and
CBE bus.
PCI Target requested transfer stop signal: as bus master, assertion of
STOPB cause MX98725 either to retry, disconnect, or abort.
PCI bus request signal: to initiate a bus master cycle request
PCI bus grant acknowledge signal: host asserts to inform MX98725
that access to the bus is granted
Power Management Event: asserts low when Magic Packet is received.
Start externel circuit signal: asserts low to enable system's power
supply when Magic Packet is detected. Normally tri-stated.
LAN wake up signal: asserts high to indicate a magic packet has been
detected in Magic Packet enable mode.
Enable On-Chip Power-On-Reset : normally unconnected.
Boot PROM address bit 1(EECS=0): together with BPA[17:0] to access
external boot PROM up to 256KB.
EEPROM data in(EECS=1): EEPROM serial data input pin.
Boot PROM address bit 0(EECS=0): together with BPA[17:0] to access
external boot PROM or FLASH up to 256KB.
EEPROM clock(EECS=1): EEPROM clock input pin
Boot PROM address lines:
Boot PROM data line 0(EECS=0): boot ROM or flash data line 0.
(EEPROM data out(EECS=1): EEPROM serial data out pin(during
reset initialization.)
Boot PROM data lines: boot ROM or FLASH data lines 7-0.
EEPROM chip select.
FLASH Write Enable
FLASH ROM Output Enable
FLASH Chip Select pin
Connecting an external resistor to ground. See application note.
Connecting an external resistor to ground. See application note.
Connecting an external resistor to ground. See application note.
Connecting an external capacitor. See application note.
Twisted pair receive differential input: Support both 10Base-T and
100 Base-TX differential receive input.
Twisted pair receive differential input: Support both 10Base-T and
100 Base-TX receive differential input
P/N:PM0488
REV. 1.7, SEP. 15, 1998
4
MX98725
Pin Name
TXOP
Type
O
Pin No.
157
TXON
O
156
CKREF
LED0
I
O
141
133
LED1
O
134
LED2
O
135
LED3
O
136
RESERVED I
VDD
I
GND
I
AVDD
I
AGND
I
160 Pin Function and Driver
Twisted pair transmit differential output: Support both 10 Base-T and
100 Base-TX transmit differential output
Twisted pair transmit differential output: Support both 10 Base-T and
100 Base-TX transmit differential output
Reference clock: 25MHz oscillator clock input
Programmable LED pin 0:
CSR9.28=1 Set the LED as Link Speed (10/100) LED.
CSR9.28=0 Set the LED as Activity LED.
Default is Activity LED after reset.
Programmable LED pin 1:
CSR9.29=1 Set the LED as Link/Activity LED.
CSR9.29=0 Set the LED as Good Link LED.
Default is RX LED after reset.
Programmable LED pin 2:
CSR9.30=1 Set the LED as Collision LED.
CSR9.30=0 Set the LED as TX LED.
Default is TX LED after reset.
Programmable LED pin 3:
CSR9.31=1 Set the LED as Full/Half Duplex LED.
CSR9.31=0 Set the LED as RX LED.
Default is RX LED after reset.
Reserved pin.
Digital Power pins.
10
25,26,28,29,
30,46,47,61,
71,72,88,89,
95,96,126,127
22,30,31,34,
Digital Ground pins.
35,39,40,43,
50,55,56,67,
68,76,77,81,
84,85,92,97,
98,128,129
3,6,8,137,
140,144,147,
148,151,152,
155
4,5,7,9,138,
142,143,145,
146,153,154,
158,159
Analog Power pins.
Analog Ground pins.
P/N:PM0488
REV. 1.7, SEP. 15, 1998
5
MX98725
5. PROGRAMMING INTERFACE
5.1 PCI CONFIGURATION REGISTERS :
5.1.1 PCI ID REGISTER ( PFID ) ( Offset 03h-00h )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Device ID (bit 31:16)
Vendor ID (bit 15:0)
This register can be loaded from external serial EEPROM or use a MXIC preset value of "0D9" and "0531" for vendor
ID and device ID respectively. Word location 3Eh and 3Dh in serial EEPROM are used to configure customer's
vendor ID and device ID respectively. If location 3Eh contains"FFFF" value then MXIC's vendor ID and device ID will
be set in this register, otherwise both 3Eh and 3Dh will be loaded into this register from serial EEPROM.
5.1.2 PCI COMMAND AND STATUS REGISTER ( PFCS ) ( Offset 07h-04h )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Detect Party Error
Signal System Error
Receive Master Abort
Receive Target Abort
Deceive Select Timing
Data Parity Report
Fast Back-to-back
New Capability
System Error Enable
Parity Error Response
Master Operation
Memory Space Access
IO Space Access
The bit content will be reset to 0 when a 1 is written to the corresponding bit location.
bit 0 : IO Space Access, set to 1 enable IO access
bit 1 : Memory Space Access, set to 1 to enable memory access
bit 2 : Master Operation, set to 1 to support bus master mode
bit 5-3 : not used
bit 6 : Parity Error Response, set to 1 to enable assertion of CSR<13> bit if parity error detected.
bit 7 : not used
bit 8 : System Error Enable, set to 1 to enable SERR# when parity error is detected on address lines and CBE[3:0].
bit 20 : New capability. Set to support PCI power management.
bit 22-bit19 : not used
bit 23 : Fast Back-to back, always set to accept fast back-to-back transactions that are not sent to the same bus
device.
P/N:PM0488
REV. 1.7, SEP. 15, 1998
6
MX98725
bit 24:Data parity Report, is set to 1 only if PERR# active and PFCS<6> is also set.
bit 26-25:Device Select Timing of DEVSELB pin.
bit 27:not used
bit 28:Receive Target Abort, is set to indicate a transaction is terminated by a target abort.
bit 29:Receive Master Abort, is set to indicate a master transaction with Master abort.
bit 30:Signal System Error, is set to indicate assertion of SERR#.
bit 31:Detected Parity Error, is set whenever a parity error detected regardless of PFCS<6>.
5.1.3 PCI REVISION REGISTER ( PFRV ) ( Offset 0Bh-08h )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
6
5
3
2
1
0
2
1
Base Class
Subclass
Revision Number
Step Number
bit 3 - 0 : Step Number, range from 0 to Fh.
bit 7 - 4 : Revision Number, fixed to 3h for MX98725
bit 15 - 8 : not used
bit 23 - 16 : Subclass, fixed to 0h.
bit 31 - 24 : Base Class, fixed to 2h.
5.1.4 PCI BASE IO ADDRESS REGISTER ( PBIO ) ( Offset 13h-10h )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
4
3
0
Configuration Base IO Address
IO/Memory Space Indicator
bit 0 : IO/Memory Space Indicator, fixed to 1 in this field will map into the IO space. This is a read only field.
bit 7 - 1 : not used, all 0 when read
bit 31 - 8 : Defines the address assignment mapping of MX98725 CSR registers.
P/N:PM0488
REV. 1.7, SEP. 15, 1998
7
MX98725
5.1.5 PCI BASE MEMORY ADDRESS REGISTER ( PBMA ) ( Offset 17h-14h )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Configuration Base Memory Address
Memory Spec Indicator
bit 0 : Memory Space Indicator, fixed to 0 in this field will map into the memory space. This is a read only field.
bit 6 - 1 : not used, all 0 when read
bit 31 - 7 : Defines the address assignment mapping of MX98725 CSR registers.
5.1.6 PCI SUBSYSTEM ID REGISTER ( PSID ) ( Offset 2Ch-2Fh )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Subsystem ID (31:16)
Subsystem Vendor ID (bit 15:0)
This register is used to uniquely identify the add-on board or subsystem where the NIC controller resides. Values in
this register are loaded directly from external serial EEPROM after system reset automatically. Word location 36h of
EEPROM is subsystem vendor ID and location 35h is sub-system ID.
5.1.7 PCI BASE EXPANSION ROM ADDRESS REGISTER ( PBER ) ( Offset 33h-30h )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
0
Expansion ROM Base Address (upper 21 bit)
Address Decode Enable
bit 0 : Address Decode Enable, decoding will be enabled if only both enable bit in PFCS<1> and this expansion ROM
register are 1.
bit 10 - 1 : not use
bit 31 - 11 : Defines the upper 21 bits of expansion ROM base address.
P/N:PM0488
REV. 1.7, SEP. 15, 1998
8
MX98725
5.1.8 PCI CAPABILITY POINTER REGISTER ( PFCP ) ( Offset 37h-34h )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Capability Pointer (Set to 44h)
bit 7- 0 : Capability pointer (Cap_Ptr) is set to 44h if PMEB is connected to PCI bus, otherwise 00.
bit 31- 8 : reserved
5.1.9 INTERRUPT REGISTER ( PFIT ) ( Offset 3Fh-3Ch )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0
0
1
1
1
0
0
0
0
0
0
0
1
0
0
9
8
7
6
5
4
3
2
1
0
0
Max_Lat
Min-Gnt
Interrupt Pin
Interrupt Line
bit 7 - 0 : Interrupt Line, system BIOS will writes the routing information into this field, driver can use this information
to determine priority and interrupt vector.
bit 15 - 8 : Interrupt Pin, fixed to 01h which use INTA#.
bit 31 - 24 : Max_Lat which is a maximum period for a access to PCI bus.
bit 23 - 16 : Min_Gnt which is the maximum period that MX98725 needs to finish a brust PCI cycle.
5.1.10 PCI DRIVER AREA REGISTER ( PFDA ) ( 43h-40h )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Sleep Mode
Board Type
Driver Special Use
bit 31 : Sleep Mode, set to sleep mode which allows access to PCI configuration space, a hardwarreset or reset to
this bit can exit from sleep mode. Magic packet can be received under sleep mode if CSR16<21> ( Magic
Packet Enable ) is set.
bit 30 : not used
bit 29 : board type
bit 15 - 8 : driver is free to read and write this field for any purpose.
bit 7 - 0 : not used.
P/N:PM0488
REV. 1.7, SEP. 15, 1998
9
MX98725
5.1.11 PCI POWER MANAGEMENT CAPABILITY REGISTER ( PPMC ) ( 47h-44h )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0
0
0
0
0
0
9
0
8
7
6
5
4
3
2
1
0
0
PME_Support
D2_Support
D1_Support
AUX_I
DSI
Auxiliary Power Source
PME Clock
Version
Next Pointer
Capability ID
bit 31- 27 : PME_Support, read only indicates the power states in which the function may assert PMEB pin.
bit 31 ---- PME_D3cold (value=1)
bit 30 ---- PME_D3warm
bit 29 ---- PME_D2
bit 28 ---- PME_D1
bit 27 ---- PME_D0
bit 26 : D2 mode support, read only.
bit 25 : D1 mode support, read only.
bit 24-22 : AUX_I bits, Auxiliary Power Reporting, read only.
bit 21 : DSI, read only.
bit 20 : Auxiliary power source, read only.
bit 19 : PME Clock, read only.
bit 18-16 : Version, read only.
bit 15-8 : Next Pointer, read only.
bit 7-0 : Capability ID, read only, a 1 indicates that the data structure currently being pointed to is the PCI power
managment data structure.
5.1.13 PCI POWER MANAGEMENT COMMAND AND STATUS REGISTER ( PPMCSR ) ( 4Bh-48h )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
1
0
Data
Bridge Extension Support
PME_Status
Data_Scale
Data_Select
PME_EN
Reserved
Power State
P/N:PM0488
REV. 1.7, SEP. 15, 1998
10
MX98725
bit 1-0 : Power_State, read/write.
bit7-2 : all 0. Reserved.
bit8 : PME_EN, set 1 to enable PMEB. Set 0 to disable PMEB assertion.
bit 12-9 : Data_Select for report in the Data register located at bit 31:24.
bit 14-13 : Data_Scale, read only.
bit 15 : PME_Status independent of the state of PME_EN.
When set, indicates a assertion of PMEB pin. (support D3 cold).
Write 1 to clear the PMEB signal. Write 0, no effect.
bit 21-16 : Reserved.
bit 22 : B2_B3#, B2_B3 support for D3 hot, meaningful only if BPCC_EN = 1, read only.
bit 23 : BPCC_EN, Bus Power/Clock Control Enable, read only.
bit 31-24 : Data, read only.
5.2 HOST INTERFACE REGISTERS
MX98725 CSRs are located in the host I/O or memory address space. The CSRs are double word aligned and 32
bits long. Definitions and address for all CSRs are as follows :
CSR Mapping
Register
Meaning
CSR0
CSR1
CSR2
CSR3
CSR4
CSR5
CSR6
CSR7
CSR8
CSR9
CSR10
CSR11
CSR12
CSR13
CSR14
CSR15
CSR16
Bus mode
Transmit poll demand
Receive poll demand
Receive list demand
Transmit list base address
Interrupt status
Operation mode
Interrupt enable
Missed frame counter
Serial ROM and MII management
Reserved
General Purpose timer
10 Base-T status port
SIA Reset Register
10 Base-T control port
Watchdog timer
Magic Packet Register
Offset from CSR Base
Address ( PBIO and PBMA )
00h
08h
10h
18h
20h
28h
30h
38h
40h
48h
50h
58h
60h
68h
70h
78h
80h
CSR20
NWay Status Register
A0h
P/N:PM0488
REV. 1.7, SEP. 15, 1998
11
MX98725
5.2.1 BUS MODE REGISTER ( CSR0 )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
WIE-Write and Invalidate Enable
PLE-Read Line Enable
RME-Read Multiple Enable
TAP- Transmit Automatice Polling
ZERO-Must be zero
CAL-Cache Alignment
PBL-Programmable Burst Length
BLE-Big/Little Endian
DSL-Descriptor Skip Length
BAR-Bus Arbitration
SWR-Software Read
Field
0
Name
SWR
1
BAR
6:2
DSL
7
BLE
13:8
PBL
15:14
CAL
21
RME
23
RLE
24
WIE
Description
Software Reset, when set, MX98725 resets all internal hardware with the exception of the
configuration area and port selection.
Internal bus arbitration scheme between receive and transmit processes.
The receive channel usually has higher priority over transmit channel when receive FIFO
is partially full to a threshold. This threshold can be selected by programming this bit. Set
for lower threshold, reset for normal threshold.
Descriptor Skip Length, specifies the number of longwords to skip between two
descriptors.
Big/Little Endian, set for big endian byte ordering mode, reset for little endian byte ordering
mode, this option only applies to data buffers
Programmable Burst Length, specifies the maximum number of longwords to be trans
ferred in one DMA transaction. default is 0 which means unlimited burst length, possible
values can be 1,2,4,8,16,32 and unlimited .
Cache Alignment, programmable address boundaries of data burst stop, MX98725 can
handle non-cache- aligned fragement as well as cache-aligned fragment efficiently.18:17
TAP Transmit Auto-Polling time interval, defines the time interval for MX98725 to performs
transmit poll command automatically at transmit suspended state.
PCI Memory Read Multiple command enable, indicates bus master may intend to fetch
more than one cache lines disconnecting.
PCI Memory Read Line command enable, indicating bus master intends to fetch a
complete cache line.
PCI Memory Write and Invalidate command enable, guarantees a minimum transfer of
one complete cache line.
P/N:PM0488
REV. 1.7, SEP. 15, 1998
12
MX98725
TABLE 5.2.0 TRANSMIT AUTO POLLING BITS
CSR<18:17>
00
01
10
11
Time Interval
No transmit auto-polling, a write to CSR1 is required to poll
auto-poll every 200 us
auto-poll every 800 us
auto-poll every 1.6 ms
5.2.2 TRANSMIT POLL COMMAND ( CSR1 )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2 1
0
Transmit Poll command
Field
31:0
Name
TPC
Description
Write only, when written with any value, MX98725 read transmit descriptor list in host
memory pointed by CSR4 and processes the list.
5.2.3 RECEIVE POLL COMMAND ( CSR2 )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Receive Poll command
Field
31:0
Name
RPC
Description
Write only, when written with any value, MX98725 read receive descriptor list in host
memory pointed by CSR4 and processes the list.
5.2.4 DESCRIPTOR LIST ADDRESS ( CSR3, CSR4 )
CSR3 Receive List Base Address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
Start of Receive List Address
CSR4 Transmit List Base Address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Start of Transmit List Address
P/N:PM0488
REV. 1.7, SEP. 15, 1998
13
MX98725
5.2.5 STATUS REGISTER ( CSR5 )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MPI-Magic Packet Interrupt
LC-Link Change
EB-Error Bits
TS-Transmit Process State
RS-Receive Process State
NIS-Normal Interrupt Summary
AIS-Abnormal Interrupt Summary
ERI-Early Receive Interrupt
FBE-Fatal Bus Error
LF-Link Fail
GTE-General Purpose Timer Expired
ETI-Early Transmit Interrupt
RWT-Receive Watchdog Timeout
RPS-Receive Process Stopped
RU-Receive Buffer Unavailable
RI-Receive Interrupt
LPACI-Link Pass/Autonegotiation
Completed Interrupt
UNF-Transmit Underflow
TJT-Transmit Jabber Timeout
TU-Transmit Buffer Unavailable
TPS-Transmit Process Stopped
TI-Transmit Interrupt
Field
28
27
Name
MPI
LC
25:23
22:20
19:17
16
EB
TS
RS
NIS
15
AIS
14
ERI
13
12
FBE
LF
11
GTE
Description
Magic packet received interrupt. Valid only if CSR16<22> bit is set.
100 Base-TX link status has changed either from pass to fail or fail to pass.
Read CSR12<1> for 100 Base-TX link status.
Error Bits, read only, indicating the type of error that casued fatal bus error.
Transmit Process State, read only bits indicating the state of transmit
process.
Receive Process State, read only bits indicating the state of receive process.
Normal Interrupt Summary, is the logical OR of CSR5<0>, CSR5<2> and CSR5<6> and
CSR5<28>.
Abnormal Interrupt Summary, is the logical OR of CSR5<1>, CSR5<3>, CSR5<5>,
CSR5<7>, CSR5<8>, CSR5<9>, CAR5,10>, CSR5<11> and CSR5<13>, CSR5<27>.
Early receive interrupt, indicating the first buffer has been filled in ring mode, or 64 bytes
has been received in chain mode.
Fatal Bus Error, indicating a system error occured, MX98725 will disable all bus access.
Link Fail, indicates a link fail state in 10 Base-T port. This bit is valid only when CSR6<18>=0,
CSR14<8>=1, and CSR13<3>=0.
General Purpose Timer Expired, indicating CSR11 counter has expired.
P/N:PM0488
REV. 1.7, SEP. 15, 1998
14
MX98725
Field
10
Name
ETI
9
RWT
8
RPS
7
RU
6
5
RI
UNF
4
LPANCI
3
TJT
2
TU
1
0
TPS
TI
Description
Early Transmit Interrupt, indicating the packet to be transmitted was fully transferred to
internal TX FIFO. CSR5<0> will automatically clears this bit.
Receive Watchdog Timeout, reflects the network line status where receive watchdog
timer has expired while the other node is still active on the network.
Write only, when written with any value, MX98725 reads receive descriptor list in host
memory pointed by CSR4 and processes the list.
Receive Buffer Unavailable, the receive process is suspended due to the next descriptor
in the receive list is owned by host. If no receive poll command is issued, the reception
process resumes when the next recognized incoming frame is received.
Receive Interrupt, indicating the completion of a frame reception.
Transmit Underflow, indicating transmit FIFO has run empty before the completion of a
packet transmission.
When autonegotiation is not enabled ( CSR14<7>=0 ), this bit indicates that the 10BaseT link integrity test has completed successfully, after the link was down. This bit is also set
as as a result of writing 0 to CSR14<12> ( Link Test Enable ).
When Autonegotiation is enabled ( CSR14<7> =1 ) , this bit indicates that the autonegotiation
has completed ( CSR12<14:12>=5 ). CSR12 should then be read for a link status report.
This bit is only valid when CSR6<18>=0, i.e. 10 Base-T port is selected Link Fail interrupt
( CSR5<12> ) will automatically clears this bit.
Transmit Jabber Timeout, indicating the MX98725 has been excessively active. The
transmit process is aborted and placed in the stopped state. TDES0<1> is also set.
Transmit Buffer Unavailable, transmit process is suspended due to the next descriptor in
the transmit list is owned by host.
Transmit Process Stopped.
Transmit Interrupt. indicating a frame transmission was completed.
P/N:PM0488
REV. 1.7, SEP. 15, 1998
15
MX98725
TABLE 5.2.1 FATAL BUS ERROR BITS
CSR5<25:23>
000
001
010
011
1XX
Process State
parity error for either SERR# or PERR#, cleared by software reset.
master abort
target abort
reserved
reserved
TABLE 5.2.2 TRANASMIT PROCESS STATE
CSR5<22:20>
000
001
010
011
100
101
110
111
Process State
Stopped- reset or transmit jabber expired.
Fetching transmit descriptor
Waiting for end of transmission
filling transmit FIFO
Reserved
Setup packet
Suspended, either FIFO underflow or unavailable transmit descriptor
Closing transmit descriptor
TABLE 5.2.3 RECEIVE PROCESS STATE
CSR5<19:17>
000
010
011
100
101
110
111
Process State
Stopped- reset or stop receive command Fetching receive descriptor
Checking for end of receive packet
Waiting for receive packet
Suspended, receive buffer unavailable
Closing receive descriptor
Purging the current frame from the receive FIFO due to unavailable receive buffer
Queuing the receive frame from the receive FIFO into host receive buffer
P/N:PM0488
REV. 1.7, SEP. 15, 1998
16
MX98725
5.2.6 OPERATION MODE REGISTER ( CSR6 )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SCR-Scrambler Mode
PCS-PCS function
TTM-Transmit Threshold Mode
SF-Store and Forward
HBD-Hearbeat Disable
PS-Port Select
COE-Collision Offset Enable
TR-Threshold Control Bits
ST-Start/Stop Transmission Command
FC-Force collision mode
LOM-Loopback Operation Mode
FD-Full Duplex Mode
PM-Pass All Multicast
PR-Promiscuous Mode
SB-Start/Stop Backoff Counter
IF-Inverse Filtering
PB-Pass Bad Frame
HO-Hash-Only Filtering Mode
SR-Start/Stop Receive
HP-Hash/Perfect Receive Filtering Mode
Field
24
23
Name
SCR
PCS
22
21
TTM
SF
19
18
HBD
PS
17
COE
15:14
TR
13
ST
Description
Scrambler Mode, default is set to enable scrambler function. Not affected by software reset.
Default is set to enable PCS functions. CSR6<18> must be set in order to operate in
symbol mode.
Transmit Threshold Mode, set for 10 Base-T and reset for 100 Base-TX.
Store and Forward, when set, transmission starts only if a full packet is in transmit FIFO.
the threshold values defined in CSR6<15:14> are ignored
Heartbeat Disable, set to disable SQE function in 10 Base-T mode.
Port Select, deafult is o which is 10 Base-T mode, set for 100 Base-TX mode.
A software reset does not affect this bit.
Collision Offset Enable, set to enable a modified backoff algorithm during low collision
situation, reset for normal backoff algorithm.
Threshold Control Bits, these bits controls the selected threshold level for MX98725's transmit
FIFO, transmission starts when frame size within the transmit FIFO is larger than the
selected threshold. Full frames with a length less than the threshold are also transmitted.
Start/Stop Transmission Command, set to place transmission process in running state and
will try to transmit current descriptor in transmit list. When reset, transmit process is placed
in stop state.
P/N:PM0488
REV. 1.7, SEP. 15, 1998
17
MX98725
Field
12
Name
FC
11:10
9
LOM
FD
7
PM
6
PR
5
SB
4
IF
3
PB
2
HO
1
SR
0
HP
Description
Force Collision Mode, used in collision logic test in internal loopback mode, set to force
collision during next transmission attempt. This can result in excessive collision reported in
TDES0<8> if 16 or more collision.
Loopback Operation Mode, see table.
Full-Duplex Mode, set for simultaneous transmit and receive operation, heartbeat check is
disabled, TDES0<7> should be ignored, and internal loopback is not allowed.
This bit controls the value of bit 6 of link code word .
Pass All Multicast, set to accept all incoming frames with a multicast des tination address
are received. Incoming frames with physical address are filtered according to the CSR6<0>
bit.
Promiscuous Mode, any incoming valid frames are accepted, default is reset and not
affected by software reset.
Start/Stop Backoff Counter, when reset, the backoff timer is not affected by the network
carrier activity. Otherwise, timer will start counting when carrier drops.
Inverse Filtering, read only bit, set to operate in inverse filtering mode, only valid during
perfect filtering mode.
Pass Bad Frames, set to pass bad frame mode, all incoming frames passed the address
filtering are accepted including runt frames, collided fragments, truncated frames caused
by FIFO overflow.
Hash-Only Filtering Mode , read only bit, set to operate in imperfect filtering mode for both
physical and multicast addresses.
Start/Stop Receive, set to place receive process in running state where descriptor
acquisition is attempted from current position in the receive list. Reset to place the receive
process in stop state.
Hash/Perfect Receive Filtering Mode, read only bit, set to use hash table to filter multicast
incoming frames. If CSR6<2> is also set, then the physical adresses are imperfect address
filtered too. If CSR6<2> is reset, then physical addresses are perfect address filtered,
according to a single physical address as specified in setup frame.
P/N:PM0488
REV. 1.7, SEP. 15, 1998
18
MX98725
TABLE 5.2.4 TRANSMIT THRESHOLD
CSR6<21>
CSR6<15:14>
0
0
0
0
1
00
01
10
11
XX
CSR6<22>=0
(for 100 Base-TX)
128
256
512
1024
( Store and Forward )
CSR6<22>=1 (Threshold bytes)
(for 10 Base-T)
72
96
128
160
TABLE 5.2.5 DATA PORT SELECTION
CSR14<7>
1
0
0
CSR6<18>
0
0
1
CSR6<22>
X
1
0
CSR6<23>
X
X
1
CSR6<24>
X
X
1
Port
Nway Auto-negociation
10 Base-T
100 Base-TX
TABLE 5.2.6 LOOPBACK OPERATION MODE
CSR6<11:10>
00
01
11
10
Operation Mode
Normal
Internal loopback at FIFO port
Internal loopback at the PHY level
External loopback at the PMD level
TABLE 5.2.7 FILTERING MODE
CSR6<7>
0
0
0
CSR6<6>
0
0
0
CSR6<4>
0
0
0
CSR6<2>
0
0
1
CSR6<0>
0
1
1
0
X
1
0
1
0
1
0
0
0
X
X
0
X
X
P/N:PM0488
Filtering Mode
16 perfect filtering
512-bit hash + 1 perfect filtering
512-bit hash for multicast and phyical
addresses
Inverse filtering
Promiscuous
Pass All Multicast
REV. 1.7, SEP. 15, 1998
19
MX98725
5.2.7 INTERRUPT MASK REGISTER ( CSR7 )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MPIE-Magic Packet Interrupt Enable
LCE-Link Changed Enable
NIE-Normal interrupt Summary Enable
AIE-Abnormal Interrupt Summary Enable
ERIE-Early Receive Interrupt Enable
FBE-Fatal Bus Error Enable
LFE-Link Fail Enable
GPTE-General-Purpose Timer Enable
ETIE-Early Transmit Interrupt Enable
RWE-Receive Watchdog Enable
RSE-Receive Stopped Enable
RUE-Receive Buffer Unavailable Enable
RIE-Receive Interrupt Enable
UNE-Underflow Interrupt Enable
LPANCIE-Link Pass
/Nway Complete Interrupt Enable
TJE-Transmit Jabber Timeout Enable
TUE-Transmit Buffer Unavailable Enable
TSE-Transmit Stopped Enable
TIE-Transmit Interrupt Enable
Field
28
27
16
15
Name
MPIE
LCE
NIE
AIE
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ERIE
FBE
LFE
GPTE
ETIE
RWE
RSE
RUE
RIE
UNE
LPANCIE
TJE
TUE
TSE
TIE
Description
Magic Packet Interrupt Enable, enables CSR5<28>.
Link Changed Enable, enables CSR5<27>.
Normal Interrupt Summary Enable, set to enable CSR5<0>, CSR5<2>, CSR5<6>.
Abnormal Interrupt Summary enable, set to enbale CSR5<1>, CSR5<3>, CSR5<5>,
CSR5<7>, CSR5<8>, CSR5<9>, CSR5<11> and CSR5<13>.
Early Receive Interrupt Enable
Fatal Bus Error Enable, set together with with CSR7<15> enables CSR5<13>.
Link Fail Interrupt Enable, enables CSR5<12>
General_-Purpose Timer Enable, set together with CSr7<15> enables CSR5<11>.
Early Transmit Interrupt Enable, enables CSR5<10>
Receive Watchdog Timeout Enable, set together with CSR7<15> enables CSR5<9>.
Receive Stopped Enable, set together with CSR7<15> enables CSR5<8>.
Receive Buffer Unavailable Enable, set together with CSR7<15> enables CSR5<7>.
Receive Interrupt Enable, set together with CSR7<16> enables CSR5<6>.
Underflow Interrupt Enable, set together with CSR7<15> enables CSR5<5>.
Link Pass/Autonegotiation Completed Interrupt Enable
Transmit Jabber Timeout Enable, set together with CSR7<15> enables CSR5<3>.
Transmit Buffer Unavailable Enable, set together with CSR7<16> enables CSR5<2>.
Transmit Stop Enable, set together with CSR7<15> enables CSR5<1>.
Transmit Interrupt Enable, set together with CSR7<16> enables CSr5<0>.
P/N:PM0488
REV. 1.7, SEP. 15, 1998
20
MX98725
5.2.8 MISSED FRAME COUNTER ( CSR8 )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Missed Frame Overflow
Missed Frame Counter
Field
16
Name
MFO
15:0
MFC
Description
Missed Frame Overflow, set when missed frame counter overflows, reset when CSR8 is
read.
Missed Frame Counter, indicates the number of frames discarded because no host
receive descriptors were available.
5.2.9 NON-VOLATILE MEMORY CONTROL REGISTER ( CSR9 )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
LED3SEL
LED2SEL
LED1SEL
LED0SEL
RD-Read Operation
WR-Write Operation
BR-Boot ROM Select
SR-Serial ROM Select
Data-Boot ROM data
or Serial ROM control
Field
31
Name
LED3SEL
30
LED2SEL
29
LED1SEL
28
LED0SEL
14
RD
Description
0:Default value. Set LED3 as RX LED.
1: Set LED3 as Full/Half duplex LED.
0:Default value. Set LED2 as Link Speed (10/100) LED.
1: Set LED2 as Collision LED.
0:Default value. Set LED1 as Good Link LED.
1: Set LED1 as Link/Activity LED.
0:Default value. Set LED0 as Activity LED.
1: Set LED0 as Link Speed (10/100) LED.
Boot ROM/EEPROM read operation select bit.
P/N:PM0488
REV. 1.7, SEP. 15, 1998
21
MX98725
Field
13
12
11
7:0
Name
WR
Description
Boot ROM/EEPROM write operation select bit.
Operation definition:
RD
WR
Operation
1
0
Boot ROM/EEPROM Read
0
1
Boot ROM/EEPROM Write
1
1
EEPROM re-load operation (SR=1)
If RD=1 and WR=1, then a EEPROM re-load operation is enabled, the entire content of
boot ROM will be reloaded just like the auto-load function after power-up or hardware
reset.
Boot ROM Select, set to select boot ROM only if CSR9<11>=0.
Serial ROM Select, set to select serial ROM for either read or write operation.
If boot ROM is selected ( CSR9<12> is set ), this field contains the data to be read from
and written to the boot ROM. If serial ROM is selected, CSR9<3:0> are defined as
follows:
3 SDO Serial ROM data out from serial ROM into MX98715/MX98725.
2 SDI
Serial ROM data input to serial ROM from MX98715/MX98725.
1 SCLK Serial clock output to serial ROM.
0 SCS
Chip select output to serial ROM.
BR
SR
Data
Warning : CSR9<11> and CSR9<12> should be mutually exclusive for correct operations.
5.2.10 FLASH MEMORY PROGRAMMING ADDRESS REGISTER ( CSR10 )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
bit 17:0=boot ROM address
5.2.11 GENERAL PURPOSE TIMER ( CSR11 )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CON-Continuous Mode
Timer Value
Field
16
Name
CON
15:0
Timer
Description
When set,the general purpose timer is in continuous operating mode. When reset, the
timer is in one-shot mode.
Value contains the timer value in a cycle time of 204.8us.
P/N:PM0488
REV. 1.7, SEP. 15, 1998
22
MX98725
5.2.12 10 BASE-T STATUS PORT ( CSR12 )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
LPC-Link Partner's Link Code Word
LPN-Link Partner Negotiable
ANS-Autonegotiation Arbitration State
TRF-Transmit Remote Fault
APS-Autopolarity State
LS10-Link Status of 10 Base-T
LS100-Link Status of 100 Base-TX
*Software reset has no effect on this register
Field
31:16
Name
LPC
15
LPN
14:12
ANS
11
3
TRF
APS
2
LS10
1
LS100
Decription
Link Partner’s Link Code Word, where bit 16 is S0 ( selector field bit 0 ) and bit 31 is NP (
Next Page ). Effective only when CSR12<15> is read as a logical 1. the following field.
Link Partner Negotiable, set when link partner support NWAY algorithm and CSR14<7>
is set.
Autonegotiation Arbitration State, arbitration states are defined
000 = Autonegotiation disable
001 = Transmit disable
010 = ability detect
011 = Acknowledge detect
100 = Complete acknowledge detect
101 = FLP link good; autonegotiation complete
110 = Link check
When autonegotiation is completed, an ANC interrupt ( CSR5<4>) is generated, write 001
into this field can restart the autonegotiation sequence if CSR14<7> is set. Otherwise,
these bits should be 0.
Transmit Remote Fault
Autopolarity State, set when polarity is positive. When reset, the 10Base-T polarity is
negative. The received bit stream is inverted by the receiver.
Set when link status of 10 Base-T port link test fail. Reset when 10 Base-T link test is in
pass state.
Link state of 100 Base-TX, this bit reflects the state of SD pin, effective only when
CSR6<23>= 1 ( PCS is set ). Set to indicate a fail condition .i.e. SD=0.
P/N:PM0488
REV. 1.7, SEP. 15, 1998
23
MX98725
5.2.13 SIA RESET REGISTER (CSR13)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
3
2
1
0
100 TX Reset100 Base-TX PHY level reset
Nway ResetNway and 10 Base-T PHY level reset
Field
0
1
Name
Nway Reset
100Base-TX
Decription
While writing 0 to this bit, resets the CSR12 & CSR14.
Reset Write a 1 will reset the internal 100 Base-TX PHY module .
5.2.14 10 BASE-T CONTROL PORT (CSR14)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
T4-100 Base-T4 (link code word)
TXF-100 Base-TX full duplex
(link code word)
TXH-100 Base-TX half duplex
(link code word)
LTE-Link Test Enable
RSO-Receive Squelch Enable
ANE-Autonegotiation Enable
HDE-Half Duplex Enable)
PWD10B-Power down 10 Base-T
LBK-Loopback (MCC)
Field
18
17
16
Name
T4
TXF
TXH
12
8
7
6
LTE
RSQ
ANE
HDE
2
PWD10B
1
LBK
Decription
Bit 9 of link code word for T4 mode.
Bit 8 of link code word for 100 Base-TX full duplex mode.
Bit 7 of link code word for 100 Base-TX half duplex mode. Meaningful only when CSR14<7>
( ANE ) is set.
Link Test Enable, when set the 10 Base-T port link test function is enabled.
Receive Squelch Enable for 10 Base-T port. Set to enable.
Autonegotiation Enable, .
Half-Duplex Enable, this is the bit 5 of link code word, only meaningful when CSR14<7> is
set.
Reset to power down 10 Base-T module, this will force both TX and RX port into tri-state
and prevent AC current path. Set for normal 10 Base T operation.
Loop back enable for 10 Base-T MCC.
P/N:PM0488
REV. 1.7, SEP. 15, 1998
24
MX98725
5.2.15 WATCHDOG TIMER ( CSR15)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MBZ-Must Be Zero
RWR-Receive Watchdog Release
PWD-Receive Watchdog Disable
JCK-Jabber Clock
HUJ-Host Unjabber
JAB-Jabber Disable
Field
Name
Description
5
RWR
4
RWD
2
JCK
1
HUJ
0
JBD
Defines the time interval no carrier from receive watchdog expiration until reenabling the
receive channel. When set, the receive watchdog is release 40-48 bit times from the last
carrier deassertion. When reset, the receive watchdog is released 16 to 24 bit times from
the last carrier deassertion.
When set, the receive watchdog counter is disable. When reset, receive carriers longer
than 2560 bytes are guaranted to cause the watchdog counter to time out. Packets horter
than 2048 bytes are guaranted to pass.
When set, transmission is cut off after a range of 2048 bytes to 2560 bytes is transmitted,
When reset, transmission for the 10 Base-T port is cut off after a range of 26 ms to 33ms.
When reset, transmission for the 100 Base-TX port is cut off after a range of 2.6ms to
3.3ms.1
Defines the time interval between transmit jabber expiration until reenabling of the
transmit channel. When set, the transmit channel is released immediately after the jabber
expiration.
When reset, the jabber is released 365ms to 420 ms after jabber expiration for 10 Base-T
port. When reset, the jabber is released 36.5ms to 42ms after the jabber exporation for
100 Base-TX port.
Jabber Disable, set to disable transmit jabber function.
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MX98725
5.2.16 MAGIC PACKET REGISTER ( CSR16 )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
MPE (Magic Packet Enable)
Field
bit 31:23
bit 22
bit 21:0
Name
reserved
MPE
reserved
Description
Magic Packet Enable, set to enable Magic Packet Mode
Sleep mode and MPE mode can be used seperately. When Sleep and MPE are both set, the Sleep mode dominate
MPE, i.e., no magic packet can be detected since both TX and RX channel are shut off in sleep mode. On the
detection of magic packet, a negative pulse will be asserted on PME# pin on PCI bus, LANWAKE pin will be
asserted high and EXSTART# pin is driven low and stay low even after PCI reset is asserted. EXSTART# pin can
be reset by device driver.
5.2.17 NWAY STATUS REGISTER ( CSR20 )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
100T4
100TXF
100TXH
10TXF
10TXH
Reserved
Reserved
Field
31
30
29
28
27
16
12
Name
T4
100TXF
100TXH
10TXF
10TXH
Reserved
Reserved
Description
T4 mode is accepted, read only
100Base-TX full duplex is accepted, read only
100Base-TX half duplex is accepted, read only
10Base-T duplex is accepted, read only
10Base-T half duplex is accepted, read only
Reserved for test purpose, must be set 1 for normal operation.
Reserved for test purpose, must be set 1 for normal operation.
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REV. 1.7, SEP. 15, 1998
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MX98725
5.3 Power Management Functions :
5.3.2 Remote Wake-Up Mode :
MX98715A complies to ACPI Version 1.0, supports
D3cold state to generate PMEB. There are basically 3
power saving modes supported, namely Remote PowerOn, Remote Wake-Up, and Sleep mode. By default,
MX98715A will enable ACPI function with the following
registers setup :
When the PC is still turned on regardless of the status
of CPU and system's status, a Magic packet can be
detected if enabled. As soon as a Magic packet addressed to the network adaptor is detected, both INTA#
and PMEB can be asserted low if registers set up as
follows :
PFCS<20> ( New Capability )= 1
PFCP<7:0> ( Capability Pointer ) = 44h
PPMC<7:0> ( Capability ID ) = 1h
CSR16<22> ( PME ) = 1 and
PPMCSR<8> ( PME_EN ) =1
to enable PMEB assertion.
Please refer to PCI configuration registers for more details.
CSR16<22> ( PME ) = 1 and
CSR7<28> ( MPIE ) = 1 to enable INTA#
assertion
5.3.1 Remote Power-On Mode :
5.3.3 Sleep Mode :
When AC power cord of PC is plugged into the wall
outlet, MX98715A will load the network ID from
EEPROM and enter itself into Remote Power-On mode
automatically. The host and PCI bus has no power at
this stage. As soon as a Magic packet addressed to this
network adaptor, PMEB will be asserted low to power
on the PC.
Set PFDA<31> ( Sleep ) = 1 will enter the chip into a
sleep mode where no TX nor RX activities can be processed. Only PCI configuration can be accessed.
To set up the Remote Power-On ( RPO ) mode, as long
as a 5.0V standby VDD is connected into the adaptor's
isolated VDD and MX98715A will set up itself to detect
Magic packet. No registers needed to be programmed.
Simply turn off the power switch or plug in the AC power
cord of the PC that support RPO and everything else is
set automatically.
P/N:PM0488
REV. 1.7, SEP. 15, 1998
27
MX98725
6. AC/DC CHARACTERISTICS
6.1 BOOT ROM TIMING (READ)
BPA 15-0
TRC
BCEB
BOEB
TOES
(CE&OE is typical shorted)
TCE
TOOLZ
TOH
TOH
BPD 7:0
TCOLZ
TACC
6.2 AC CHARACTERISTICS
SYMBOL
TRC
TCE
TACC
TOES
TOH
DESCRIPTION
Read Cycle
Chip Enable Access Time
Address Access Time
Output Enable Access Time
Output Hold from Address, CEB, or OEB
MINIMUM
8
0
TYPICAL
-
MAXIMUM
7
7
7
-
UNITS
PCI Cycle
PCI Cycle
PCI Cycle
PCI Cycl
ns
PCI cycle range:66ns (16MHz)~25ns (40MHz)
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REV. 1.7, SEP. 15, 1998
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MX98725
6.3 COMMAND WRITE TIMING WAVEFORMS
FCSB
FOEB
FWEB
tWP
tAS
BPA17-0
tAH
VALID
tDS
BPD 7:0
SYMBOL
tWP
tAS
tAH
tDS
tDH
tDH
HIGHZ
DESCRIPTION
Write Pulse Width
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
DIN
MINIMUM
8
0
7
7
1
TYPICAL
-
MAXIMUM
UNITS
PCI Cycle
ns
PCI Cycle
PCI Cycl
PCI Cycle
PCI cycle range:66ns (16MHz)~25ns (40MHz)
6.4 ABSOLUTE OPERATION CONDITION
Supply Voltage (VCC)
DC Input Voltage (Vin)
DC Output Voltage (Vout)
Storage Temperature Range (Tstg)
Operating Temperature Range
Power Dissipation (PD)
Lead Temp. (TL) (Soldering, 10 sec)
ESD Rating (Rzap=1.5K, Czap=100pF)
Clamp Diode Current
-0.5V to +7.0V
4.75V to 5.25V
-0.5V to VCC +0.5V
-55°C to +150°C
0°C to 70°C
750mW (Typ)
260°C
1.0KV
±20mA
P/N:PM0488
REV. 1.7, SEP. 15, 1998
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MX98725
6.5 DC CHARACTERISTICS
Symbol
Parameter
Conditions
Min
2.4
Max
Units
TTL/PCI Input/Output
Voh
Minimum High Level Output Voltage
Ioh = -3mA
Vol
Maximum Low Level Output Voltage
Iol = +6mA
Vih
Minimum High Level Input Voltage
Vil
Maximum Low Level Input Voltage
Iin
Input Current
Vi = VCC or GND
Ioz
Minimum TRI-STATE Output Leakage Current
Vout = VCC or GND
V
0.4
2.0
V
V
0.8
V
- 1.0
+ 1.0
uA
-10
+10
uA
0.4
V
130
170
mA
4.75V
5.25V
V
LED output Driver
Vlol
LED turn on Output Voltage
Iol = 16mA
Average Supply Current
CKREF =25MHz
Supply
Idd
PCICLK = 33MHz
Vdd
Average Supply Voltage
P/N:PM0488
REV. 1.7, SEP. 15, 1998
30
MX98725
REVISION HISTORY
Revision
1.7
Destription
(1) revise PFRV register bit 31-24 to be 2h
(2) exchange description for PFIT register bit 7-0 and bit 15-8
(3) revise LED2SEL default setting to be Link Speed (10/100)
(4) revise ESD rating in Section 6.4 from 1.5KV to 1.0KV
(5) add Power Dissipation in Section 6.4 to be 750mW (typ)
(6) add Idd value in Section 6.5 to be 130 mA to 170mA
P/N:PM0488
Page
7
9
21
29
29
30
Date
Sep/15/1998
REV. 1.7, SEP. 15, 1998
31
MX98725
7.0 PACKAGE INFORMATION
160-Pin Plastic Quad Flat Pack
A
B
ITEM
MILLIMETERS
INCHES
A
31.20 ±.30
1.228 ±.12
B
28.00 ±.10
1.102 ± .004
C
28.00 ±.10
1.102 ±.004
D
31.20 ±.30
1.228 ±.012
E
25.35
.999
F
1.33 [REF.]
.052 [REF.]
G
1.33 [REF.]
.052 [REF.]
H
.30 [Typ.]
.012 [Typ.]
I
.65 [Typ.]
.026 [Typ.]
J
1.60 [REF.]
.063 [REF.]
K
.80 ±.20
.031 ±.008
L
.15 [Typ.]
.006 [Typ.]
M
.10 max.
.004 max.
N
3.35 max.
.132 max.
O
.10 min.
.004 min.
P
3.68 max.
.145 max.
NOTE:
120
121
81
80
E
F
Each lead centerline is located within .25
mm[.01 inch] of its true position [TP] at
maximum material condition.
160
1
C
D
41
40
G
H
I
J
N
P
L
M
P/N:PM0488
K
O
REV. 1.7, SEP. 15, 1998
32
MX98725
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-8888
FAX:+886-3-578-8887
EUROPE OFFICE:
TEL:+32-2-456-8020
FAX:+32-2-456-8021
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FAX:+65-748-4090
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CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
33