Integrated Circuit Systems
Preliminary Data Sheet
ICS1526
Video Clock Synthesizer
General Description
Features
The ICS1526 is a low-cost, high-performance
frequency generator. It is suited to general purpose
phase controlled clock synthesis as well as
line-locked and genlocked high-resolution video
applications. Using ICS’s advanced low-voltage
CMOS mixed-mode technology, the ICS1526 is an
effective clock synthesizer that supports video
projectors and displays at resolutions from VGA to
beyond XGA.
The ICS1526 offers single-ended clock outputs to 200
MHz. The HSYNC_out, and VSYNC_out pins provide
the regenerated versions of the HSYNC and VSYNC
inputs synchronous to the CLK output.
The advanced PLL uses its internal programmable
feedback divider. The device is programmed by a
standard I2C-bus™ serial interface and is available in
a TSSOP16 package.
ICS1526 Functional Diagram
• Lead-free packaging (Pb-free)
• Low jitter (typical 27 ps short term jitter)
• Wide input frequency range
• 8 kHz to 100 MHz
• LVCMOS single-ended clock outputs
• Up to 200 MHz
• Uses 3.3 V power supply
• 5 Volt tolerant Inputs (HSYNC, VSYNC)
• Coast (ignore HSYNC) capability via VSYNC pin
• Industry standard I2C-bus programming interface
• PLL Lock detection via I2C or LOCK output pin
• 16-pin TSSOP package
Applications
• Frequency synthesis
• LCD monitors, video projectors and plasma displays
• Genlocking multiple video subsystems
Pin Configuration (16-pin TSSOP)
HSYNC_out
OSC
HSYNC
VSYNC
I2C
MDS 1526 I
ICS1526
VSYNC_out
CLK
LOCK
VSSD
SDA
SCL
VSYNC
HSYNC
VDDA
VSSA
OSC
ICS reserves the right to make changes in the preliminary device data
identified in this publication without notice. ICS advises its customers
to obtain the latest version of all device data to verify that information
being relied upon is current and accurate.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDD
VSSQ
VSYNC_out
VDDQ
CLK
HSYNC_out
LOCK
I2CADR
Revision 020304
ICS1526 Preliminary Data Sheet
Section 1
Section 1 Overview
Overview
The ICS1526 has the ability to operate in line-locked
mode with the HSYNC input.
1.1 Phase-Locked Loop
The ICS1526 is a user-programmable,
high-performance general purpose clock generator. It
is intended for graphics system line-locked and
genlocked applications and provides the clock signals
required by high-performance analog-to-digital
converters.
Figure 1-1
OSC
HSYNC
The phase-locked loop has a very wide input frequency
range (8 kHz to 100 MHz). Not only is the ICS1526 an
excellent, general purpose clock synthesizer, but it is
also capable of line-locked operation. Refer to the
block diagram below.
Simplified Block Diagram
Divider
3..129
CP
PFD
VCO
VCOD
CLK
2,4,8,16
FD
12..4103
Flip-flop
VSYNC
Flip-flop
HSYNC_out
VSYNC_out
Note: Polarity controls and other circuit elements are not shown in above diagram for simplicity
The heart of the ICS1526 is a voltage controlled
oscillator (VCO). The VCOs speed is controlled by the
voltage on the loop filter. This voltage will be described
later in this section.
The VCOs clock output is first passed through the VCO
Divider (VCOD). The VCOD allows the VCO to operate
at higher speeds than the required output clock.
The input HSYNC and VSYNC can be conditioned by a
high-performance Schmitt-trigger by sharpening the
rising/falling edge.
The HSYNC_out and VSYNC_out signals are aligned
with the output clock (CLK) via a set of flip flops.
1.2 Output Drivers and Logic Inputs
NOTE: Under normal, locked operation the VCOD has
no effect on the speed of the output clocks, just the
VCO frequency.
The ICS1526 uses low-voltage TTL (LVTTL) inputs and
LVCMOS outputs, operating at the 3.3 V supply
voltage. The LVTTL inputs are 5 V tolerant.
The output of the VCOD is the full speed output
frequency seen on the CLK. This clock is then sent
through the 12-bit internal Feedback Divider (FD). The
feedback divider controls how many clocks are seen
during every cycle of the input reference.
The LVCMOS drive resistive terminations or
transmission lines.
The Phase Frequency Detector (PFD) then compares
the feedback to the input and controls the filter voltage
by enabling and disabling the charge pump. The
charge pump has programmable current drive and will
source and sink current as appropriate to keep the
input and the clock output aligned.
MDS 1526 I
2
1.3 Automatic Power-On Reset Detection
The ICS1526 has automatic power-on reset detection
(POR) circuitry and it resets itself if the supply voltage
drops below threshold values. No external connection
to a reset signal is required.
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ICS1526 Preliminary Data Sheet
Section 1 Overview
1.4 I2C Bus Serial Interface
The ICS1526 uses a 5 volt tolerant, industry-standard
I2C-bus serial interface that runs at either low speed
(100 kHz) or high speed (400 kHz). The interface uses
12 word addresses for control and status: one
write-only, eight read/write, and three read-only
addresses.
Two ICS1526 devices can sit on the same I2C bus,
each selected by the Master according to the state of
the I2CADR pin. The 7-bit device address is 0100110
(binary) when I2CADR is low. The device address is
0100111 (binary) when I2CADR is high. See Section 4,
“Programming”
MDS1526 I
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ICS1526 Preliminary Data Sheet
Section 2
Section 2 Pin Descriptions
Pin Descriptions
Table 2-1 ICS1526 Pin Descriptions
PIN NO. PIN NAME
TYPE
DESCRIPTION
1
VSSD
POWER
Digital ground
2
SDA
IN/OUT
Serial data
COMMENTS
Notes
I2C-bus
1
2
3
SCL
IN
Serial clock
I C-bus
1
4
VSYNC
IN
Vertical sync
5
HSYNC
IN
Horizontal sync
Clock input to PLL
6
VDDA
POWER
Analog supply
Power for analog circuitry
7
VSSA
POWER
Analog ground
Ground for analog circuitry
8
OSC
IN
Oscillator
Input from crystal oscillator package
9
I2CADR
IN
I2C device address
Chip I2C address select
10
LOCK
LVCMOS
OUT
Lock
PLL Lock detect
11
HSYNC_out
LVCMOS
OUT
HSYNC output
Schmitt-trigger filtered HSYNC
realigned with the output pixel clock
12
CLK
LVCMOS
OUT
Pixel clock output
LVCMOS driver for full speed clock
13
VDDQ
POWER
Output driver supply
Power for output drivers
14
VSYNC_out
LVCMOS
OUT
VSYNC output
Schmitt-trigger filtered VSYNC
realigned with the output pixel clock
15
VSSQ
POWER
Output driver ground
Ground for output drivers
16
VDDD
POWER
Digital supply
Power for digital sections
1&2
1&2
1&2
Notes: 1. These LVTTL inputs are 5 V tolerant.
2. Connect to ground if unused.
MDS 1526 I
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ICS1526 Preliminary Data Sheet
Section 3
Word
Address
00h
01h
Section 3 Register map summary
Register map summary
Name
Access
Bit Name
Bit #
Reset
Value
Input
Control
R/W
CPen
0
1
Charge Pump Enable
0=External Enable via VSYNC, 1=Always Enabled
VSYNC_Pol
1
0
VSYNC Polarity (Charge Pump Enable)
Requires 00h:0=0
0=Coast (charge pump disabled) while VSYNC low,
1=Coast (charge pump disabled) while VSYNC high
HSYNC_Pol
2
0
HSYNC Polarity
0=Rising Edge, 1=Falling Edge
Loop
Control*
R/W
Description
Reserved
3
0
Reserved
Reserved
4
0
Part requires a 0 for correct operation
Reserved
5
0
Reserved
EnPLS
6
1
Enable PLL Lock Output
0=Disable, 1=Enable
Reserved
7
0
Reserved
ICP0-2
0-2
ICP (Charge Pump Current)
Bit 2,1,0 = {000 =1 µA, 001 = 2 µA, 010 = 4 µA... 110 = 64 µA, 111 =
128 µA}
Reserved
3
VCOD0-1
4-5
Reserved
VCO Divider
Bit 5,4 = {00 = ÷2, 01=÷4, 10=÷8, 11=÷16}
Reserved
6-7
Reserved
02h
FdBk Div
0*
R/W
FBD0-7
0-7
Feedback Divider LSBs (bits 0-7)
03h
FdBk Div
1*
R/W
FBD8-11
0-3
Feedback Divider MSBs (bits 8-11)
Divider setting = 12-bit word + 8
Minimum 12 = 000000000100
Maximum 4103 =111111111111
Reserved
4-7
Reserved
Reserved
0-7
0
Reserved
Schmitt
control
0
1
Schmitt-trigger control
0=Schmitt-trigger, 1=No Schmitt-trigger
Metal_Rev
1-7
0
Metal Mask Revision Number
04h
Reserved
05h
Schmitttrigger*
06h
MDS1526 I
Output
Enables
R/W
R/W
Reserved
0
0
Reserved
OE
1
0
Output Enable for CLK, HSYNC_out, VSYNC_out
0=High Impedance (disabled), 1=Enabled
Reserved
2-7
0
Reserved
5
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ICS1526 Preliminary Data Sheet
Word
Address
Name
07h
Osc_Div
08h
Access
R/W
Section 3 Register map summary
Bit Name
Bit #
Reset
Value
Osc_Div 0-6
0-6
0
Osc Divider modulus
Minimum 3 =0000001 binary, Maximum 129 = 1111111 binary
Divider setting = 7-bit word + 2
In-Sel
7
0
Input Select
0=HSYNC Input, 1=OSC Input
OSC input clock must be present to select OSC input
x
Writing 5Ah resets PLL and commits values written to word
addresses 01h-03h and 05h
Description
Reset
Write
PLL
0-7
09-0Fh
Reserved
Read
Reserved
0-7
Reserved
10h
Chip Ver
Read
Reserved
0-7
Reserved
11h
Chip Rev
Read
Chip Rev
0-7
12h
Rd_Reg
Read
01
Reserved
Reserved
0
N/A
Reserved
PLL_Lock
1
N/A
PLL Lock Status
0=Unlocked, 1=Locked
Reserved
2-7
0
Reserved
*. Written values to these registers do not take effect immediately, but require a commit via register 08h
MDS 1526 I
6
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ICS1526 Preliminary Data Sheet
Section 4
Section 4 Programming
Programming
4.1 Industry-Standard I2C Serial Bus: Data Format
Figure 4-1
ICS1526 Data Format for I2C 2-Wire Serial Bus
S ingle/m ultiple register w rite (page w rite)
D evice address
W ord address
S 0 1 0 0 1 1 B 0 A
T
C
A
K
R
T
D ata (0)
A
C
K
D ata (n)
A
C
K
...
A S
C T
K O
P
S ingle/m ultiple register read
D evice address
S 0 1 0 0 1 1 B 0 A
T
C
A
K
R
T
W ord address
D evice address
A S 0 1 0 0 1 1 B 1 A
C T
C
K A
K
R
T
D ata (n)
D ata (0)
A
C
K
...
N
O
A
C
K
S
T
O
P
S equ ential single/m u ltiple register read
D evice address
S 0 1 0 0 1 1 B 1 A
T
C
A
K
R
T
M aster drives line
D ata (n)
D ata (0)
A
C
K
...
N
O
A
C
K
S
T
O
P
S lave drives line
Notes:
The ICS1526 uses 16-byte pages (00h-0Fh is the first page, 10h-1Fh is the second page). Writing or reading
beyond the end of page yields undefined results.
The ICS1526 has a device address of 010011B, where B is the state of the I2CADR pin.
MDS1526 I
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ICS1526 Preliminary Data Sheet
Section 5
Section 5 AC/DC Operating Conditions
AC/DC Operating Conditions
5.1 Absolute Maximum Ratings
Table 5-1 lists absolute maximum ratings for the ICS1526. Stresses above these ratings can cause permanent
damage to the device. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the ICS1526 at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Table 5-1 ICS1526 Absolute Maximum Ratings
Item
Rating
VDD, VDDA, VDDQ (measured to VSS)*
4.3 V
Digital Inputs
VSS –0.3 V to 5.5 V
Analog Inputs
VSS -0.3 V to 6.0 V
Analog Outputs
VSSA –0.3 V to VDDA +0.3 V
Digital Outputs
VSSQ –0.3 V to VDDQ +0.3 V
Storage Temperature
–65°C to +150°C
Junction Temperature
125°C
Soldering Temperature
260°C
ESD Susceptibility*
> 2 KV**
*. Measured with respect to VSS. During normal operations, the VDD supply voltage for the ICS1526 must
remain within the recommended operating conditions.
**. Electrostatic-sensitive devices. Do not open or handle except in a static-free workstation.
Table 5-2 Environmental Conditions
Parameter
Min.
Typ.
Max.
Units
0
–
+70
°C
+3.0
+3.3
+3.6
V
Ambient Operating Temperature
Power Supply Voltage
Table 5-3 DC Characteristics
Parameter
Symbol
Conditions
Min.
Max.
Units
Digital Supply Current
IDDD
VDDD = 3.6 V
-
25
mA
Output Driver Supply Current
IDDQ
VDDD = 3.6 V
No drivers enabled
-
6
mA
Analog Supply Current
IDDA
VDDA = 3.6 V
-
5
mA
300
mW
1.8
V
Power consumption
Power-On-Reset (POR)
Threshold
MDS 1526 I
VSS
8
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ICS1526 Preliminary Data Sheet
Section 5 AC/DC Operating Conditions
Table 5-4 AC Characteristics
Parameter
Symbol
Min.
fVCO
40
Typical
Max.
Units
400
MHz
Notes
General
VCO Frequency
VCO Gain
K
165
MHz/V
AC Inputs
OSC Input Frequency
fOSC
0.02
100
MHz
Analog Input (HSYNC/VSYNC)
HSYNC Input Frequency
fHSYNC
8
10,000
kHz
VSYNC Input Frequency
fVSYNC
30
120
Hz
Input High Voltage
VIH
1.7
5.5
V
Input Low Voltage
VIL
VSS - 0.3
1.1
V
0.2
0.8
V
Input Hysteresis
Schmitt trigger active
SDA, SCL, OSC Digital Inputs
Input High Voltage
VIH
2
5.5
V
Input Low Voltage
I2CADDR Digital
VIL
VSS - 0.3
0.8
V
Input High Voltage
VIH
2
VDD+0.3
V
Input Low Voltage
VIL
VSS - 0.3
0.8
V
Input
SDA Digital Output
SDA Output Low Voltage
VOL
0.4
V
IOUT = 3 mA
SDA Output High Voltage
VOH
6.0
V
Determined by
external Rset resistor
200
MHz
VDDD = 3.3 V
55
%
2
LVCMOS Outputs (CLK, HSYNC_out, VSYNC_out, LOCK)
Output Frequency
Fs
2.5
Duty Cycle
SDC
45
Jitter, STJ, RMS
STJ
0.027
ns
Jitter, STJ, pk-pk
STJ
0.200
ns
30 kHz input to 50
MHz output
Jitter, Input-Output
IOJ
2.500
ns
HSYNC in to CLK out
50
HSYNC to HSYNC_out
propagation delay (without
Schmitt trigger)
2
9
ns
1
HSYNC to HSYNC_out
propagation delay (with
Schmitt-trigger)
6
10
ns
1
1.0
ns
1.5
ns
CLK to HSYNC_out/
VSYNC_out skew
Clock/ HSYNC_out/
VSYNC_out
Transition Time - Rise
MDS1526 I
1.0
TCR
9
2
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ICS1526 Preliminary Data Sheet
Parameter
Symbol
Section 5 AC/DC Operating Conditions
Min.
Typical
Max.
Units
Notes
1.0
1.5
ns
2
Clock/ HSYNC_out/
VSYNC_out
Transition Time - Fall
TCF
LOCK Transition Time - Rise
TLR
3.0
ns
2
LOCK Transition Time - Fall
TLF
2.0
ns
2
Note 1—Measured between chosen edge of HSYNC (00h:2) and rising edge of output
Note 2—Measured at 110 MHz, 3.3 VDC, 25oC, 15 pF, unterminated
MDS 1526 I
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ICS1526 Preliminary Data Sheet
Section 6
Section 6 Package Outline and Package Dimensions
Package Outline and Package Dimensions
16-pin TSSOP 4.40 mm body, 0.65 mm pitch
Package dimensions are kept current with JEDEC Publication No. 95
16
Millimeters
Symbol
E1
A
A1
A2
b
C
D
E
E1
e
L
α
aaa
E
INDEX
AREA
1 2
D
Min
Inches
Max
Min
-1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
4.90
5.1
6.40 BASIC
4.30
4.50
0.65 Basic
0.45
0.75
0°
8°
-0.10
Max
-0.047
0.002
0.006
0.032
0.041
0.007
0.012
0.0035 0.008
0.193
0.201
0.252 BASIC
0.169
0.177
0.0256 Basic
0.018
0.030
0°
8°
-0.004
A
A2
A1
c
-Ce
SEATING
PLANE
b
L
aaa C
Section 7
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
ICS1526GLF
1526GLF
Tubes
16-pin TSSOP
0 to +70° C
ICS1526GLFTR
1526GLF
Tape & Reel
16-pin TSSOP
0 to +70° C
“LF” denotes Pb (lead) free package.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS1526 I
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In te grated Circuit Systems, 525 Race Stre e t, Sa n Jose , CA 95 126, tel (408 ) 29 7-120 1 w w w. i c s t . c o m