Revised April 1999 74VHC164 8-Bit Serial-In, Parallel-Out Shift Register General Description The VHC164 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC164 is a high-speed 8-Bit Serial-In/Parallel-Out Shift Register. Serial data is entered through a 2input AND gate synchronous with the LOW-to-HIGH transition of the clock. The device features an asynchronous Master Reset which clears the register, setting all outputs LOW independent of the clock. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Features ■ High Speed: fMAX = 175 MHz at VCC = 5V ■ Low power dissipation: ICC = 4 µA (max) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (min) ■ Power down protection provided on all inputs ■ Low noise: VOLP = 0.8V (max) ■ Pin and function compatible with 74HC164 Ordering Code: Order Number Package Number 74VHC164M 74VHC164SJ 74VHC164MTC 74VHC164N M14A M14D MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Descriptions Pin Names A, B Description Data Inputs CP Clock Pulse Input (Active Rising Edge) MR Master Reset Input (Active LOW) Q0–Q7 Outputs © 1999 Fairchild Semiconductor Corporation DS011636.prf www.fairchildsemi.com 74VHC164 8-Bit Serial-In, Parallel-Out Shift Register August 1993 74VHC164 Functional Description Function Table The VHC164 is an edge-triggered 8-bit shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (A or B); either of these inputs can be used as an active High Enable for data entry through the other input. An unused input must be tied HIGH. Operating Each LOW-to-HIGH transition on the Clock (CP) input shifts data one place to the right and enters into Q0 the logical AND of the two data inputs (A • B) that existed before the rising clock edge. A LOW level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all Q outputs LOW. Inputs Outputs MR A B Reset (Clear) L X X L L–L Shift H L L L Q0–Q6 H L H L Q0–Q6 H H L L Q0–Q6 H H H H Q0–Q6 Mode Q0 H = HIGH Voltage Levels L = LOW Voltage Levels X = Immaterial Q = Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com Q1–Q7 2 Supply Voltage (VCC) −0.5V to +7.0V DC Input Voltage (VIN) −0.5V to + 7.0V Recommended Operating Conditions (Note 2) −0.5V to VCC + 0.5V DC Output Voltage (VOUT) Supply Voltage (VCC) 2.0V to 5.5V Input Voltage (VIN) 0V to +5.5V DC Diode Current (IIK) −20 mA Output Voltage (VOUT) Output Diode Current (IOK) ±20 mA Operating Temperature (TOPR) DC Output Current (IOUT) ±25 mA Input Rise and Fall Time (tr, tf) DC VCC /GND Current (ICC ) ±75 mA VCC = 3.3V ± 0.3V 0 ns/V ∼ 100 ns/V −65°C to +150°C VCC = 5.0V ± 0.5V 0 ns/V ∼ 20 ns/V Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 0V to VCC −40°C to +85°C Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specifications. 260°C Note 2: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH Parameter HIGH Level Input Voltage VIL LOW Level Input Voltage VOH VOL IIN VCC (V) TA = 25°C Min TA = −40°C to +85°C Typ Max Min 2.0 1.50 1.50 3.0− 5.5 0.7 VCC 0.7 VCC 2.0 0.50 0.50 0.3 VCC 0.3 VCC HIGH Level Output 2.0 1.9 2.0 1.9 3.0 2.9 3.0 2.9 4.5 4.4 4.5 3.0 2.58 2.48 4.5 3.94 3.80 VIN = VIH IOH = −4 mA V LOW Level Output 2.0 0.0 0.1 0.1 3.0 0.0 0.1 0.1 4.5 0.0 Quiescent Supply IOH = −50 µA or VIL 4.4 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 0 − 5.5 ±0.1 ±1.0 5.5 4.0 40.0 Current ICC V V Voltage Input Leakage Conditions V 3.0 − 5.5 Voltage Units Max Current IOH = −8 mA VIN = VIH V V µA µA IOL = 50 µA or VIL IOL = 4 mA IOL = 8 mA VIN = 5.5V or GND VIN = VCC or GND Noise Characteristics Symbol VOLP Parameter Quiet Output Maximum (Note 3) Dynamic VOL VOLV Quiet Output Minimum (Note 3) Dynamic VOL VIHD Minimum HIGH Level (Note 3) Dynamic Input Voltage VILD Maximum LOW Level (Note 3) Dynamic Input Voltage TA = 25°C VCC (V) Typ Limits 5.0 0.5 0.8 V CL = 50 pF 5.0 −0.5 0.8 V CL = 50 pF 5.0 3.5 V CL = 50 pF 5.0 1.5 V CL = 50 pF Units Conditions Note 3: Parameter guaranteed by design. 3 www.fairchildsemi.com 74VHC164 Absolute Maximum Ratings(Note 1) 74VHC164 AC Electrical Characteristics Symbol fMAX TA = 25°C TA = −40°C to +85°C Parameter VCC (V) Min Typ Maximum Clock Frequency 3.3 ± 0.3 80 125 50 75 45 5.0 ± 0.5 125 175 105 85 115 tPLH Propagation Delay tPHL Time (CP–Qn) 3.3 ± 0.3 5.0 ± 0.5 tPLH Propagation Delay tPHL Time (MR–Qn) 3.3 ± 0.3 5.0 ± 0.5 Max Min Max 65 MHz MHz 75 8.4 12.8 1.0 15.0 10.9 16.3 1.0 18.5 5.8 9.0 1.0 10.5 7.3 11.0 1.0 12.5 8.3 12.8 1.0 15.0 10.8 16.3 1.0 18.5 5.2 8.6 1.0 10.0 6.7 10.6 1.0 12.0 10 CIN Input Capacitance 4 CPD Power Dissipation 76 Units 10 ns ns ns ns Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF pF VCC = Open pF (Note 4) Capacitance Note 4: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) = CPD * VCC * fIN + ICC. AC Operating Requirements Symbol tW(L) Parameter VCC (V) (Note 5) Minimum Pulse Width (CP) tW(H) tW(L) tS tH tREC Minimum Pulse Width (MR) Minimum Setup Time Minimum Hold Time Minimum Removal Time (MR) Note 5: VCC is 3.3 ± 0.3V or 5.0 ± 0.5V www.fairchildsemi.com 4 TA = 25°C Typ TA = −40°C to +85°C Guaranteed Minimum 3.3 5.0 5.0 5.0 5.0 5.0 3.3 5.0 5.0 5.0 5.0 5.0 3.3 5.0 6.0 5.0 4.5 4.5 3.3 0.0 0.0 5.0 1.0 1.0 3.3 2.5 2.5 5.0 2.5 2.5 Units ns ns ns ns ns 74VHC164 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com 74VHC164 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 www.fairchildsemi.com 6 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 74VHC164 8-Bit Serial-In, Parallel-Out Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued)