ICS8302 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8302 is a low skew, 1-to-2 LVCMOS Fa n o u t B u f f e r a n d a m e m b e r o f t h e HiPerClockS™ HiPerClock S™ family of High Performance Clock Solutions from ICS. The ICS8302 has a single ended clock input. The single ended clock input accepts LVCMOS or LVTTL input levels. The ICS8302 features a pair of LVCMOS/LVTTL outputs. The ICS8302 is characterized at full 3.3V for input VDD, and mixed 3.3V and 2.5V for output operating supply modes (VDDO). Guaranteed output and par t-to-par t skew characteristics make the ICS8302 ideal for clock distribution applications demanding well defined performance and repeatibility. • 2 LVCMOS / LVTTL outputs ICS • LVCMOS / LVTTL clock input accepts LVCMOS or LVTTL input levels • Maximum output frequency: 200MHz • Output skew: 25ps (typical) • Part-to-part skew: 250ps (typical) • Small 8 lead SOIC package saves board space • Full 3.3V or 3.3V core, 2.5V supply modes • 0°C to 70°C ambient operating temperature • Lead-Free package available • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT Q0 VDDO VDD CLK GND CLK Q1 1 2 3 4 8 7 6 5 Q0 GND VDDO Q1 ICS8302 8-Lead SOIC 3.8mm x 4.8mm, x 1.47mm package body M Package Top View 8302AM www.icst.com/products/hiperclocks.html 1 REV. C JUNE 15, 2004 ICS8302 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1, 6 VDDO Power Type Description Output supply pins. 2 VDD Power Core supply pin. 3 CLK Input 4,7 GND Power Pulldown Power supply ground. LVCMOS / LVTTL clock input. 5 Q1 Output Single clock output. LVCMOS / LVTTL interface levels. 8 Q0 Output Single clock output. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions CPD Power Dissipation Capacitance (per output) RPULLDOWN Input Pulldown Resistor ROUT Output Impedance 8302AM Minimum Typical Maximum Units 4 pF VDD, VDDO = 3.465V 22 pF VDD = 3.465V, VDDO = 2.625V 16 pF 51 KΩ 5 www.icst.com/products/hiperclocks.html 2 7 12 Ω REV. C JUNE 15, 2004 ICS8302 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 112.7°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Minimum Typical Maximum Units VDD Core Supply Voltage Test Conditions 3.135 3.3 3.465 V 3.135 3.3 VDDO Output Power Supply Voltage 3.465 V IDD Power Supply Current 13 mA IDDO Output Supply Current 4 mA TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage Test Conditions Minimum Typical 2 Units VDD + 0.3 V VIL Input Low Voltage IIH Input High Current CLK VDD = VIN = 3.465V IIL Input Low Current CLK VDD = 3.465V, VIN = 0V -5 µA 50Ω to VDDO/2 2.6 V IOH = -100µA 2.9 V VOH Output High Voltage VOL Output Low Voltage -0.3 Maximum 1.3 V 150 µA 50Ω to VDDO/2 0.5 V IOL = 100µA 0.2 V Maximum Units 200 MHz 2.8 ns TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions fMAX Output Frequency tpLH Propagation Delay, Low-to-High; NOTE 1 ƒ≤ 200MHz Minimum 1.9 Typical 2.35 tsk(o) Output Skew; NOTE 2, 4 25 85 ps tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 250 800 ps tR Output Rise Time 20% to 80% 300 800 ps tF Output Fall Time 20% to 80% 300 800 ps ƒ≤ 133MHz 45 55 % odc Output Duty Cycle 133MHz < ƒ ≤ 200MHz 40 60 % Parameters measured at fMAX unless otherwise noted. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 8302AM www.icst.com/products/hiperclocks.html 3 REV. C JUNE 15, 2004 ICS8302 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER TABLE 3C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Minimum Typical Maximum Units VDD Core Supply Voltage Test Conditions 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 13 mA IDDO Output Supply Current 4 mA TABLE 3D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Maximum Units VIH Input High Voltage Test Conditions Minimum 2 Typical VDD + 0.3 V VIL Input Low Voltage -0.3 1.3 V 150 µA IIH Input High Current CLK VDD = VIN = 3.465V IIL Input Low Current CLK VDD = 3.465V, VIN = 0V -5 µA VOH Output High Voltage 50Ω to VDDO/2 1.8 V IOH = -100µA 2.2 VOL Output Low Voltage V 50Ω to VDDO/2 0.5 IOL = 100µA 0.2 V V TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency Test Conditions tpLH Propagation Delay, Low-to-High; NOTE 1 tsk(o) Output Skew; NOTE 2, 4 tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 ƒ≤ 200MHz Minimum Typical 2.3 250 Maximum Units 200 MHz 3.3 ns 85 ps 800 ps tR Output Rise Time 20% to 80% 250 650 ps tF Output Fall Time 20% to 80% 250 650 ps odc Output Duty Cycle ƒ≤ 133MHz 45 55 % 133MHz < ƒ ≤ 200MHz 40 60 % Parameters measured at fMAX unless otherwise noted. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 8302AM www.icst.com/products/hiperclocks.html 4 REV. C JUNE 15, 2004 ICS8302 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 1.65V±5% 2.05V±5% 1.25V±5% SCOPE VDD, VDDO VDDO Qx LVCMOS SCOPE V DD Qx LVCMOS GND GND -1.65V±5% -1.25V±5% 3.3V OUTPUT LOAD AC TEST CIRCUIT PART 1 3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT V V DDO DD Qx Qx 2 2 V V PART 2 DDO DD Qy Qy 2 t sk(pp) PART-TO-PART SKEW 2 t sk(o) OUTPUT SKEW VDD 2 80% 80% CLK Clock Outputs 20% 20% tR tF VDDO 2 Q0, Q1 t OUTPUT RISE/FALL TIME Q0, Q1 PD PROPAGATION DELAY VDDOX VDDOX VDDOX 2 2 2 t PW t PERIOD odc = t PW t PERIOD OUTPUT PULSE WIDTH/PERIOD 8302AM www.icst.com/products/hiperclocks.html 5 REV. C JUNE 15, 2004 ICS8302 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER RELIABILITY INFORMATION TABLE 5. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3°C/W 112.7°C/W 128.5°C/W 103.3°C/W 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8302 is: 322 8302AM www.icst.com/products/hiperclocks.html 6 REV. C JUNE 15, 2004 ICS8302 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER PACKAGE OUTLINE - SUFFIX M FOR 8 LEAD SOIC TABLE 6. PACKAGE DIMENSIONS SYMBOL Millimeters MINIMUN N MAXIMUM 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 e H 4.00 1.27 BASIC 5.80 6.20 h 0.25 0.50 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-012 8302AM www.icst.com/products/hiperclocks.html 7 REV. C JUNE 15, 2004 ICS8302 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER TABLE 7. ORDERING INFORMATION Part/Order Number Marking Package ICS8302AM 8302AM 8 lead SOIC ICS8302AMT 8302AM 8 lead SOIC on Tape and Reel ICS8302AMLF 8302AMLF 8 lead "Lead Free" SOIC ICS8302AMLFT 8302AMLF 8 lead "Lead Free" SOIC on Tape and Reel Count 96 per tube 2500 96 per tube 2500 Temperature 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8302AM www.icst.com/products/hiperclocks.html 8 REV. C JUNE 15, 2004 ICS8302 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER REVISION HISTORY SHEET Rev B Table T1 T2 T3A & T3C T4A & T4B Page 2 2 3, 4 3, 4 T2 2 T7 8 C 8302AM Description of Change Pin Description table, revised VDD description. Pin Characteristics table, deleted RPULLUP row. Power Supply table, changed VDD parameter to correspond with description. AC Characteristics tables - added note "Parameters measured at fMAX unless otherwise noted." tpLH Test Conditions, added f ≤ 200MHz. Pin Chararcteristics table - changed CIN 4pF max. to 4pF typical. Added 5Ω min. and 12Ω max. to ROUT row. Ordering Information table - added "Lead-Free" par t number. www.icst.com/products/hiperclocks.html 9 Date 2/4/03 6/15/04 REV. C JUNE 15, 2004