ICS8344I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8344I is a low voltage, low skew fanout buffer and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8344I has two selectable clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can accept most standard differential input levels. The ICS8344I is designed to translate any differential signal levels to LVCMOS levels. The low impedance LVCMOS outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased to 48 by utilizing the ability of the outputs to drive two series terminated lines. Redundant clock applications can make use of the dual clock input. The dual clock inputs also facilitate board level testing. ICS8344I is characterized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V output operating supply modes. • 24 LVCMOS outputs, 7Ω typical output impedance ,&6 • 2 selectable differential clock input pairs for redundant clock applications • CLKx, nCLKx pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency up to 100MHz • Translates any single-ended input signal to LVCMOS with resistor bias on nCLK input • Multiple output enable pins for disabling unused outputs in reduced fanout applications • Output skew: 275ps (maximum) • Part-to-part skew: 600ps (maximum) Guaranteed output and part-to-part skew characteristics make the ICS8344I ideal for those clock distribution applications demanding well defined performance and repeatability. • Bank skew: 150ps (maximum) • 3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes • -40°C to 85°C ambient operating temperature BLOCK DIAGRAM PIN ASSIGNMENT Q8 Q9 VDDO GND Q10 Q11 Q12 Q13 VDDO GND Q14 Q15 CLK_SEL CLK0 nCLK0 0 CLK1 nCLK1 1 Q16 Q17 VDDO GND Q18 Q19 Q20 Q21 VDDO GND Q22 Q23 Q0 - Q7 OE1 Q8 - Q15 OE2 Q16 - Q23 OE3 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 ICS8344I Q7 Q6 VDDO GND Q5 Q4 Q3 Q2 VDDO GND Q1 Q0 OE1 OE2 OE3 CLK0 nCLK0 VDD GND CLK1 nCLK1 VDD GND CLK_SEL 48-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 8344BYI www.icst.com/products/hiperclocks.html 1 REV. A AUGUST 9, 2001 ICS8344I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1, 2, 5, 6 7, 8, 11, 12 Q16, Q17, Q18, Q19 Q20, Q21, Q22, Q23 Output Q16 thru Q23 outputs. 7Ω typical output impedance. VDDO Power Output supply pins. Connect 3.3V or 2.5V. GND Power Power supply ground. Connect to ground. 13 CLK_SEL Input 15, 19 VDD Power 16 nCLK1 Input 3, 9, 28, 34, 39, 45 4, 10, 14,18, 27, 33, 40, 46 Type 17 CLK1 Input 20 nCLK0 Input 21 CLK0 Input 22 OE3 Input 23 OE2 Input 24 OE1 Input 25, 26, 29, 30 31, 32, 35, 36 37, 38, 41, 42 43, 44, 47, 48 Q0, Q1, Q2, Q3 Q4, Q5, Q6, Q7 Q8, Q9, Q10, Q11 Q12, Q13, Q14, Q15 Description Clock select input. When HIGH, selects CLK1, nCLK1 inputs. Pulldown When LOW, selects CLK0, nCLK0. LVTTL / LVCMOS interface levels. Positive supply pins. Connect 3.3V or 2.5V. Pullup Inver ting differential clock input. Pulldown Non-inver ting differential clock input.. Pullup Inver ting differential clock input. Pulldown Non-inver ting differential clock input.. Output enable. Controls enabling and disabling of outputs Pullup Q16 thru Q23. Output enable. Controls enabling and disabling of outputs Pullup Q8 thru Q15. Output enable. Controls enabling and disabling of outputs Pullup Q0 thru Q7. Output Q0 thru Q7 outputs. 7Ω typical output impedance. Output Q8 thru Q15 outputs. 7Ω typical output impedance. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units 4 pF 4 pF 20 pF RPULLUP CLK0, nCLK0, CLK1, nCLK1 Input Capacitance CLK_SEL, OE1, OE2, OE3 Power Dissipation Capacitance (per output) Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ ROUT Output Impedance 7 Ω CIN CPD 8344BYI www.icst.com/products/hiperclocks.html 2 REV. A AUGUST 9, 2001 ICS8344I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER TABLE 3A. OUTPUT ENABLE FUNCTION TABLE Bank 1 Bank 2 Bank 3 Input Output Input Output Input Output OE1 Q0-Q7 OE2 Q8-Q15 OE3 Q16-Q23 0 Hi-Z 0 Hi-Z 0 Hi-Z 1 Enabled 1 Enabled 1 Enabled TABLE 3B. CLOCK SELECT FUNCTION TABLE Control Input Clock CLK_SEL CLK0, nCLK0 CLK1, nCLK1 0 Selected De-selected 1 De-selected Selected TABLE 3C. CLOCK INPUTS FUNCTION TABLE Inputs OE1, OE2, OE3 CLK Outputs nCLK Q0 thru Q23 Input to Output Mode Polarity 1 0 1 LOW Differential to Single Ended Non Inver ting 1 1 0 HIGH Differential to Single Ended Non Inver ting 1 0 Biased; NOTE 1 LOW Single Ended to Differential Non Inver ting 1 1 Biased; NOTE 1 HIGH Single Ended to Differential Non Inver ting 1 Biased; NOTE 1 0 HIGH Single Ended to Differential Inver ting 1 Biased; NOTE 1 1 LOW Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information section on page 13, Figure 8, which discusses wiring the differential input to accept single ended levels. 8344BYI www.icst.com/products/hiperclocks.html 3 REV. A AUGUST 9, 2001 ICS8344I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, θ JA Storage Temperature, TSTG 4.6V -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V 47.9°C/W (0lfpm) -65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VDD Positive Supply Voltage Test Conditions 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Quiescent Power Supply Current 95 mA Maximum Units 2 3.8 V -0.3 0.8 V 5 µA 150 µA TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current Test Conditions CLK_SEL, OE1, OE2, OE3 CLK_SEL, OE1, OE2, OE3 OE1, OE2, OE3 CLK_SEL Minimum Typical VDD = VIN = 3.465V VDD = VIN = 3.465V OE1, OE2, OE3 VDD = 3.465, VIN = 0V -150 µA CLK_SEL VDD = 3.465, VIN = 0V -5 µA 2.6 V IIL Input Low Current VOH Output High Voltage VDD = VDDO = 3.135V IOH = -36mA VOL Output Low Voltage VDD = VDDO = 3.135V IOL = 36mA 0.6 V Maximum Units 5 µA 150 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol IIH Parameter Input High Current Test Conditions Minimum Typical nCLK0, nCLK1 CLK0, CLK1 nCLK0, nCLK1 IIL Input Low Current VPP Peak-to-Peak Input Voltage CLK0, CLK1 -150 µA -5 µA 0.15 Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 VCMR NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 8344BYI www.icst.com/products/hiperclocks.html 4 1.3 V VDD - 0.85 V REV. A AUGUST 9, 2001 Integrated Circuit Systems, Inc. ICS8344I LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions fMAX Maximum Output Frequency tpLH Propagation Delay, Low to High; NOTE 1 f ≤ 100MHz tpHL Propagation Delay, High to Low; NOTE 1 f ≤ 100MHz tsk(b) Minimum Typical Maximum Units 100 MHz 2.6 4.3 ns 2.4 4.3 ns Bank Skew; NOTE 2, 6 150 ps tsk(o) Output Skew; NOTE 3, 6 275 ps tsk(pp) Par t-to-Par t Skew; NOTE 4, 6 600 ps tR Output Rise Time; NOTE 5 30% to 70% 300 1700 ps tF Output Fall Time; NOTE 5 30% to 70% 300 1400 ps 40% odc Output Duty Cycle 60% % tEN Output Enable Time; NOTE 5 f = 66.7MHz 5 ns tDIS Output Disable TIme; NOTE 5 f = 66.7MHz 4 ns All parameters measured at 100MHz unless noted otherwise. NOTE 1: Measured from the diffferential input crossing point to VDDO/2. NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. 8344BYI www.icst.com/products/hiperclocks.html 5 REV. A AUGUST 9, 2001 ICS8344I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VDD Positive Supply Voltage Test Conditions 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Quiescent Power Supply Current 95 mA Maximum Units 2 3.8 V -0.3 0.8 V TABLE 4E. LVCMOS DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical CLK_SEL, OE1, OE2, OE3 CLK_SEL, OE1, OE2, OE3 OE1, OE2, OE3 VDD = VIN = 3.465V 5 µA CLK_SEL VDD = VIN = 3.465V 150 µA OE1, OE2, OE3 CLK_SEL VDD = 3.465, VIN = 0V -150 µA VDD = 3.465, VIN = 0 -5 µA 2 V VOH Output High Voltage VDD = 3.135V, VDDO = 2.375V IOH = -27mA VOL Output Low Voltage VDD = 3.135V, VDDO = 2.365V IOL = 27mA 0.63 V Maximum Units 5 µA 150 µA TABLE 4F. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage Minimum Typical nCLK0, nCLK1 CLK0, CLK1 nCLK0, nCLK1 -150 CLK0, CLK1 -5 0.15 VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 8344BYI µA www.icst.com/products/hiperclocks.html 6 µA 1.3 V VDD - 0.85 V REV. A AUGUST 9, 2001 Integrated Circuit Systems, Inc. ICS8344I LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions fMAX Maximum Output Frequency tpLH Propagation Delay, Low to High; NOTE 1 f ≤ 100MHz tpHL Propagation Delay, High to Low; NOTE 1 f ≤ 100MHz tsk(b) Minimum Typical Maximum Units 100 MHz 2.6 4.5 ns 2.6 4.5 ns Bank Skew; NOTE 2, 6 150 ps tsk(o) Output Skew; NOTE 3, 6 275 ps tsk(pp) Par t-to-Par t Skew; NOTE 4, 6 600 ps tR Output Rise Time; NOTE 5 30% to 70% 300 1700 ps tF Output Fall Time; NOTE 5 30% to 70% 300 1400 ps odc Output Duty Cycle 40% 60% % tEN Output Enable Time; NOTE 5 f = 66.7MHz 6 ns tDIS Output Disable TIme; NOTE 5 f = 66.7MHz 6 ns All parameters measured at 100MHz unless noted otherwise. NOTE 1: Measured from the diffferential input crossing point to VDDO/2. NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. 8344BYI www.icst.com/products/hiperclocks.html 7 REV. A AUGUST 9, 2001 ICS8344I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER TABLE 4G. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Positive Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Quiescent Power Supply Current 95 mA Maximum Units 2 2.9 V -0.3 0.8 V TABLE 4H. LVCMOS DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current VOH VOL Test Conditions Minimum Typical CLK_SEL, OE1, OE2, OE3 CLK_SEL, OE1, OE2, OE3 OE1, OE2, OE3 VDD = VIN = 2.625V 5 µA CLK_SEL VDD = VIN = 2.625V 150 µA OE1, OE2, OE3 VDD = 2.625, VIN = 0V -150 µA CLK_SEL VDD = 2.625, VIN = 0V -5 µA Output High Voltage VDD = VDDO = 2.375V IOH = -27mA 2 V Output Low Voltage VDD = VDDO = 2.375V IOL = 27mA 0.6 V Maximum Units 5 µA 150 µA TABLE 4I. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage Minimum Typical nCLK0, nCLK1 CLK0, CLK1 nCLK0, nCLK1 CLK0, CLK1 -150 µA -5 µA 0.15 Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 VCMR NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 8344BYI www.icst.com/products/hiperclocks.html 8 1.3 V VDD - 0.85 V REV. A AUGUST 9, 2001 Integrated Circuit Systems, Inc. ICS8344I LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions fMAX Maximum Output Frequency tpLH Propagation Delay, Low to High; NOTE 1 f ≤ 100MHz tpHL Propagation Delay, High to Low; NOTE 1 f ≤ 100MHz tsk(b) Minimum Typical Maximum Units 100 MHz 2.7 4.3 ns 2.7 4.3 ns Bank Skew; NOTE 2, 6 150 ps tsk(o) Output Skew; NOTE 3, 6 275 ps tsk(pp) Par t-to-Par t Skew; NOTE 4, 6 600 ps tR Output Rise Time; NOTE 5 30% to 70% 300 1700 ps tF Output Fall Time; NOTE 5 30% to 70% 300 1400 ps odc Output Duty Cycle 40% 60% % tEN Output Enable Time; NOTE 5 f = 66.7MHz 6 ns tDIS Output Disable TIme; NOTE 5 f = 66.7MHz 6 ns All parameters measured at 100MHz unless noted otherwise. NOTE 1: Measured from the diffferential input crossing point to VDDO/2. NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. 8344BYI www.icst.com/products/hiperclocks.html 9 REV. A AUGUST 9, 2001 ICS8344I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION VDD VDDO SCOPE LVCMOS Qx VDD = +1.65V VDDO = +1.65V GND = -1.65V FIGURE 1A - 3.3V OUTPUT LOAD TEST CIRCUIT VDDO SCOPE LVCMOS Qx VDDO = +1.25V GND = -1.25V FIGURE 1B - 2.5V OUTPUT LOAD TEST CIRCUIT 8344BYI www.icst.com/products/hiperclocks.html 10 REV. A AUGUST 9, 2001 ICS8344I Integrated Circuit Systems, Inc. V DD LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER VDDO SCOPE LVCMOS Qx VDD = +2.05V VDDO = +1.25V GND = -1.25V FIGURE 1C - 3.3V/2.5V OUTPUT LOAD TEST CIRCUIT VDD CLK0, CLK1 V PP Cross Points V CMR nCLK0, nCLK1 GND FIGURE 2 - DIFFERENTIAL INPUT LEVEL Qx Qy tsk(o) FIGURE 3 - OUTPUT SKEW 8344BYI www.icst.com/products/hiperclocks.html 11 REV. A AUGUST 9, 2001 ICS8344I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER PART 1 Qx PART 2 Qy tsk(pp) FIGURE 4 - PART-TO-PART SKEW 70% 70% V 30% SWING 30% Clock Inputs and Outputs trise FIGURE 5 - INPUT tfall AND OUTPUT RISE AND FALL TIME CLK0, CLK1 nCLK0, nCLK1 V /2 DDOx Q0 - Q23 tp tp LH HL FIGURE 6 - PROPAGATION DELAY CLK0, CLK1, Q0 - Q23 nCLK0, nCLK1 Pulse Width t t odc = t PERIOD PW PERIOD FIGURE 7 - odc & tPERIOD 8344BYI www.icst.com/products/hiperclocks.html 12 REV. A AUGUST 9, 2001 ICS8344I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 8 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD VCC CLK_IN CLK_IN R1 1K R1 1K + + V_REF V_REF - C1 C1 0.1uF 0.1uF R2 1K R2 1K FIGURE 8 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 8344BYI www.icst.com/products/hiperclocks.html 13 REV. A AUGUST 9, 2001 ICS8344I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W 200 55.9°C/W 42.1°C/W 500 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8344I is: 1,449 8344BYI www.icst.com/products/hiperclocks.html 14 REV. A AUGUST 9, 2001 ICS8344I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER PACKAGE OUTLINE - Y SUFFIX TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BCC SYMBOL MINIMUM NOMINAL 48 N 1.60 A A1 MAXIMUM 0.05 0.15 A2 1.35 1.40 1.45 b 0.17 0.22 0.27 c 0.09 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.50 E 9.00 BASIC E1 7.00 BASIC E2 5.50 e 0.5 BASIC L 0.45 q 0° 0.60 0.75 7° 0.08 ccc Reference Document: JEDEC Publication 95, MS-026 8344BYI www.icst.com/products/hiperclocks.html 15 REV. A AUGUST 9, 2001 ICS8344I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS8344BYI ICS8344BYI-T ICS8344BYI 48 Lead LQFP 250 per tray -40°C to 85°C ICS8344BYI 48 Lead LQFP on Tape and Reel 1000 -40°C to 85°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8344BYI www.icst.com/products/hiperclocks.html 16 REV. A AUGUST 9, 2001