ICS840011 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS840011 is a Fibre Channel Clock Generator and a member of the HiPerClocksTM HiPerClockS™ family of high performance devices from ICS. The ICS840011 uses a 26.5625MHz or 25MHz crystal to synthesize 106.25MHz or 100MHz respectively. The ICS840011 has excellent phase jitter performance, from 637KHz – 10MHz integration range. The ICS840011 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. • 1 LVCMOS/LVTTL output, 7Ω output impedence ICS • Crystal oscillator interface designed for a 26.5625MHz or 25MHz, 18pF parallel resonant crystal • Output frequency: 106.25MHz (typical) • VCO range: 560MHz to 680MHz • RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal (637KHz - 10MHz): 0.780ps (typical) • RMS phase noise at 106.25MHz (typical) Phase noise: Offset Noise Power 100Hz ............... -95.7 dBc/Hz 1KHz ................ -121 dBc/Hz 10KHz ................ -129 dBc/Hz 100KHz .............. -129.6 dBc/Hz • 3.3V operating supply • -30°C to 85°C ambient operating temperature FREQUENCY TABLE Inputs Crystal Frequency (MHz) 26.5625 Output Frequency (MHz) 106.25 25 100 BLOCK DIAGRAM PIN ASSIGNMENT OE (Pullup) XTAL_IN OSC XTAL_OUT Phase Detector VCO 637.5MHz w/ 26.5625MHz Ref. ÷6 Q0 1 2 3 4 8 7 6 5 VDD Q0 GND nc ICS840011 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View M = ÷24 (fixed) 840011AG VDDA OE XTAL_OUT XTAL_IN www.icst.com/products/hiperclocks.html 1 REV. A OCTOBER 15, 2004 ICS840011 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name 1 VDDA Power Type 2 OE Input 3, 4 5 XTAL_OUT, XTAL_IN nc Unused 6 GND Power 7 Q0 Output 8 VDD Power Input Description Pullup Analog supply pin. Output enable pin. When HIGH, Q0 output is enabled. When LOW, forces Q0 to HiZ state. LVCMOS/LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. No connect. Power supply ground. Single-ended clock output. LVCMOS/LVTTL interface levels. 7Ω output impedance. Core supply pin. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions CIN Input Capacitance CPD Power Dissipation Capacitance RPULLUP Input Pullup Resistor ROUT Output Impedance Minimum VDD, VDDA = 3.465V 5 Typical Maximum Units 4 pF 24 pF 51 KΩ 7 12 Ω TABLE 3. CONTROL FUNCTION TABLE Control Inputs Output OE Q0 0 Hi-Z 1 Active 840011AG www.icst.com/products/hiperclocks.html 2 REV. A OCTOBER 15, 2004 ICS840011 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, θJA 101.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -30°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VDD Core Supply Voltage Test Conditions 3.135 3.3 3.465 V 3.135 3.3 VDDA Analog Supply Voltage 3.465 V IDD Power Supply Current 80 mA IDDA Analog Supply Current 10 mA Maximum Units TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -30°C TO 85°C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current OE VDD = VIN = 3.465V 5 µA IIL Input Low Current OE VDD = 3.465V, VIN = 0V VOH Output High Voltage; NOTE 1 -150 µA 2.6 V VOL Output Low Voltage; NOTE 1 NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information Section, "3.3V Output Load Test Circuit". 0.5 V Maximum Units TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Fundamental 26.5625 MHz Equivalent Series Resistance (ESR) Frequency 50 Ω Shunt Capacitance 7 pF TABLE 6. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -30°C TO 85°C Symbol Parameter fOUT Output Frequency RMS Phase Jitter (Random); NOTE 1 Output Rise/Fall Time tjit(Ø) tR / tF Test Conditions odc Output Duty Cycle All parameters are characterized @ 106.25MHz. NOTE 1: Please refer to the Phase Noise Plot. 840011AG Minimum Typical Maximum Units 93.33 106.25 113.33 MHz fOUT = 106.25MHz, (637KHz to 10MHz) 20% to 80% 250 600 ps fOUT = 106.25MHz 48 52 % www.icst.com/products/hiperclocks.html 3 0.780 ps REV. A OCTOBER 15, 2004 ICS840011 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR TYPICAL PHASE NOISE AT 106.25MHZ ➤ 0 -10 Fibre Channel Filter -20 -30 106.25MHz -40 RMS Phase Jitter (Random) 637K to 10MHz = 0.780ps (typical) -50 NOISE POWER dBc Hz -60 -70 -80 -90 -100 Raw Phase Noise Data -110 ➤ -120 -130 -140 -150 ➤ -160 -170 -180 Phase Noise Result by adding Fibre Channel Filter to raw data -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 840011AG www.icst.com/products/hiperclocks.html 4 REV. A OCTOBER 15, 2004 ICS840011 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 1.65V ± 5% Phase Noise Plot SCOPE V DD Phase Noise Mask Qx LVCMOS GND f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot -1.65V ± 5% 3.3V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER V DD 80% 2 Q0 80% Pulse Width t odc = Clock Outputs PERIOD 20% 20% tR tF t PW t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 840011AG OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 5 REV. A OCTOBER 15, 2004 ICS840011 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS840011 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VDDA pin. 3.3V VDD .01µF 10Ω V DDA .01µF 10µF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. The ICS840011 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 26.5625MHz, 18pF XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p Figure 2. CRYSTAL INPUt INTERFACE 840011AG www.icst.com/products/hiperclocks.html 6 REV. A OCTOBER 15, 2004 ICS840011 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR APPLICATION SCHEMATIC Figure 3A shows a schematic example of the ICS840011. An example of LVCMOS termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. In this example, an 18pF parallel resonant 26.5625MHz crystal is used for generating VDD 106.25MHz output frequency. The C1 = 27pF and C2 = 33pF are recommended for frequency accuracy. For different board layout, the C1 and C2 values may be slightly adjusted for optimizing frequency accuracy. VDDA R2 10 C3 10uF C4 0.1u U1 OE C2 33pF 1 2 3 4 VDDA OE XTAL_OUT XTAL_IN VDD Q0 GND NC 8 7 6 5 R3 43 VDD Q Zo = 50 Ohm X1 C5 0.1u ICS840011 C1 27pF LVCMOS VDD=3.3V FIGURE 3A. ICS840011 SCHEMATIC EXAMPLE PC BOARD LAYOUT EXAMPLE Figure 3B shows an example of P.C. board layout. The crystal X1 footprint in this example allows either surface mount (HC49S) or through hole (HC49) package. C3 is 0805. C1 and C2 are 0402. Other resistors and capacitors are 0603. This layout assumes that the board has clean analog power and ground planes. FIGURE 3B. ICS840011 PC BOARD LAYOUT EXAMPLE 840011AG www.icst.com/products/hiperclocks.html 7 REV. A OCTOBER 15, 2004 ICS840011 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θJA by Velocity (Meters Per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W TRANSISTOR COUNT The transistor count for ICS840011 is: 1521 840011AG www.icst.com/products/hiperclocks.html 8 REV. A OCTOBER 15, 2004 ICS840011 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR 8 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 8 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 840011AG www.icst.com/products/hiperclocks.html 9 REV. A OCTOBER 15, 2004 ICS840011 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS840011AG 011A 8 lead TSSOP 100 per tube -30°C to 85°C ICS840011AGT 011A 8 lead TSSOP on Tape and Reel 2500 -30°C to 85°C ICS840011AGLN 011AN 100 per tube -30°C to 85°C ICS840011AGLNT 011AN 8 lead "Lead Free Annealed" TSSOP 8 lead "Lead Free Annealed" TSSOP on Tape and Reel 2500 -30°C to 85°C The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 840011AG www.icst.com/products/hiperclocks.html 10 REV. A OCTOBER 15, 2004 ICS840011 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR REVISION HISTORY SHEET Rev Table Page A T9 10 840011AG Description of Change Ordering Information Table - corrected count from 154 per tube to 100. www.icst.com/products/hiperclocks.html 11 Date 10/15/04 REV. A OCTOBER 15, 2004