ICS843051 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS843051 is a Gb Ethernet Generator and a member of the HiPerClocks TM family of high HiPerClockS™ performance devices from ICS. The ICS843051 can synthesize 10 Gigabit Ethernet, SONET, or Serial ATA reference clock frequencies with the appropriate choice of crystal and output divider. The ICS843051 has excellent phase jitter performance and is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. • 1 differential 3.3V LVPECL output ICS • Crystal oscillator interface designed for 18pF parallel resonant crystals • RMS phase jitter at: 155.52MHz (12KHz - 20MHz): 0.74ps (typical) 156.25MHz (1.875MHz - 20MHz): 0.43ps (typical) 161.13MHz (1.933MHz - 20MHz): 0.43ps (typical) • RMS phase noise at 156.25MHz Offset Noise Power 100Hz .................. -95 dBc/Hz 1KHz ................ -110 dBc/Hz 10KHz ................ -125 dBc/Hz 100KHz ................ -125 dBc/Hz • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request • Lead-Free package fully RoHS compliant PIN ASSIGNMENT FREQUENCY TABLE Inputs Crystal Frequency (MHz) FREQ_SEL Output Frequency (MHz) 20.141601 0 161.132812 20.141601 1 80.566406 19.53125 0 156.25 19.53125 1 78.125 19.44 0 155.52 19.44 1 77.76 18.75 0 15 0 18.75 1 75 VCCA VEE XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VCC Q0 nQ0 FREQ_SEL ICS843051 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View BLOCK DIAGRAM FREQ_SEL XTAL_IN OSC XTAL_OUT Phase Detector 0 ÷4 (default) 1 ÷8 VCO nQ0 Q0 ÷32 (fixed) 843051AG www.icst.com/products/hiperclocks.html 1 REV. A DECEMBER 14, 2004 ICS843051 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name Type 1 VCCA Power 2 3, 4 5 V EE XTAL_OUT, XTAL_IN FREQ_SEL Power 6, 7 nQ0, Q0 Output Differential clock outputs. LVPECL interface levels. 8 VCC Power Core supply pin. Input Input Description Analog supply pin. Negative supply pin. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characterristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 KΩ 843051AG Test Conditions Minimum www.icst.com/products/hiperclocks.html 2 Typical Maximum Units REV. A DECEMBER 14, 2004 ICS843051 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 101.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA=0°C TO 70°C Symbol Parameter Minimum Typical Maximum Units VCC Core Supply Voltage Test Conditions 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V ICC Power Supply Current 70 mA ICCA Analog Supply Current 15 mA IEE Power Supply Current 85 mA Maximum Units VCC + 0.3 V TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA=0°C TO 70°C Symbol Parameter Test Conditions VIH Input High Voltage FREQ_SEL Minimum Typical 2 VIL Input Low Voltage FREQ_SEL IIH Input High Current FREQ_SEL VCC = VIN = 3.465V IIL Input Low Current FREQ_SEL VCC = 3.465V, VIN = 0V -0.3 0.8 V 150 µA -5 µA TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA=0°C TO 70°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCC - 1.4 Typical VCC - 0.9 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V Maximum Units 40 MHz NOTE 1: Outputs terminated with 50Ω to VCC - 2V. TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Fundamental Frequency 12 Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF 843051AG www.icst.com/products/hiperclocks.html 3 REV. A DECEMBER 14, 2004 ICS843051 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA=0°C TO 70°C Symbol fOUT tjit(Ø) tR / tF Parameter Test Conditions Output Frequency RMS Phase Jitter (Random); NOTE 1 Output Rise/Fall Time 155.52MHz @ Integration Range: 12KHz - 20MHz 156.25MHz @ Integration Range: 1.875MHz - 20MHz 156.25MHz @ Integration Range: 12KHz - 20MHz 161.13MHz @ Integration Range: 1.933MHz - 20MHz 161.13MHz @ Integration Range: 12KHz - 20MHz 20% to 80% odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plots following this section. 843051AG Minimum www.icst.com/products/hiperclocks.html 4 Typical Maximum Units 155.52 MHz 156.25 MHz 161.13 MHz 0.74 ps 0.43 ps 0.75 ps 0.43 ps 0.72 ps 325 600 ps 49 51 % REV. A DECEMBER 14, 2004 ICS843051 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR TYPICAL PHASE NOISE AT 155.52MHZ ➤ 0 -10 -20 Filter -30 -40 -50 155.52MHz RMS Phase Noise Jitter 12KHz to 20MHz = 0.74ps (typical) -80 -90 -100 Raw Phase Noise Data -110 -120 -130 ➤ -140 ➤ NOISE POWER dBc Hz -60 -70 -150 -160 Phase Noise Result by adding a Filter to raw data -170 -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 156.25MHZ ➤ 0 -10 -20 Gb Ethernet Filter -30 -40 -50 156.25MHz RMS Phase Noise Jitter 1.875MHz to 20MHz = 0.43ps (typical) -70 -80 -90 Raw Phase Noise Data -100 -110 ➤ NOISE POWER dBc Hz -60 -120 -130 -140 -150 -190 100 ➤ -160 -170 -180 1k Phase Noise Result by adding Gb Ethernet Filter to raw data 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 843051AG www.icst.com/products/hiperclocks.html 5 REV. A DECEMBER 14, 2004 ICS843051 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR TYPICAL PHASE NOISE AT 161.13MHZ ➤ 0 -10 -20 Filter -50 161.13MHz -60 -70 RMS Phase Noise Jitter 1.933M to 20MHz = 0.43ps (typical) -80 -90 Raw Phase Noise Data -100 -110 ➤ NOISE POWER dBc Hz -30 -40 -120 -130 -140 -150 ➤ -160 -170 -180 -190 100 Phase Noise Result by adding a Filter to raw data 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 843051AG www.icst.com/products/hiperclocks.html 6 REV. A DECEMBER 14, 2004 ICS843051 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 2V Phase Noise Plot Qx SCOPE Noise Power V CC LVPECL Phase Noise Mask nQx VEE f1 Offset Frequency f2 -1.3V ± 0.165V RMS Jitter = Area Under the Masked Phase Noise Plot 3.3V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER nQ0 80% Q0 80% VSW I N G Pulse Width t odc = Clock Outputs PERIOD 20% 20% t PW tR tF t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 843051AG OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 7 REV. A DECEMBER 14, 2004 ICS843051 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843051 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01µF 10Ω V CCA .01µF 10µF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. The ICS843051 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 26.04167MHz, 18pF XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p Figure 2. CRYSTAL INPUt INTERFACE 843051AG www.icst.com/products/hiperclocks.html 8 REV. A DECEMBER 14, 2004 ICS843051 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR LAYOUT GUIDELINE parallel resonant crystal is used. The C1 = 27pF and C2 = 33pF are recommended for frequency accuracy. The C1 and C2 values may be slightly adjusted for optimizing frequency accuracy. Figure 3A shows a schematic example of the ICS843051. An example of LVEPCL termination is shown in this schematic. Additional LVPECL termination approaches are shown in the LVPECL Termination Application Note. In this example, an 18 pF VCCA VCC VCC VCC R2 10 C4 0.1u C3 10uF R3 133 R1 1K R5 133 Zo = 50 Ohm U1 Q XTAL2 C2 33pF 19.44MHz 18pF 1 2 3 4 VCCA VEE XTAL_OUT XTAL2 XTAL_IN XTAL1 VCC Q0 nQ0 FREQ_SEL 8 7 6 5 VCC Zo = 50 Ohm nQ X1 XTAL1 + - ICS843051 R4 82.5 C5 0.1u C1 27pF R6 82.5 FIGURE 3A. ICS843051 SCHEMATIC EXAMPLE PC BOARD LAYOUT EXAMPLE Figure 3B shows an example of ICS843051 P.C. board layout. The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through-hole HC49 package. The footprints of other components in this example are listed in the Table 6. There should be at least one decoupling capacitor per power pin. The decoupling capacitors should be located as close as possible to the power pins. The layout assumes that the board has clean analog power ground plane. TABLE 6. FOOTPRINT TABLE Reference Size C1, C2 0402 C3 0805 C4, C5 0603 R2 0603 NOTE: Table 6, lists component sizes shown in this layout example. FIGURE 3B. ICS843051 PC BOARD LAYOUT EXAMPLE 843051AG www.icst.com/products/hiperclocks.html 9 REV. A DECEMBER 14, 2004 ICS843051 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS843051. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843051 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_TYP = 3.465V * 85mA = 294.5mW Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 294.5mW + 30mW = 324.5mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.324W * 90.5°C/W = 99.3°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 843051AG 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W www.icst.com/products/hiperclocks.html 10 REV. A DECEMBER 14, 2004 ICS843051 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = V OH_MAX (V CCO_MAX • -V OH_MAX OL_MAX CCO_MAX -V CC_MAX – 0.9V ) = 0.9V For logic low, VOUT = V (V =V =V CC_MAX – 1.7V ) = 1.7V OL_MAX Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CC_MAX - 2V))/R ] * (V CC_MAX L -V OH_MAX ) = [(2V - (V CC_MAX -V OH_MAX ))/R ] * (V CC_MAX L -V OH_MAX )= [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 843051AG www.icst.com/products/hiperclocks.html 11 REV. A DECEMBER 14, 2004 ICS843051 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W TRANSISTOR COUNT The transistor count for ICS843051 is: 1892 843051AG www.icst.com/products/hiperclocks.html 12 REV. A DECEMBER 14, 2004 ICS843051 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR 8 LEAD TSSOP TABLE 9. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 8 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 843051AG www.icst.com/products/hiperclocks.html 13 REV. A DECEMBER 14, 2004 ICS843051 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS843051AG 3051A 8 Lead TSSOP 100 per tube 0°C to 70°C ICS843051AGT 3051A 8 Lead TSSOP on Tape and Reel 2500 0°C to 70°C ICS843051AGLF 051AL 100 per tube 0°C to 70°C ICS843051AGLFT 051AL 8 Lead "Lead-Free" TSSOP 8 Lead "Lead-Free" TSSOP on Tape and Reel 2500 0°C to 70°C The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843051AG www.icst.com/products/hiperclocks.html 14 REV. A DECEMBER 14, 2004 ICS843051 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR REVISION HISTORY SHEET Rev A A 843051AG Table T10 Page 14 T10 1 14 Description of Change Ordering Information Table - corrected count from 154 per tube to 100 per tube. Added Lead-Free bullet in Features section. Ordering Information Table - added "Lead-Free" par t. www.icst.com/products/hiperclocks.html 15 Date 11/16/04 12/14/04 REV. A DECEMBER 14, 2004