ICS ICS9112-17

Integrated
Circuit
Systems, Inc.
ICS9112-17
Low Skew Output Buffer
General Description
Features
The ICS9112-17 is a high performance, low skew, low jitter
zero delay buffer. It uses a phase lock loop (PLL) technology
to align, in both phase and frequency, the REF input with the
CLKOUT signal. It is designed to distribute high speed
clocks in PC systems operating at speeds from 25 to
133 MHz.
•
•
•
ICS9112-17 is a zero delay buffer that provides
synchronization between the input and output. The
synchronization is established via CLKOUT feed back to the
input of the PLL. Since the skew between the input and
output is less than +/- 350 pS, the part acts as a zero delay
buffer.
Zero input - output delay
Frequency range 25 - 133 MHz (3.3V)
High loop filter bandwidth ideal for Spread Spectrum
applications.
Less than 200 ps cycle to cycle Jitter
Skew controlled outputs
Skew less than 250 ps between outputs
Available in 16 pin, 150 mil SSOP & SOIC package
•
•
•
•
Pin Configuration
The ICS9112-17 has two banks of four outputs controlled by
two address lines. Depending on the selected address line,
bank B or both banks can be put in a tri-state mode. In this
mode, the PLL is still running and only the output buffers are
put in a high impedance mode. The test mode shuts off the
PLL and connects the input directly to the output buffers (see
table below for functionality).
The ICS9112-17 comes in a sixteen pin 150 mil SOIC or 16
pin SSOP package. In the absence of REF input, will be in the
power down mode. In this mode, the PLL is turned off and the
output buffers are pulled low. Power down mode provides
the lowest power consumption for a standby condition.
16 pin SSOP & SOIC
Block Diagram
Functionality
9112-17 Rev G 10/20/00
FS2
FS1
CLKA
(1, 4)
CLKB
(1, 4)
CLKOUT
Output
Source
PLL
Shutdown
0
0
Tristate
Tristate
Driven
PLL
N
0
1
Driven
Tristate
Driven
PLL
N
1
0
PLL
Bypass
Mode
PLL
Bypass
Mode
PLL
Bypass
Mode
REF
Y
1
1
Driven
Driven
Driven
PLL
N
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9112-17
Pin Descriptions
PIN NUMBER
1
2
3
PIN NAME
2
REF
CLKA2
VDD
5, 12
GND
6
7
8
9
IN
DESCRIPTION
Input reference frequency.
3
OUT
Buffered clock output, Bank A
3
OUT
Buffered clock output, Bank A
PWR
Power Supply (3.3V)
CLKA1
4, 13
TYPE
PWR
Ground
CLKB1
3
OUT
Buffered clock output. Bank B
CLKB2
3
OUT
Buffered clock output. Bank B
FS2
4
4
FS1
IN
Select input, bit 2
IN
Select input, bit 1
3
OUT
Buffered clock output. Bank B
3
OUT
Buffered clock output. Bank B
CLKA3
3
OUT
Buffered clock output, Bank A
15
CLKA4
3
OUT
Buffered clock output, Bank A
16
CLKOUT3
OUT
Buffered clock output, internal feedback on this pin
10
11
14
CLKB3
CLKB4
Notes:
1. Guaranteed by design and characterization. Not subject to 100% test.
2. Weak pull-down
3. Weak pull-down on all outputs
4. Weak pull-ups on these inputs
2
ICS9112-17
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input & Supply
T A = 0 - 70C; Supply Voltage VDD = 5.0 V +/-10% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Operating current
Input frequency
Input Capacitance
1
SYMBOL
CONDITIONS
VIH
VIL
IIH
VIN = VDD
IIL
VIN = 0 V;
C L = 0 pF; FIN @ 66M
IDD1
Fi 1
C IN1
VDD = 3.3 V; All Outputs Loaded
MIN
2.0
GND -0.5
TYP
2.5
0.1
19
45
MAX
UNITS
VDD +0.5
V
0.8
V
100
uA
50
uA
65
mA
25
Logic Inputs
133
MHz
5
pF
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input & Supply
T A = 0 - 70C; Supply Voltage VDD = 3.3 V +/-10% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Operating current
SYMBOL
VIH
VIL
IIH
IIL
IDD1
Input frequency
Fi 1
C IN1
Input Capacitance
1
CONDITIONS
MIN
2.0
GND-0.3
VIN = VDD
VIN = 0 V;
C L = 0 pF; FIN @ 66M
TYP
2.0
0.1
19
30
VDD = 3.3 V; All Outputs Loaded
Logic Inputs
Guarenteed by design, not 100% tested in production.
3
25
MAX UNITS
VDD+0.3
V
0.8
V
100
uA
50
uA
45
mA
133
M Hz
5.0
pF
ICS9112-17
Electrical Characteristics - OUTPUT
TA = 0 - 70C; VDD = VDDL = 5.0 V +/-10%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
VO = VDD*(0.5)
Output Impedance
RDSP
Output Impedance
RDSN
VO = VDD*(0.5)
Output High Voltage
VOH
IOH = -8 mA
Output Low Voltage
VOL
IOL = 8 mA
1
Rise Time
Tr
VOL = 0.8 V, VOH = 2.0 V
Fall Time1
Tf
VOH = 2.0 V, VOL = 0.8 V
Stable power supply, valid clock presented on
1
tLOCK
PLL Lock Time
REF pin
Duty Cycle1
Dt
VT = 1.4V;Cl=30pF
Tcyc-cyc at 66MHz , Loaded Outputs
Cycle to Cycle jitter1
Tcyc-cyc >66MHz , Loaded Outputs
Absolute Jitter1
Tjabs
10000 cycles; Cl=30pF
1
Jitter; 1-Sigma
Tj1s
10000 cycles; Cl=30pF
Skew1
Tsk
VT = 1.4 V (Window) Output to Output
Measured at VDD/2 on the CLKOUT
Tdsk-Tdsk
Device to Device Skew1
pins of devices
Delay Input-Output1
DR1
VT = 14 V
1
MIN
10
10
2.4
TYP
2.9
0.25
0.8
1.0
MAX UNITS
24
Ω
24
Ω
5.0
V
0.4
V
1.5
ns
1.5
ns
1.0
ms
60
250
200
100
30
250
%
ps
ps
ps
ps
ps
0
700
ps
0
700
ps
40
50
-100
60
14
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - OUTPUT
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
VO = VDD*(0.5)
Output Impedance
RDSP
Output Impedance
RDSN
VO = VDD*(0.5)
Output High Voltage
VOH
IOH = -8 mA
IOL = 8 mA
Output Low Voltage
VOL
Rise Time1
Tr
VOL = 0.8 V, VOH = 2.0 V
1
Fall Time
Tf
VOH = 2.0 V, VOL = 0.8 V
Stable power supply, valid clock presented on
PLL Lock Time1
tLOCK
REF pin
VT = 1.4V;Cl=30pF
Dt
Duty Cycle1
Dt
VT = Vdd/2; Fout <66.6MHz
Tcyc-cyc
at
66MHz , Loaded Outputs
Cycle to Cycle jitter1
Tcyc-cyc >66MHz , Loaded Outputs
Absolute Jitter1
Tjabs
10000 cycles; Cl=30pF
Jitter; 1-Sigma1
Tj1s
10000 cycles; Cl=30pF
Skew1
Tsk
VT = 1.4 V (Window) Output to Output
Measured at VDD/2 on the CLKOUT
Device to Device Skew1 Tdsk-Tdsk
pins of devices
Delay Input-Output1
DR1
VT = 14 V
1
Guaranteed by design, not 100% tested in production.
4
MIN
10
10
2.4
TYP
2.9
0.25
1.2
1.2
MAX UNITS
24
Ω
24
Ω
5.0
V
0.4
V
2.0
ns
2.0
ns
1.0
ms
60
55
250
200
100
30
250
%
%
ps
ps
ps
ps
ps
0
700
ps
0
700
ps
40
45
50
50
-100
70
14
ICS9112-17
Output to Output Skew
The skew between CLKOUT and the CLKA/B outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the
inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded, zero phase
difference will maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must equally loaded.
If the CLKA/B outputs are less loaded than CLKOUT, CLKA/B outputs will lead it; and if the CLKA/B is more loaded than
CLKOUT, CLKA/B will lag the CLKOUT.
Since the CLKOUT and the CLKA/B outputs are identical, they all start at the same time, but different loads cause them to
have different rise times and different times crossing the measurement thresholds.
REF input and
all outputs
loaded Equally
REF input and CLKA/B
outputs loaded equally, with
CLKOUT loaded More.
REF input and CLKA/B
outputs loaded equally, with
CLKOUT loaded Less.
Timing diagrams with different loading configurations
5
ICS9112-17
Application Suggestion:
ICS9112-17 is a mixed analog/digital product. The analog portion of the PLL is very sensitive to any random noise generated
by charging or discharging of internal or external capacitor on the power supply pins. This type of noise will cause excess
jitter to the outputs of ICS9112-17. Below is a recommended lay out to alleviate any addition noise. For additional
information on FT. layout, please refer to our AN07. The 0.1 uF capacitors should be connected as close as possible to power
pins (4 & 13). An Isolated power plane with a 2.2 uF capacitor to ground will enhance the power line stability.
33Ω
33Ω
0.1µF
33Ω
33Ω
10KΩ
1 REF
CLKOUT 16
2 CLKA1
CLKA4 15
3 CLKA2
CLKA3 14
4 VDD
VDD 13
5 GND
GND 12
6 CLKB1
CLKB4 11
7 CLKB2
CLKB3 10
8 FS2
FS1
9
33Ω
33Ω
33Ω
0.1µF
33Ω
33Ω
10KΩ
GND
GND
VDD
VDD
6
ICS9112-17
Ordering Information
ICS9112yF-17-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
7
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9112-17
Ordering Information
ICS9112yM-17-T
Example:
ICS XXXX y M - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
M=SOIC
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
8
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.