ICS9148-37 Integrated Circuit Systems, Inc. Frequency Generator & Integrated Buffers for PENTIUM/ProTM General Description Features • Generates the following system clocks: - 4 CPU(2.5V/3.3V) upto 100MHz. - 6 PCI(3.3V) @ 33.3MHz - 2AGP(3.3V) @ 2 x PCI - 12 SDRAMs(3.3V) @ either CPU or AGP - 2 REF (3.3V) @ 14.318MHz • Skew characteristics: - CPU – CPU<250ps - SDRAM – SDRAM < 250ps - CPU – SDRAM < 250ps - CPU–AGP: < 1ns - CPU(early) – PCI : 1-4ns • Supports Spread Spectrum modulation +0.25, ±0.6% Serial programming I C interface allows changing functions, stop clock programming and frequency selection. The SD_SEL latched input allows the SDRAM frequency to follow the CPUCLK frequency(SD_SEL=1) or the AGP clock frequency(SD_SEL=0) • Serial I2C interface for Power Management, Frequency Select, Spread Spectrum. • Efficient Power management scheme through PCI and CPU STOP CLOCKS. • Uses external 14.318MHz crystal Block Diagram • 48 pin 300mil SSOP. The ICS9148-37 is the single chip clock solution for Desktop/Notebook designs using the VIA MVP3 style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS914837 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. 2 Pin Configuration Power Groups VDD1 = REF (0:1), X1, X2 VDD2 = PCICLK_F, PCICLK(0:5) VDD3 = SDRAM (0:11), supply for PLL core, 24 MHz, 48MHz VDD4 = AGP (0:1) VDDL = CPUCLK (0:3) 0143G—08/04/04 48-Pin SSOP * Internal Pull-up Resistor of 240K to 3.3V on indicated inputs ICS9148-37 Pin Descriptions PIN NUMBER 1 2 3,9,16,22,27, 33,39,45 PIN NAME VDD1 REF0 TYPE PWR OUT C P U 3 . 3 # _ 2 . 5 1,2 IN GND PWR 4 X1 IN 5 X2 OUT VDD2 PWR PCICLK_F OUT 6,14 7 FS11, 2 IN PCICLK0 8 10, 11, 12, 13 15, 47 OUT 1, 2 FS2 IN PCICLK(1:4) OUT AGP (0:1) OUT 1 CPU_STOP# IN 17 SDRAM 11 PCI_STOP#1 OUT IN 18 SDRAM 10 OUT SDRAM (0:9) OUT 19,30,36 VDD3 PWR 23 24 SDATA SCLK 24MHz IN IN OUT 20, 21,28, 29, 31, 32, 34, 35,37,38 25 26 40, 41, 43, 44 42 46 48 MODE1, 2 IN 48MHz OUT FS01, 2 IN CPUCLK(0:3) VDDL REF1 SD_SEL VDD4 OUT PWR OUT IN PWR DESCRIPTION Ref (0:2), XTAL power supply, nominal 3.3V 14.318 MHz reference clock. Indicates whether VDDL2 is 3.3V or 2.5V. High=2.5V CPU, LOW=3.3V CPU1. Latched input2 Ground Cr ystal input, has inter nal load cap (33pF) and feedback resistor from X2 Cr ystal output, nominally 14.318MHz. Has inter nal load cap (33pF) Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V Free running PCI clock output. Synchronous with CPUCLKs with 1-4ns skew (CPU early) This is not affected by PCI_STOP# Frequency select pin. Latched Input. Along with other FS pins determines the CPU, SDRAM, PCI & AGP frequencies. PCI clock output. Synchronous CPUCLKs with 1-4ns skew (CPU early) Frequency select pin. Latched Input Along with other FS pins determines the CPU, SDRAM, PCI & AGP frequencies. PCI clock outputs. Synchronous CPUCLKs with 1-4ns skew (CPU early) Advanced Graphic Por t outputs, powered by VDD4. This asynchronous input halts CPUCLK (0:3) and AGP (0:1) clocks at logic 0 level, when input low (in Mobile Mode, MODE=0) SDRAM clock output. Frequency is selected by the SD_SEL latched input. SD_SEL = 1 at power on causes SDRAM frequency = CPU frequency SD_SEL = 0 at power on causes SDRAM frequency = AGP frequency This asynchronous input halts PCICLK(0:5) clocks at logic 0 level, when input low (In mobile mode, MODE=0) SDRAM clock output. Frequency is selected by the SD_SEL latched input. SD_SEL = 1 at power on causes SDRAM frequency = CPU frenquency SD_SEL = 0 at power on causes SDRAM frequency = AGP frequency SDRAM clock outputs. Frequency is selected by the SD_SEL latched input. SD_SEL = 1 at power on causes SDRAM frequency = CPU frequency SD_SEL = 0 at power on causes SDRAM frequencies = AGP frequency Supply for SDRAM (0:11), CPU Core and 24, 48MHz clocks, nominal 3.3V. Data input for I2C serial input. Clock input of I2C input 24MHz output clock, for Super I/O timing. Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input. 48MHz output clock, for USB timing. Frequency select pin. Latched Input Along with other FS pins determines the CPU, SDRAM, PCI & AGP frequencies. CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low Supply for CPU (0:3), either 2.5V or 3.3V nominal 14.318MHz reference clock. Latched input at Power On selects either CPU (SDSEL=1) or AGP (SD_SEL=0) frequencies for the SDRAM clock outputs. Supply for AGP (0:1) Notes: 1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low. 0143G—08/04/04 2 ICS9148-37 Mode Pin - Power Management Input Control MODE, Pin 25 (Latched Input) 0 1 Pin 17 Pin 18 CPU_STOP# (INPUT) SDRAM 11 (OUTPUT) PCI_STOP# (INPUT) SDRAM 10 (OUTPUT) Power Management Functionality PCICLK (0:5) PCICLK_F, REF, 24/48MHz and SDRAM Crystal OSC VCO CPU_STOP# PCI_STOP# AGP, CPUCLK Outputs 0 1 Stopped Low Running Running Running Running 1 1 Running Running Running Running Running 1 0 Running Stopped Low Running Running Running CPU 3.3#_2.5V Buffer selector for CPUCLK drivers. CPU3.3#_2.5 Input level (Latched Data) 1 0 Buffer Selected for operation at: 2.5V VDD 3.3V VDD Functionality VDD1, 2, 3, 4 = 3.3V±5%, VDDL = 2.5V ±5% or 3.3 ±5%, TA= 0 to 70°C Crystal (X1, X2) = 14.31818MHz FS2 FS1 FS0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 CPU (MHz) 100 95.25 83.3 75 75 68.5 66.8 60 SDRAM (MHz) SD_SEL=1 SD_SEL=0 100 66.6 95.25 63.5 83.3 66.6 75 60 75 75 68.5 68.5 66.8 66.8 60 60 0143G—08/04/04 3 PCI (MHz) AG P ( M H z ) 33.3 31.75 33.3 30 37.5 34.25 33.4 30 66.6 63.5 66.6 60 75 68.5 66.8 60 ICS9148-37 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: • • • • • • • • • • • • • • • • Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 • ICS clock will acknowledge each byte one at a time. • Controller (host) sends a Stop bit Controller (host) will send start bit. Controler (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ACK ICS (Slave/Receiver) ACK Byte Count Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Stop Bit Notes: 1. 2. 3. 4. 5. 6. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 0143G—08/04/04 4 ICS9148-37 Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = 0) Bit Description PWD 0 ± 0 . 2 5 % S p r e a d S p e c t r u m M o d u l a t i o n Bit 7 1 - ±0.6% Spread Spectrum Modulation 0 Bit6 Bit5 CPU Clock PCI AGP Bit4 111 100 33.3 66.6 110 95.25 31.75 63.5 Bit 101 83.3 33.3 66.6 Note 6:4 100 75 30 60 1 011 75 37.5 75 010 68.5 34.25 68.5 001 66.8 33.4 66.8 000 60 30 60 0 - Frequency is selected by hardware Bit 3 seleLcat,tched Inputs 0 1 - Frequency is selected by Bit 6:4 (above) 0 - Spread Spectrum center spread type. 0 1 - Spread Spectrum down spread type. Normal Bit 1 10 -- S 0 pread Spectrum Enabled unning Bit 0 10- -TR 0 ristate all outputs Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 40 41 43 44 PWD 1 1 1 1 1 1 1 1 Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Description (Reserved) (Reserved) (Reserved) (Reserved) CPUCLK3 (Act/Inact) CPUCLK2 (Act/Inact) CPUCLK1 (Act/Inact) CPUCLK0 (Act/Inact) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. Pin # 7 15 13 12 11 10 8 PWD 1 1 1 1 1 1 1 1 Description (Reserved) PCICLK_F (Act/Inact) AGP0 (Act/Inact) PCICLK4 (Act/Inact) PCICLK3 (Act/Inact) PCICLK2 (Act/Inact) PCICLK1 (Act/Inact) PCICLK0(Act/Inact) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 0143G—08/04/04 5 ICS9148-37 Byte 4: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 28 29 31 32 34 35 37 38 PWD 1 1 1 1 1 1 1 1 Description SDRAM7 (Act/Inact) SDRAM6 (Act/Inact) SDRAM5 (Act/Inact) SDRAM4 (Act/Inact) SDRAM3 (Act/Inact) SDRAM2 (Act/Inact) SDRAM1 (Act/Inact) SDRAM0 (Act/Inact) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. Pin # 47 46 2 PWD 1 1 1 1 1 1 1 1 Pin # - PWD 1 1 1 1 Bit 3 17 1 Bit 2 18 1 Bit 1 Bit 0 20 21 1 1 Description (Reserved) (Reserved) (Reserved) (Reserved) SDRAM11 (Act/Inact) (Desktop Mode Only) SDRAM10 (Act/Inact) (Desktop Mode Only) SDRAM9 (Act/Inact) SDRAM8 (Act/Inact) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Description (Reserved) (Reserved) (Reserved) AGP1(Act/Inact) (Reserved) (Reserved) REF1 (Act/Inact) REF0 (Act/Inact) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 0143G—08/04/04 6 ICS9148-37 CPU_STOP# Timing Diagram CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9148-37. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks. Notes: 1. All timing is referenced to the internal CPU clock. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9148-37. 3. All other clocks continue to run undisturbed. (including SDRAM outputs). 0143G—08/04/04 7 ICS9148-37 PCI_STOP# Timing Diagram PCI_STOP# is an asynchronous input to the ICS9148-37. It is used to turn off the PCICLK (0:5) clocks for low power operation. PCI_STOP# is synchronized by the ICS9148-37 internally. The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock. Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9148. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state. 0143G—08/04/04 8 ICS9148-37 Shared Pin Operation Input/Output Pins solder spot tabs or a physical jumper header may be used. These figures illustrate the optimal PCB physical layout options. These configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. The layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s). Pins 2, 7, 8, 25, 26 and 46 on the ICS9148-37 serve as dual signal functions to the device. During initial powerup, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm(10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figs. 1 and 2 show the recommended means of implementing this function. In Fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the device’s internal logic. Figs. 2a and b provide a single resistor loading option where either Fig. 1 0143G—08/04/04 9 ICS9148-37 Fig. 2a Fig. 2b 0143G—08/04/04 10 ICS9148-37 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . 7.0 V GND –0.5 V to VDD +0.5 V 0°C to +70°C –65°C to +150°C 115°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage VIH 2 VDD + 0.3 V VSS - 0.3 0.8 V Input Low Voltage VIL Input High Current I IH VIN = V DD 0.1 5 mA VIN = 0 V; Inputs with no pull-up resistors -5 2.0 mA Input Low Current IIL1 Input Low Current IIL2 VIN = 0 V; Inputs with pull-up resistors -200 -100 mA 100 160 mA Operating I DD3.3OP CL = 0 pF; 66.8 MHz Supply Current VDD = 3.3 V; 14.318 MHz Input frequency Fi Input Capacitance1 CIN Logic Inputs 5 pF X1 & X2 pins 27 36 45 pF CINX Transition Time1 Ttrans To 1st crossing of target Freq. 2 ms Settling Time1 Ts From 1st crossing to 1% target Freq. ms Clk Stabilization1 TSTAB From VDD = 3.3 V to 1% target Freq. 2 ms Skew1 1 TCPU-SDRAM1 VT = 1.5 V; SDRAM Leads TCPU-PCI1 VT = 1.5 V; CPU Leads TCPU-AGP VT = 1.5 V; CPU Leads -500 1 -1 200 2.8 0 500 4 1 ps ns ns Guaranteed by design, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating Supply Current Skew1 SYMBOL CONDITIONS CL = 0 pF; 66.8 MHz I DD2.5OP TCPU-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Lead TCPU-PCI2 VT = 1.5 V; VTL = 1.25 V; CPU Leads 1 Guaranteed by design, not 100% tested in production. 0143G—08/04/04 11 MIN TYP 10 MAX 20 UNITS mA -500 1 200 2.7 500 4 ps ns ICS9148-37 Electrical Characteristics - CPU TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output High Voltage VOH2B IOH = -8 mA Output Low Voltage VOL2B IOL = 12 mA Output High Current IOH2B VOH = 1.7 V Output Low Current IOL2B VOL = 0.7 V Rise Time VOL = 0.4 V, VOH = 2.0 V tr2B1 1 Fall Time VOH = 2.0 V, VOL = 0.4 V tf2B 1 Duty Cycle VT = 1.25 V dt2B Skew tsk2B1 VT = 1.25 V Jitter, Single Edge tjsed2B1 VT = 1.25 V Displacement2 Jitter, One Sigma tj1s2B 1 VT = 1.25 V Jitter, Absolute tjabs2B1 VT = 1.25 V 1 2 MIN 2 19 40 -300 TYP 2.2 0.3 -20 26 1.5 1.6 47 60 MAX 1.8 1.8 55 250 UNITS V V mA mA ns ns % ps 200 250 ps 65 160 150 300 ps ps 0.4 -16 Guaranteed by design, not 100% tested in production. Edge displacement of a period relative to a 10-clock-cycle rolling average period. Electrical Characteristics - CPU TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; C L = 10 - 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current SYMBOL VOH2A VOL2A IOH2A IOL2A Rise Time tr2A1 tf2A1 d t2A1 tsk2A1 t j1s2A1 tjabs2A1 Fall Time Duty Cycle Skew Jitter, One Sigma Jitter, Absolute 1 CONDITIONS IOH = -28 mA IOL = 27 mA VOH = 2.0 V VOL = 0.8 V MIN 2.5 33 TYP 2.6 0.35 -29 37 MAX 0.4 -23 UNITS V V mA mA VOL = 0.4 V, VOH = 2.4 V 1.75 2 ns VOH = 2.4 V, VOL = 0.4 V 1.1 2 ns 50 55 % 50 250 ps 65 150 ps 165 250 ps VT = 1.5 V 45 VT = 1.5 V VT = 1.5 V VT = 1.5 V -250 Guaranteed by design, not 100% tested in production. 0143G—08/04/04 12 ICS9148-37 Electrical Characteristics - SDRAM TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF PARAMETER SYMBOL CONDITIONS IOH = -28 mA Output High Voltage VOH1 IOL = 23 mA Output Low Voltage VOL1 VOH = 2.0 V Output High Current IOH1 VOL = 0.8 V Output Low Current IOL1 1 Rise Time Tr1 VOL = 0.4 V, VOH = 2.4 V Fall Time1 Tf1 VOH = 2.4 V, VOL = 0.4 V Duty Cycle1 1 Skew Jitter, One Sigma 1 Jitter, Absolute1 Jitter, Absolute1 1 MIN 2.4 41 45 TYP 3 0.2 -60 50 MAX UNITS V V mA mA 1.75 2 ns 1.5 2 ns 50 55 % 0.4 -40 Dt1 VT = 1.5 V Tsk1 VT = 1.5 V 200 500 ps Tj1s1 VT = 1.5 V 50 150 ps Tjabs1 Tjabs1 VT = 1.5 V (with synchronous PCI) VT = 1.5 V (with asynchronous PCI) -250 +250 ps -400 400 ps Guaranteed by design, not 100% tested in production. Electrical Characteristics - PCI TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; C L = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current CONDITIONS IOH = -28 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V MIN 2.4 41 TYP 3 0.2 -60 50 MAX 0.4 -40 UNITS V V mA mA tr1 1 VOL = 0.4 V, VOH = 2.4 V 1.8 2 ns tf1 1 VOH = 2.4 V, VOL = 0.4 V 1.6 2 ns Duty Cycle d t1 1 VT = 1.5 V 51 55 % Skew tsk1 1 VT = 1.5 V 130 250 ps tj1s1a tj1s1b VT = 1.5 V, synchronous VT = 1.5 V, asynchronous 40 200 150 250 ps ps tab s1a tjabs1b VT = 1.5 V, synchronous VT = 1.5 V, asynchronous 135 500 250 650 ps ps Rise Time Fall Time Jitter, One Sigma Jitter, Absolute 1 SYMBOL VOH1 VOL1 IOH1 IOL1 1 1 45 Guaranteed by design, not 100% tested in production. 0143G—08/04/04 13 -250 -650 ICS9148-37 Electrical Characteristics - AGP TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current CONDITIONS IOH = -28 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V tr1 1 VOL = 0.4 V, VOH = 2.4 V Fall Time tf1 1 VOH = 2.4 V, VOL = 0.4 V Duty Cycle d t1 1 VT = 1.4 V 1 tj1s1 Rise Time 1 SYMBOL VOH1 VOL1 IOH1 IOL1 Skew Jitter, One Sigma1 tsk1 Jitter, Absolute1 tabs1a tjabs1b MIN 2.4 41 TYP 3 0.2 -60 50 MAX 1.1 2 ns 0.4 -40 UNITS V V mA mA 1 2 ns 49 55 % VT = 1.5 V 130 250 ps VT = 1.5 V 2 3 % 2.5 4.5 5 6 % % TYP 2.6 0.3 -32 25 MAX UNITS V V mA mA 2 4 ns 1.9 4 ns 54 57 % 1 3 % - 5 % 45 VT = 1.5 V, synchronous VT = 1.5 V, asynchronous -5 -6 Guaranteed by design, not 100% tested in production. Electrical Characteristics - 24MHz, 48MHz, REF0 TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current CONDITIONS IOH = -16 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V tr5 1 VOL = 0.4 V, VOH = 2.4 V Fall Time tf5 1 VOH = 2.4 V, VOL = 0.4 V Duty Cycle d t5 1 Rise Time Jitter, One Sigma Jitter, Absolute 1 SYMBOL VOH5 VOL5 IOH5 IOL5 1 tj1s5 tjabs5 1 MIN 2.4 16 VT = 1.5 V 45 VT = 1.5 V VT = 1.5 V -5 Guaranteed by design, not 100% tested in production. 0143G—08/04/04 14 0.4 -22 ICS9148-37 General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance. Notes: 1) All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram. 2) 47 ohm / 56pf RC termination should be used on all over 50MHz outputs. 3) Optional crystal load capacitors are recommended. Connections to VDD: 0143G—08/04/04 15 ICS9148-37 300 mil SSOP c N SYMBOL L E1 INDEX AREA A A1 b c D E E1 e h L N a E 1 2 α h x 45° D A In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° VARIATIONS N A1 -Ce In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° SEATING PLANE b .10 (.004) C 48 D mm. MIN 15.75 D (inch) MAX 16.00 MIN .620 MAX .630 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 Ordering Information ICS9148yF-37 LF-T Example: ICS XXXX y F PPP LF- T Designation for tape and reel packaging Lead Free (Optional) Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0143G—08/04/04 16