Integrated Circuit Systems, Inc. ICS9248-143 Frequency Generator & Integrated Buffers for PENTIUM II/IIITM & K6 Block Diagram PLL2 48MHz 24_48MHz /2 X1 X2 XTAL OSC 2 REF[1:0] BUFFER IN CPUCLK_F PLL1 Spread Spectrum FS(0:3) SEL24_48# STOP 3 CPUCLK [2:0] 4 STOP LATCH 8 SDRAM [7:0] SDRAM_F 4 POR CLK_STOP# PCI CLOCK DIVDER STOP 6 PCICLK [5:0] PCI_STOP# CPU2.5_3.3# Control Logic PCICLK_F SDATA SCLK PD# Config. PCICLK_E Reg. 9248-143 Rev C 7/26/00 Pin Configuration VDDREF *SPREAD/REF0 GNDREF X1 X2 VDDPCI *CPU2.5_3.3#/PCICLK_F *FS3/PCICLK0 GNDPCI *SEL24_48#/PCICLK1 *SELPCIE_6#/PCICLK2 PCICLK3 PCICLK4 VDDPCI BUFFER IN GNDPCI PCICLK5 PCICLK6/PCICLK_E VDDCOR PCI_STOP# *PD# GND48 SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ICS9248-143 Recommended Application: 440BX, MX, VIA Apollo Pro 133, Apollo Pro Media or MVP4 style chip set, for Note book applications. Output Features: 4 - CPUs @ 2.5V/3.3V including 1 free running CPUCLK_F 9 - SDRAM @ 3.3V 7 - PCI @ 3.3V, including 1 free running PCICLK_F 1 - PCI Early @ 3.3V 1 - 48MHz, @ 3.3V fixed. 1 - 24/48MHz @ 3.3V 2 - REF @3.3V, 14.318MHz. Features: Up to 137MHz frequency support 97MHz to support high-end AMD processor. Support power management: CLK, PCI, stop and Power down Mode from I2C programming. Spread spectrum for EMI control (±.25% & 0 to -0.5% down spread). Uses external 14.318MHz crystal FS pins for frequency select Key Specifications: CPU Output Jitter @ 2.5V: <300ps CPU Output Jitter @ 3.3V: <250ps PCI Output Jitter @ 3.3V: <250ps CPU Output Skew @ 2.5V: <175ps CPU Output Skew @ 3.3V: <175ps PCI Output Skew @ 3.3V: <500ps PCI Early to PCI Skew @ 3.3V: typ = 3ns 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF1/FS2* VDDLCPU CPUCLK_F CPUCLK0 GNDLCPU CPUCLK1 CPUCLK2 CLK_STOP# GNDSDR SDRAM_F SDRAM0 SDRAM1 VDDSDR SDRAM2 SDRAM3 GNDSDR SDRAM4 SDRAM5 VDDSDR SDRAM6 SDRAM7 VDD48 48MHz/FS0* 24_48MHz/FS1* 48-Pin SSOP and TSSOP * Internal Pull-up Resistor of 120K to VDD Functionality FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHz) 66.67 100.00 100.30 133.33 105.00 133.37 137.00 75.00 100.00 95.00 97.00 133.33 90.00 96.22 66.82 91.50 PCI (MHz) 33.33 33.33 33.43 33.33 35.00 33.34 34.25 37.50 33.33 31.67 32.33 33.33 30.00 32.07 33.41 30.50 Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-143 Pin Descriptions PIN NUMBER 1 2 20 3, 9, 16, 33, 40, 44 4 5 6,14 7 8 10 11 17, 13, 12 P I N NA M E TYPE VDDREF S P R E A D 1,2 REF0 PWR IN OUT PCI_STOP# IN GND X1 PWR IN DESCRIPTION Ref, XTAL power supply, nominal 3.3V Active High Spread Spectrum enable input. Power-up default is "High", spreading is "on" 14.318 Mhz reference clock.This REF output is the STRONGER buffer for ISA BUS loads Halts PCICLK clocks at logic 0 level, when input low (In mobile mode, MODE=0) Ground Crystal input, has internal load cap (36pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Supply for PCICLK_F and PCICLK nominal 3.3V Indicates whether VDDLCPU is 2.5 or 3.3V. High=2.5V CPU, LOW=3.3V CPU. Latched Input. Free running PCI clock not affected by PCI_STOP# for power management. Frequency select pin. Latched Input. X2 VDDPCI C P U 2 . 5 _ 3 . 3 # 1,2 PCICLK_F FS31,2 OUT PWR IN OUT IN PCICLK0 OUT PCI clock output. Synchronous to CPU clocks with 1-4ns skew (CPU early) SEL24_48#1,2 PCICLK1 IN OUT Selects either 24 or 48MHz when Low =48 MHz PCI clock output. Synchronous to CPU clocks with 1-4ns skew (CPU early) SELPCIE_6#1,2 IN PCICLK2 OUT PCI Early or normal PCI select latch input. (for pin 18 power-up default is "High" early PCICLK.) PCICLK clock output. PCICLK (5:3) OUT PCI clock outputs. Synchronous to CPU clocks with 1-4ns skew (CPU early) 15 18 19 BUFFER IN PCICLK6/PCICLK_E VDDCOR IN OUT PWR 21 PD#1 22 28, 29, 31, 32, 34, 35, 37, 38 30, 36 23 24 25 26 27 39 41 42, 43, 45 46 47 48 GND48 PWR Input to Fanout Buffers for SDRAM outputs. PCI clock output or early PCI clock output selectable by SELPCIE_6# Power pin for the PLL core. 3.3V Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 4ms. Ground pin for the 24 & 48MHz output buffers & fixed PLL core. SDRAM (7:0) OUT SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset). VDDSDR SDATA SCLK 24_48MHz FS11, 2 48MHz FS01, 2 VDD48 SDRAM_F CLK_STOP# CPUCLK (2:0) CPUCLK_F VDDLCPU REF1 FS21, 2 PWR IN IN OUT IN OUT IN PWR OUT IN OUT OUT PWR OUT IN Supply for SDRAM and CPU PLL Core, nominal 3.3V. Data input for I2C serial input, 5V tolerant input Clock input of I2C input, 5V tolerant input 24MHz or 48MHz output clock selectable by pin 10 Frequency select pin. Latched Input. 48MHz output clock Frequency select pin. Latched Input Power for 24 & 48MHz output buffers and fixed PLL core. Free running SDRAM clock output. Not affected by CPU_STOP# This asynchronous input halts CPUCLK, & SDRAM at logic "0" level when driven low. CPU clock outputs, powered by VDDLCPU Free running CPU clock. Not affected by the CPU_STOP# Supply for CPU clocks 2.5V 14.318 MHz reference clock. Frequency select pin. Latched Input IN Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low. 2 ICS9248-143 General Description The ICS9248-143 is the single chip clock solution for Notebook designs using thE 440BX, MX, VIA Apollo Pro 133, Apollo Pro Media or MVP4 style chip set. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-143 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = 0) Bit Bit 7 Bit [2, 6:4] Bit 3 Bit 1 Bit 0 Description 0 - ±0.25% Spread Spectrum Modulation, Center Spread 1 - 0 to -0.5% Down Spread CPUCLK PCICLK Bit [2, 6:4] (MHz) (MHz) 0000 66.67 33.33 0001 100.00 33.33 0010 100.30 33.43 0011 133.33 33.33 0100 105.00 35.00 0101 133.37 33.34 0110 137.00 34.25 0111 75.00 37.50 1000 100.00 33.33 1001 95.00 31.67 1010 97.00 32.33 1011 133.33 33.33 1100 90.00 30.00 1101 96.22 32.07 1110 66.82 33.41 1111 91.50 30.50 0 - Frequency and Spread Spectrum are selected by hardware select, latched inputs 1 - Frequency is selected by Bit [2, 6:4]; Spread Spectrum is selected by bit 1 0 - Normal 1 - Spread Spectrum Enabled 0 - Running 1- Tristate all outputs PWD 1 Note1 0 1 0 Notes: 1, Default at Power-up will be for latched logic inputs to define frequency. Bit [2, 6:4] are default to 0011. 2, PWD = Power-Up Default 3 ICS9248-143 Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 46 39 42 43 45 PWD 1 1 1 1 1 1 1 1 Description (Reserved) CPUCLK_F (Act/Inact) (Reserved) (Reserved) SDRAM_F (Act/Inact) CPUCLK2 (Act/Inact) CPUCLK1 (Act/Inact) CPUCLK0 (Act/Inact) Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 7 18 17 13 12 11 10 8 PWD 1 1 1 1 1 1 1 1 Description PCICLK_F (Act/Inact) PCICLK6 (Act/Inact) PCICLK5 (Act/Inact) PCICLK4 (Act/Inact) PCICLK3 (Act/Inact) PCICLK2 (Act/Inact) PCICLK1 (Act/Inact) PCICLK0 (Act/Inact) Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 28 29 31 32 PWD 1 1 1 1 1 1 1 1 Description (Reserved) (Reserved) (Reserved) (Reserved) SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions. 4 ICS9248-143 Byte 4: Reserved Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # - PWD 1 1 X 1 X 1 X 1 Description (Reserved) (Reserved) (SEL24_48)# (Reserved) Latched FS1# (Reserved) Latched FS3# (Reserved) Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 34 35 37 38 26 25 48 2 PWD 1 1 1 1 1 1 1 1 Description SDRAM3 (Act/Inact) SDRAM2 (Act/Inact) SDRAM1 (Act/Inact) SDRAM0 (Act/Inact) 48MHz (Act/Inact) 24MHz (Act/Inact) REF1 (Act/Inact) REF0 (Act/Inact) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions. 5 ICS9248-143 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 5.5 V GND 0.5 V to VDD +0.5 V 0°C to +70°C 115°C 65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characte ristics - Input/Supply/Com m on Output Param ete rs T A = 0 - 70C; Supply Voltage VD D = VD D L = 3.3 V +/-5% (unles s otherwis e s tated) PA RA M ETER Input High Voltage Input Low Voltage SYM BOL VIH VIL CONDITIONS IDD3.3 OP Powerdown Current Input Frequency ID D P D Fi CL = 0 pF; Input address VDD or GND VD D = 3.3 V CIN CIN X Logic Inputs X1 & X2 pins T STA B From VD D = 3.3 V to 1% target Freq. Clk Stabilization Skew 1 1 1 1 t CP U -P CI1 MAX VD D +0.3 0.8 150 170 180 UNITS V V 12 600 16 µA M Hz 27 5 45 pF pF 5.5 ms 4 ns C L = 0 pF; Select @ 66M Hz C L = 0 pF; Select @ 100M Hz C L = 0 pF; Select @ 133M Hz Operating Supply Current Input Capacitance M IN 2 VSS -0.3 VT = 1.5 V TYP 90 114 139 1 mA Guaranteed by des ign, not 100% tes ted in production. Ele ctrical Characte ristics - Input/Supply /Com m on Output Param e te rs T A = 0 - 70º C; Supply Voltage VD D = 3.3 V +/-5%, VD D L = 2.5 V +/-5% (unles s otherwis e s tated) PA RA M ETER SYMBOL Operating SupplyCurrent ID D L 2 .5 Powerdown Current ID D L P D Skew 1 1 t CP U -P CI2 CONDITIONS CL = 0 pF; Select @ 66.8 M Hz CL = 0 pF; Select @ 100 M Hz CL = 0 pF; Select @ 133 M Hz M IN TYP 10 13 22 CL = 0 pF; Input address VDD or GN D VT = 1.5 V; VTL = 1.25 V Guaranteed by des ign, not 100% tes ted in production. 6 1 3 MAX 15 18 25 10 UNITS 4 ns mA µA ICS9248-143 Electrical Characteristics - CPU T A = 0 - 70C; VD D = 3.3 V +/-5%; CL = 20 pF PA RA M ETER Output High Voltage Output Low Voltage Output High Current Output Low Current Ris e Time Fall Time 1 1 Duty Cycle 1 Skew window 1 Jitter, Cycle-to-cycle 1 1 SYM BOL VO H 2 A VO L 2 A IO H 2 A IO L 2 A CONDITIONS IO H = -20 mA IO L = 12 mA VO H = 2.0 V VO L = 0.8 V M IN 2.4 22 TYP 2.85 0.31 -45 29 M A X UNITS V 0.4 V -27 mA mA t r2 A VO L = 0.4 V, VO H = 2.4 V 1.5 2 ns 1.4 2 ns 52.4 55 % t f2 A VO H = 2.4 V, VO L = 0.4 V d t2 A VT = 1.5 V t sk 2 A VT = 1.5 V 80 175 ps t jcy c-cy c2 A VT = 1.5 V 200 250 ps 45 Guaranteed by des ign, not 100% tes ted in production. Electrical Characteristics - CPU T A = 0 - 70C; VD D L = 2.5 V +/-5%; CL = 20 pF PA RA M ETER Output High Voltage Output Low Voltage Output High Current Output Low Current Ris e Time Fall Time 1 1 Duty Cycle 1 Skew window 1 1 CONDITIONS IO H = -12 mA IO L = 12 mA VO H = 1.7 V VO L = 0.7 V M IN 2 TYP 22 t r2 B VO L = 0.4 V, VO H = 2.0 V t f2 B VO H = 2.0 V, VO L = 0.4 V VT = 1.25 V, < 133 M Hz VT = 1.25 V, >= 133 M Hz d t2B Jitter, Cycle-to-cycle 1 SYM BOL VO H 2 B VO L 2 B IO H 2 B IO L 2 B 45 42 M A X UNITS V 0.4 V -21 mA mA 1.39 1.8 ns 1.47 47.9 45.8 1.8 55 52 ns % t sk 2 B VT = 1.25 V 85 175 ps t jcyc-cy c2 B VT = 1.25 V 183 300 ps Guaranteed by des ign, not 100% tes ted in production. 7 ICS9248-143 Electrical Characteristics - PCI T A = 0 - 70C; VD D = VD D L = 3.3 V +/-5%; CL = 30 pF PA RA M ETER Output High Voltage Output Low Voltage Output High Current Output Low Current Ris e Time Fall Time 1 1 Duty Cycle 1 Skew window Skew window 1 1 Jitter, A bs olute 1 1 SYM BOL VO H 1 VO L 1 IO H 1 IO L 1 CONDITIONS IO H = -18 mA IO L = 9.4 mA VO H = 2.0 V VO L = 0.8 V M IN 2.4 TYP 38 M A X UNITS V 0.4 V -33 mA mA t r1 VO L = 0.4 V, VO H = 2.4 V 1.56 2.2 ns t f1 VO H = 2.4 V, VO L = 0.4 V 1.74 2.2 ns d t1 VT = 1.5 V 50.3 55 % t sk 1 VT = 1.5 V 357 500 ps t sk 2 VT = 1.5 V PCICLKE to PCI [5:0] 2 2.77 4 ns t jab s1 VT = 1.5 V -250 143 250 ps M IN 2.4 TYP 45 Guaranteed by des ign, not 100% tes ted in production. Electrical Characteristics - SDRAM T A = 0 - 70C; VD D = VD D L = 3.3 V +/-5%; CL = 30 pF PA RA M ETER Output High Voltage Output Low Voltage Output High Current Output Low Current CONDITIONS IO H = -28 mA IO L = 19 mA VO H = 2.0 V VO L = 0.8 V 32 M A X UNITS V 0.4 V -46 mA mA 1 T r3 VO L = 0.4 V, VO H = 2.4 V 1.22 1.6 ns 1 T f3 VO H = 2.4 V, VO L = 0.4 V 1.25 1.6 ns Dt3 VT = 1.5 V 45.6 52 % T sk 3 VT = 1.5 V 169 250 ps T sk 3 VT = 1.5 V 3.3 5 ns Ris e Time Fall Time SYM BOL VO H 3 VO L 3 IO H 3 IO L 3 Duty Cycle 1 Skew window 1 42 1 Propagation Time (Buffer In to output) 1 Guaranteed by des ign, not 100% tes ted in production. 8 ICS9248-143 Electrical Characteristics - 24,48M Hz, REF(1:0) T A = 0 - 70C; VD D = VD D L = 3.3 V +/-5%; CL = 10 - 20 pF (unles s otherwis e s tated) PA RA M ETER Output High Voltage Output Low Voltage Output High Current Output Low Current Ris e Time Fall Time 1 1 Duty Cycle 1 Jitter, A bs olute 1 1 SYM BOL VO H 5 VO L 5 IO H 5 IO L 5 CONDITIONS IO H = -14 mA IO L = 6 mA VO H = 2.0 V VO L = 0.8 V M IN 2.4 TYP 16 M A X UNITS V 0.4 V -20 mA mA t r5 VO L = 0.4 V, VO H = 2.4 V 2.1 4 ns t f5 VO H = 2.4 V, VO L = 0.4 V 2.31 4 ns d t5 VT = 1.5 V 45 51.5 55 % t jab s5 VT = 1.5 V -600 368 600 ps Guaranteed by des ign, not 100% tes ted in production. 9 ICS9248-143 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ACK ACK Byte Count Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Stop Bit Notes: 1. 2. 3. 4. 5. 6. ICS (Slave/Receiver) The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 10 ICS9248-143 Shared Pin Operation Input/Output Pins Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. The I/O pins designated by (input/output) on the ICS9248143 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Via to VDD Programming Header 2K Via to Gnd Device Pad 8.2K Clock trace to load Series Term. Res. Fig. 1 11 ICS9248-143 CLK_STOP# Timing Diagram CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CLK_STOP# is synchronized by the ICS9248-143. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks. INTERNAL CPUCLK PCICLK CLK_STOP# PCI_STOP# (High) SDRAM CPUCLK CPUCLK _F SDRAM_F Notes: 1. All timing is referenced to the internal CPU clock. 2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9248-143. 3. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-143 CLK_STOP# signal. SDRAM are controlled as shown. 4. All other clocks continue to run undisturbed. 12 ICS9248-143 PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 4 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CLK_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. PD# CPUCLK PCICLK VCO Crystal Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz. 13 ICS9248-143 PCI_STOP# Timing Diagram PCI_STOP# is an asynchronous input to the ICS9248-143. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-143 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only three rising PCICLK clocks, off latency is one PCICLK clock. CPUCLK (Internal) PCICLK_F (Internal) PCICLK_F (Free-running) CLK_STOP# PCI_STOP# PCICLK Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248. 3. All other clocks continue to run undisturbed. 4. CLK_STOP# is shown in a high (true) state. 14 ICS9248-143 SY MBOL In Millimeters COMMON DIMENSIONS MIN MA X In Inc hes COMMON DIMENSIONS MIN MA X A 2.413 2.794 .095 A1 0.203 0.406 .008 .016 b 0.203 0.343 .008 .0135 c 0.127 0.254 SEE V A RIA TIONS D .110 .005 .010 SEE V A RIA TIONS E 10.033 10.668 .395 .420 E1 7.391 7.595 .291 .299 e 0.635 BA SIC h 0.381 L 0.508 1.016 SEE V A RIA TIONS N α 0.025 BA SIC 0.635 0° .015 .025 .020 .040 SEE V A RIA TIONS 8° 0° 8° MA X MIN MA X V A RIA TIONS D mm. N MIN D (inc h) 28 9.398 9.652 .370 .380 34 11.303 11.557 .445 .455 48 15.748 16.002 .620 .630 56 18.288 18.542 .720 .730 64 20.828 21.082 .820 .830 J EDE C MO- 118 6/1/00 DOC# 10- 0034 R E VB Ordering Information ICS9248yF-143-T Example: ICS XXXX y F - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 15 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-143 SYMBOL In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A - 1.20 - .047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 SEE VARIATIONS D .0035 .008 SEE VARIATIONS 8.10 BASIC E E1 6.00 e 0.319 6.20 .236 0.50 BASIC L 0.45 0.75 SEE VARIATIONS N .244 0.020 BASIC .018 .30 SEE VARIATIONS α 0° 8° 0° 8° aaa - 0.10 - .004 MIN MAX MIN 28 7.70 7.90 .303 .311 36 9.60 9.80 .378 .386 40 10.90 11.10 .429 .437 44 10.90 11.10 .429 .437 48 12.40 12.60 .488 .496 VARIATIONS D mm. N 6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil) D (inch) MAX 56 13.90 14.10 .547 .555 64 16.90 17.10 .665 .673 MO-153 JEDEC Doc.# 10-0039 7/6/00 Rev B Ordering Information ICS9248yG-143-T Example: ICS XXXX y G - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G=TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 16 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.