ICS ICS9148F-58

Integrated
Circuit
Systems, Inc.
ICS9148-58
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
The ICS9148-58 is the single chip clock solution for Desktop/
Notebook designs using the VIA MVP3 style chipset. It
provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9148-58
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
2
Serial programming I C interface allows changing functions,
stop clock programming and frequency selection. The SD_SEL
latched input allows the SDRAM frequency to follow the
CPUCLK frequency(SD_SEL=1) or the AGP clock
frequency(SD_SEL=0)
Block Diagram
Features
•
Generates the following system clocks:
- 4 CPU(2.5V/3.3V) upto 100MHz.
- 6 PCI(3.3V) @ 33.3MHz
- 2AGP(3.3V) @ 2 x PCI
- 12 SDRAMs(3.3V) @ either CPU or AGP
- 2 REF (3.3V) @ 14.318MHz
•
Skew characteristics:
- CPU – CPU<250ps
- SDRAM – SDRAM < 250ps
- CPU – SDRAM < 250ps
- CPU(early) – PCI : 1-4ns
•
Spread Spectrum 0 to -5% down spread.
•
Serial I2C interface for Power Management, Frequency
Select, Spread Spectrum.
•
Efficient Power management scheme through PCI and CPU
STOP CLOCKS.
•
Uses external 14.318MHz crystal
•
48 pin 300mil SSOP.
Pin Configuration
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:11), supply for PLL core,
24 MHz, 48MHz
VDD4 = AGP (0:1)
VDDL = CPUCLK (0:3)
9148-58 Rev C 12/07/98
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9148-58
Pin Descriptions
PIN NUMBER
1
2
3,9,16,22,27,
33,39,45
PIN NAME
VDD1
REF0
TYPE
PWR
OUT
CPU3.3#_2.5 1,2
IN
GND
PWR
4
X1
IN
5
X2
OUT
VDD2
PWR
PCICLK_F
OUT
6,14
7
FS11, 2
8
10, 11, 12, 13
15, 47
IN
PCICLK0
OUT
1, 2
IN
FS2
PCICLK(1:4)
AGP (0:1)
OUT
OUT
CPU_STOP#1
IN
17
SDRAM 11
OUT
PCI_STOP#1
IN
SDRAM 10
OUT
SDRAM (0:9)
OUT
19,30,36
VDD3
PWR
23
24
SDATA
SCLK
24MHz
IN
IN
OUT
18
20, 21,28, 29, 31,
32, 34, 35,37,38
25
MODE1, 2
48MHz
26
40, 41, 43, 44
42
46
48
FS0
1, 2
CPUCLK(0:3)
VDDL
REF1
SD_SEL
VDD4
IN
OUT
IN
OUT
PWR
OUT
IN
PWR
DESCRIPTION
Ref (0:2), XTAL power supply, nominal 3.3V
14.318 MHz reference clock.
Indicates whether VDDL2 is 3.3V or 2.5V. High=2.5V CPU, LOW=3.3V
CPU1. Latched input2
Ground
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V
Free running PCI clock output. Synchrounous with CPUCLKs with 1-4ns
skew (CPU early) This is not affected by PCI_STOP#
Frequency select pin. Latched Input. Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frequencies.
PCI clock output. Synchrounous CPUCLKs with 1-4ns skew (CPU early)
Frequency select pin. Latched Input Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frequencies.
PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early)
Advanced Graphic Port outputs, powered by VDD4.
This asyncheronous input halts CPUCLK (0:3) and AGP (0:1) clocks at
logic 0 level, when input low (in Mobile Mode, MODE=0)
SDRAM clock output. Frequency is selected by the SD_SEL latched input.
SD_SEL = 1 at power on causes SDRAM frequency = CPU frenquencies
SD_SEL = 0 at power on causes SDRAM frequencies = AGP frequencies
This asyncheronous input halts PCICLK(0:5) clocks at logic 0 level, when
input low (In mobile mode, MODE=0)
SDRAM clock output. Frequency is selected by the SD_SEL latched input.
SD_SEL = 1 at power on causes SDRAM frequency = CPU frenquencies
SD_SEL = 0 at power on causes SDRAM frequencies = AGP frequencies
SDRAM clock outputs. Frequency is selected by the SD_SEL latched input.
SD_SEL = 1 at power on causes SDRAM frequency = CPU frenquencies
SD_SEL = 0 at power on causes SDRAM frequencies = AGP frequencies
Supply for SDRAM (0:11), CPU Core and 24, 48MHz clocks,
nominal 3.3V.
Data input for I2C serial input.
Clock input of I2C input
24MHz output clock, for Super I/O timing.
Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile Mode.
Latched Input.
48MHz output clock, for USB timing.
Frequency select pin. Latched Input Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frequencies.
CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low
Supply for CPU (0:3), either 2.5V or 3.3V nominal
14.318MHz reference clock.
Latched input at Power On selects either CPU (SDSEL=1) or AGP
(SD_SEL=0) frequencies for the SDRAM clock outputs.
Supply for AGP (0:1)
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
2
ICS9148-58
Mode Pin - Power Management Input Control
MODE, Pin 25
(Latched Input)
0
1
Pin 17
Pin 18
CPU_STOP#
(INPUT)
SDRAM 11
(OUTPUT)
PCI_STOP#
(INPUT)
SDRAM 10
(OUTPUT)
Power Management Functionality
PCICLK
(0:5)
PCICLK_F,
REF,
24/48MHz
and SDRAM
Crystal
OSC
VCO
CPU_STOP#
PCI_STOP#
AGP,
CPUCLK
Outputs
0
1
Stopped Low
Running
Running
Running
Running
1
1
Running
Running
Running
Running
Running
1
0
Running
Stopped Low
Running
Running
Running
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
CPU3.3#_2.5
Input level
(Latched Data)
1
0
Buffer Selected for
operation at:
2.5V VDD
3.3V VDD
Functionality
VDD1, 2, 3, 4 = 3.3V±5%, VDDL = 2.5V ±5% or 3.3 ±5%, TA= 0 to 70°C
Crystal (X1, X2) = 14.31818MHz
FS2
FS1
FS0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
CPU
(M H z)
1 0 0 .2
9 5 .2 5
8 3 .3
1 3 3 .3
75
124
6 6 .8
11 2
S D R A M (M H z)
S D _ S EL= 1
S D _ S EL= 0
1 0 0 .2
66.6
9 5 .2 5
63.5
8 3 .3
66.6
1 3 3 .3
88.7
75
75
124
82.7
6 6 .8
66.8
11 2
74.7
3
P C I (M H z)
A G P (M H z)
33.3
31.75
33.3
44.3
37.5
41.3
33.4
37.3
6 6 .6
6 3 .5
6 6 .6
8 8 .7
75
8 2 .7
6 6 .8
7 4 .7
ICS9148-58
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C
programming application note.
How to Write:
•
•
Send the address D2(H) .
Send two additional dummy bytes, a command code
and byte count.
• Send the desired number of data bytes.
See the diagram below:
Clock Generator
Address (7 bits)
A(6:0) & R/W#
D2(H)
ACK
+ 8 bits
dummy
command code
ACK
+ 8 bits
dummy Byte
count
ACK
Data Byte
1
ACK
Data Byte
N
ACK
Note that the acknowledge bit is sent by the clock chip, and pulls the data line low. There is no minimum of data bytes that must
be sent.
How to Read:
•
•
•
Send the address D3(H).
Send the byte count in binary coded decimal
Read back the desired number of data bytes
See the diagram below:
Clock Generator
Address (7 bits)
A(6:0) & R/W# ACK
D3 (H)
Byte
Count
ACK
Data Byte
1
The following specifications should be observed:
1. Operating voltage for I2C pins is 3.3V
2. Maximum data transfer rate (SCLK) is 100K bits/sec.
Note 1. Default at Power-up will be for latched logic inputs
to define frequency. Bits 4, 5, 6 are default to 000,
and if bit 3 is written to a 1 to use Bits 6:4, then
these should be defined to desired frequency at same
write cycle.
Note: PWD = Power-Up Default
2
I C is a trademark of Philips Corporation
ACK
Data Byte
N
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register
(default = 0)
Bit
Description
Bit 7 Reserved
AGP
PCI
CPU Clock
Bit6 Bit5
Bit4
66.6
33.3
100.2
111
63.5
31.75
95.25
110
66.6
33.3
83.3
101
Bit
88.7
44.3
133.3
100
6:4
75
37.5
75
011
82.7
41.3
124
010
66.8
33.4
66.8
001
74.7
37.3
112
000
0 - Frequency is selected by hardware select,
Bit 3
Latched Inputs
1 - Frequency is selected by Bit 6:4 (above)
Spread Spectrum center spread type. ±.25%
Bit 2 10 -- Spread
Spectrum down spread type. 0 to -.5%
0
Normal
Bit 1 1 - Spread Spectrum Enabled
0 - Running
Bit 0 1Tristate all outputs
4
PWD
0
Note
1
0
0
0
0
ICS9148-58
Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
40
41
43
44
PWD
1
1
1
1
1
1
1
1
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
CPUCLK3 (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Pin #
7
15
14
12
11
10
8
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
PCICLK_F (Act/Inact)
AGP0 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0(Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 3: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
28
29
31
32
34
35
37
38
PWD
1
1
1
1
1
1
1
1
Description
SDRAM7 (Act/Inact)
SDRAM6 (Act/Inact)
SDRAM5 (Act/Inact)
SDRAM4 (Act/Inact)
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Pin #
47
46
2
PWD
1
1
1
1
1
1
1
1
Pin #
-
PWD
1
1
1
1
Bit 3
17
1
Bit 2
18
1
Bit 1
Bit 0
20
21
1
1
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
SDRAM11 (Act/Inact)
(Desktop Mode Only)
SDRAM10 (Act/Inact)
(Desktop Mode Only)
SDRAM9 (Act/Inact)
SDRAM8 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Description
(Reserved)
(Reserved)
(Reserved)
AGP1(Act/Inact)
(Reserved)
(Reserved)
REF1 (Act/Inact)
REF0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
5
ICS9148-58
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9148-58. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9148-58.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
6
ICS9148-58
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-58. It is used to turn off the PCICLK (0:5) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9148-58 internally. The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
7
ICS9148-58
Shared Pin Operation Input/Output Pins
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
Pins 1 and 2 on the ICS9148-58 serve as dual signal functions
to the device. During initial power-up, they act as input pins.
The logic level (voltage) that is present on these pins at this
time is read and stored into a 4-bit internal data latch. At the
end of Power-On reset, (see AC characteristics for timing
values), the device changes the mode of operations for these
pins to an output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figs. 1 and 2 show the recommended means of implementing
this function. In Fig. 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the device’s
internal logic. Figs. 2a and b provide a single resistor loading
option where either solder spot tabs or a physical jumper
header may be used.
Fig. 1
8
ICS9148-58
Fig. 2a
Fig. 2b
9
ICS9148-58
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
Supply Current
Input frequency
Input Capacitance1
Transition Time
Settling Time
1
1
Clk Stabilization
Skew1
1
1
SYMBOL
CONDITIONS
VIH
VIL
VIN = VDD
IIH
VIN = 0 V; Inputs with no pull-up resistors
IIL1
VIN = 0 V; Inputs with pull-up resistors
IIL2
CL = 0 pF; 66.8 MHz
IDD3.3OP
CL = 0 pF; 133 MHz
VDD = 3.3 V;
Fi
Logic Inputs
CIN
X1 & X2 pins
CINX
MIN
2
VSS-0.3
TYP
12
0.1
2.0
-100
100
200
14.318
27
36
-5
-200
MAX UNITS
VDD+0.3
V
0.8
V
µA
5
µA
µA
160
320
16
5
45
MHz
pF
pF
To 1st crossing of target Freq.
3
ms
Ts
From 1st crossing to 1% target Freq.
2
ms
TSTAB
TCPU-PCI
From VDD = 3.3 V to 1% target Freq.
VT = 1.5 V; CPU leads
VT = 1.5 V; Window
3
4
250
ms
ns
ps
Ttrans
TCPU-SDRAM
1
3
100
mA
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Operating
Supply Current
Skew1
1
SYMBOL
IDD2.5OP
TCPU-PCI
TCPU-SDRAM
CONDITIONS
CL = 0 pF; 66.8 MHz
CL = 0 pF;133 MHz
VT = 1.5 V; CPU leads
VT = 1.5 V; Window
Guaranteed by design, not 100% tested in production.
10
MIN
1
TYP
10
20
3
100
MAX
20
40
4
250
UNITS
mA
ns
ps
ICS9148-58
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
SYMBOL
VOH2A
VOL2A
IOH2A
IOL2A
Rise Time
tr2A1
tf2A1
dt2A1
tsk2A1
tj1s2A1
tjabs2A1
Fall Time
Duty Cycle
Skew
Jitter, One Sigma
Jitter, Absolute
1
CONDITIONS
IOH = -28 mA
IOL = 27 mA
VOH = 2.0 V
VOL = 0.8 V
MIN
2.5
TYP
2.6
0.35
-29
37
33
MAX UNITS
V
0.4
V
-23
mA
mA
VOL = 0.4 V, VOH = 2.4 V
1.75
2
ns
VOH = 2.4 V, VOL = 0.4 V
1.1
2
ns
50
55
%
VT = 1.5 V
50
250
ps
VT = 1.5 V
VT = 1.5 V
65
150
ps
165
250
ps
VT = 1.5 V
45
-250
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU
T A = 0 - 70C; VDD = 3.3 V +/-5%, V DDL = 2.5 V +/-5%; C L = 10 - 20 pF (unless otherwise stated)
PARAM ETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
2
1
CONDITIONS
TYP
2.2
0.3
-20
26
M AX
VOL = 0.4 V, VOH = 2.0 V
1.5
1.8
ns
VOH = 2.0 V, VOL = 0.4 V
1.6
1.8
ns
IOH = -8 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
M IN
2
19
0.4
-16
UNITS
V
V
mA
mA
Fall Time
tf2B
Duty Cycle
dt2B 1
VT = 1.25 V
47
55
%
Skew
Jitter, Single Edge
Displacement 2
Jitter, One Sigma
tsk2B 1
VT = 1.25 V
60
250
ps
tjsed2B 1
VT = 1.25 V
200
250
ps
tj1s2B 1
tjabs2B 1
VT = 1.25 V
VT = 1.25 V
65
150
ps
160
300
ps
Jitter, Absolute
1
SYM BOL
VOH2B
VOL2B
IOH2B
IOL2B
tr2B 1
40
-300
Guaranteed by design, not 100% tested in production.
Edge displacement of a period relative to a 10-clock-cycle rolling average period.
11
ICS9148-58
Electrical Characteristics - PCI
T A = 0 - 70C; V DD = VDDL = 3.3 V +/-10%; C L = 30 pF (unless otherwise stated)
PARAM ETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
CONDITIONS
IOH = -28 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
t r1
VOL = 0.4 V, VOH = 2.4 V
Fall Time
t f1
1
VOH = 2.4 V, VOL = 0.4 V
Duty Cycle
d t1 1
VT = 1.5 V
ts k 1 1
Skew
Jitter, One Sigma
Jitter, A bs olute
1
1
M IN
2.4
41
1
Rise Time
1
SYM BOL
VOH1
VOL1
IOH1
IOL1
TYP
3
0.2
-60
50
M AX
1.8
2
0.4
-40
UNITS
V
V
mA
mA
ns
1.6
2
ns
51
55
%
VT = 1.5 V
130
250
ps
t j1 s1 a
t j1 s1 b
VT = 1.5 V, s ynchronous
VT = 1.5 V, as ynchronous
40
200
150
250
ps
ps
tab s1 a
t jab s1 b
VT = 1.5 V, s ynchronous
VT = 1.5 V, as ynchronous
-250
-650
135
500
250
650
ps
ps
M IN
2.4
TYP
3
0.2
-60
50
M A X UNITS
V
0.4
V
-40
mA
mA
45
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
T A = 0 - 70C; VD D = VD D L = 3.3 V +/-5%; CL = 30 pF
PA RA M ETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Ris e Time
Fall Time
1
1
Duty Cycle
Skew
1
1
Jitter, One Sigma
Jitter, A bs olute
Jitter, A bs olute
1
1
1
1
SYM BOL
VO H 1
VO L 1
IO H 1
IO L 1
CONDITIONS
IO H = -28 mA
IO L = 23 mA
VO H = 2.0 V
VO L = 0.8 V
41
T r1
VO L = 0.4 V, VO H = 2.4 V
1.75
2
ns
T f1
VO H = 2.4 V, VO L = 0.4 V
1.5
2
ns
Dt1
VT = 1.5 V
50
55
%
T sk 1
VT = 1.5 V
200
500
ps
T j1 s1
VT = 1.5 V
50
150
ps
T jab s1
VT = 1.5 V (with s ynchronous PCI)
-250
+250
ps
T jab s1
VT = 1.5 V (with as ynchronous PCI)
-400
400
ps
45
Guaranteed by des ign, not 100% tes ted in production.
12
ICS9148-58
Electrical Characteristics - AGP
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
IOH = -28 mA
Output High Voltage
VOH1
IOL = 23 mA
Output Low Voltage
VOL1
Output High Current
IOH1
VOH = 2.0 V
Output Low Current
IOL1
VOL = 0.8 V
1
Rise Time
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
Fall Time
tf11
1
VT = 1.4 V
Duty Cycle
dt1
1
Skew
tsk1
VT = 1.5 V
1
Jitter, One Sigma
tj1s1
Jitter, Absolute1
tabs1a
tjabs1b
MIN
2.4
41
45
VT = 1.5 V
VT = 1.5 V, synchronous
VT = 1.5 V, asynchronous
TYP
3
0.2
-60
50
1.1
1
49
130
MAX UNITS
V
0.4
V
-40
mA
mA
2
ns
2
ns
55
%
250
ps
2
3
%
-5
-6
2.5
4.5
5
6
%
%
MIN
2.4
TYP
2.6
0.3
-32
25
2
1.9
54
1
-
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz, 48MHz, REF0
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 10 -20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
IOH = -16 mA
Output High Voltage
VOH5
IOL = 9 mA
Output Low Voltage
VOL5
VOH = 2.0 V
Output High Current
IOH5
VOL = 0.8 V
Output Low Current
IOL5
1
VOL = 0.4 V, VOH = 2.4 V
Rise Time
tr5
1
VOH = 2.4 V, VOL = 0.4 V
Fall Time
tf5
VT = 1.5 V
Duty Cycle
dt51
1
VT = 1.5 V
Jitter, One Sigma
tj1s5
1
VT = 1.5 V
t
Jitter, Absolute
jabs5
1
Guaranteed by design, not 100% tested in production.
13
16
45
-5
MAX UNITS
V
0.4
V
-22
mA
mA
4
ns
4
ns
57
%
3
%
5
%
ICS9148-58
SSOP Package
SYMBOL
A
A1
A2
B
C
D
E
e
H
h
L
N
∝
X
COMMON DIMENSIONS
MIN.
NOM.
MAX.
.095
.101
.110
.008
.012
.016
.088
.090
.092
.008
.010
.0135
.005
.010
See Variations
.292
.296
.299
0.025 BSC
.400
.406
.410
.010
.013
.016
.024
.032
.040
See Variations
0°
5°
8°
.085
.093
.100
VARIATIONS
AC
MIN.
.620
D
NOM.
.625
N
MAX.
.630
48
Ordering Information
ICS9148F-58
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
14
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.