ICS9159C-14 Integrated Circuit Systems, Inc. Frequency Generator and Integrated Buffer for PENTIUM™ General Description Features The ICS9159C-14 generates all clocks required for high speed RISC or CISC microprocessor systems such as 486, Pentium, PowerPC, etc. Four different reference frequency multiply-ing factors are externally selectable with smooth frequency transitions. These multiplying factors can be customized for specific applications. It has a TURBO pin that can speed up the 60 and 66.6 MHz clocks by 2.5%. • Generates up to four processor and six bus clocks, plus disk, USB and reference clocks • Synchronous clocks skew matched to 250ps window on PCLKs and 500ps window on BCLKs • TURBO input pin that can speed up the 60 and 66.6 MHz PCLKs by 2.5%. High drive BCLK outputs provide typically greater than 1V/ ns slew rate into 30pF loads. PCLK outputs provide typically better than 1V/ns slew rate into 20pF loads while maintaining 50±5% duty cycle. • 2.5V or 3.3V output: PCLK (0:3) • 3.0V - 5.5V supply range • 28-pin SOIC package Block Diagram Pin Cnfiguration 28-Pin SOIC Functionality TURBO FS1 FS0 X1, REF (MHz) PCLK (MHz) 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 50 66.8 60 55 83.3 68.4 61.6 75 ICS9159C-14RevC062397P PCLK(0:3) BCLK(0:5) USB DISK VCO/2 PCLK/2 48 MHz 24 MHz All frequencies in MHz, assuming 14.318 MHz input. Pentium is a trademark of Intel Corporation. PowerPC is a trademark of Motorola Corporation. ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9159C-14 Pin Descriptions PIN NUMBER 1, 26 PIN NAME TYPE VDD PWR 2 X1 IN 3 X2 OUT 4, 11, 17, 23 VSS PWR 5 TURBO IN 6, 7, 9, 10 PCLK(0:3) OUT 8 VDD2 PWR 13, 12 FS(0:1) IN 14, 20 15, 16, 18 19, 21, 22 VDD PWR Ground Speeds up the 60 and 66.6 MHz by 2.5% (see functionality table). It has an internal pull-up resistor. Processor clock outputs which are a multiple of the input reference frequency as shown in the table above. Power for PCLK output buffers only. This V DD supply can be reduced to 2.5V for PCLK (0:3) outputs. Frequency multiplier select pins. See table above. These inputs have internal pull-up devices. Power for BCLK output buffers. BCLK(0:5) OUT Busclock outputs are fixed at one half the PCLK frequency. 24 DISK OUT 25 USB OUT 28, 27 REF(0:1) OUT The DISK controller clock is fixed at 24 MHz (with 14.318 MHZ input) The USB clock is fixed at 48 MHz (with 14.318 MHz input). REF is a buffered copy of the crystal oscillator or reference input clock, nominally 14.31818 MHz. DESCRIPTION Power for logic and fixed frequency output buffers. XTAL or external reference frequency input. This input includes XTAL load capacitance and feedback bias for a 12 - 16 MHz crystal, nominally 14.31818 MHz. XTAL output which includes XTAL load capacitance. 2 ICS9159C-14 Absolute Maximum Ratings Supply Voltage .......................................................................................................... 7.0 V Logic Inputs ....................................................................... GND –0.5 V to VDD +0.5 V Ambient Operating Temperature ............................................................. 0°C to +70°C Storage Temperature ........................................................................... –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics at 3.3V VDD = 3.0 – 3.7 V, TA = 0 – 70° C unless otherwise stated DC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Low Voltage VIL - - 0.2VDD V Input High Voltage VIH 0.7V DD - - V Input Low Current IIL VIN=0V -28.0 -10.5 - mA Input High Current IIH -5.0 - 5.0 mA Output Low Current 1 IOL 30.0 47.0 - Ma Output High Current 1 IOH - -66.0 -42.0 mA Output Low Current 1 IOL VIN=VDD VOL=0.8V; for PCLKs & BCLKs VOH=2.0V; for PCLKs & BCLKs VOL=0.8V; for fixed CLKs 25.0 38.0 - mA - -47.0 -30.0 mA - 0.3 0.4 V 2.4 2.8 - V - 0.3 0.4 V 2.4 2.8 - V - 55 110 mA Output High Current 1 IOH Output Low Voltage 1 VOL Output High Voltage 1 VOH Output Low Voltage 1 VOL 1 VOH Output High Voltage Supply Current IDD VOH=2.0V; for fixed CLKs IOL=15mA; for PCLKs & BCLKs IOH=-30mA; for PCLKs & BCLKs IOL=12.5mA; for fixed CLKs IOH=-20mA; for fixed CLKs @66.5 MHz; all outputs unloaded Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 3 ICS9159C-14 Electrical Characteristics at 3.3V VDD = 3.1 – 3.7 V, TA = 0 – 70° C PARAMETER Rise Time 1 Fall Time1 Rise Time1 Fall Time1 Duty Cycle1 Jitter, One Sigma1 Jitter, Absolute1 1 Jitter, One Sigma Jitter, Absolute1 Input Frequency1 Logic Input Capacitance 1 Crystal Oscillator Capacitance1 AC Characteristics SYMBOL TEST CONDITIONS 20pF load, 0.8 to 2.0V Tr1 PCLK & BCLK 20pF load, 2.0 to 0.8V Tf1 PCLK & BCLK 20pF load, 20% to 80% Tr2 PCLK & BCLK 20pF load, 80% to 20% Tf2 PCLK & BCLK Dt 20pF load @ VOUT=1.4V PCLK & BCLK; Tj1s1 Load=20pF. PCLK & BCLK; Tjab1 Load=20pF. Tj1s2 Fixed CLK; Load=20pF Tjab2 Fixed CLK; Load=20pF Fi CIN Logic input pins CINX Power-on Time1 ton Frequency Settling Time 1 ts Clock Skew Window 1 Clock Skew Window 1 Clock Skew Window 1 Tsk1 Tsk2 Tsk3 MIN TYP MAX UNITS - 0.9 1.5 ns - 0.8 1.4 ns - 1.5 2.5 ns - 1.4 2.4 ns 48 50 58 % - 50 150 ps -250 - 250 ps -5 12.0 - 1 2 14.318 5 3 5 16.0 - % % MHz pF X1, X2 pins - 18 - pF From VDD=1.6V to 1st crossing of 66.5 MHz VDD supply ramp < 40ms From 1st crossing of acquisition to < 1% settling PCLK to PCLK; Load=20pF; @1.4V BCLK to BCLK; Load=20pF; @1.4V PCLK to BCLK; Load=20pF; @1.4V - 2.5 4.5 ms - 2.0 4.0 ms 1 150 300 2.6 250 500 5 ps ps ns Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 4 ICS9159C-14 Electrical Characteristics at 5.0V VDD = 4.5 – 5.5 V, TA = 0 – 70° C DC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Low Voltage VIL - - 0.8 V Input High Voltage VIH 2.4 - - V Input Low Current IIL VIN=0V -45 -15 - µA Input High Current IIH -5.0 - 5.0 µA Output Low Current1 IOL 36.0 62.0 - mA Output High Current 1 IOH - -152 -90.0 mA Output Low Current1 IOL VIN=VDD VOL=0.8V; for PCLKs & BCLKs VOL=2.0V; for PCLKs & BCLKs VOL=0.8V; for fixed CLKs 30.0 50.0 - mA - -110.0 -65.0 mA - 0.25 0.4 V 2.4 4.0 - V - 0.2 0.4 V 2.4 4.7 - V - 80.0 160.0 mA Output High Current 1 IOH Output Low Voltage1 VOL Output High Voltage 1 VOH Output Low Voltage1 VOL Output High Voltage 1 VOH Supply Current IDD VOL=2.0V; for fixed CLKs IOL=20mA; for PCLKs & BCLKs IOH=-70mA; for PCLKs & BCLKs IOL=15mA; for fixed CLKs IOH=-50mA; for fixed CLKs @66.5 MHz; all outputs unloaded Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 5 ICS9159C-14 Electrical Characteristics at 5.5V VDD = 4.5 – 5.5 V, TA = 0 – 70° C PARAMETER Rise Time 1 Fall Time1 Rise Time1 Fall Time1 Duty Cycle1 Duty Cycle1 Jitter, One Sigma1 Jitter, Absolute1 Jitter, One Sigma1 Jitter, Absolute1 Input Frequency1 Logic Input Capacitance1 Crystal OscillatorCapacitance1 AC Characteristics SYMBOL TEST CONDITIONS 20pF load, 0.8 to 2.0V Tr1 PCLK & BCLK 20pF load, 2.0 to 0.8V Tf1 PCLK & BCLK 20pF load, 20% to 80% Tr2 PCLK & BCLK 20pF load, 80% to 20% Tf2 PCLK & BCLK Dt1 20pF load @ VOUT=1.4V Dt2 20pF load @ VOUT=50% PCLK & BCLK; Tj1s1 Load=20pF, Rs=33Ω PCLK & BCLK; Tjab1 Load=20pF, Rs=33Ω Tj1s2 REF CLKs; Load=20pF Rs=33 Ω Tjab2 REF CLKs; Load=20pF Rs=33 Ω Fi CIN Logic input pins CINX Power-on Time1 ton Frequency Settling Time1 ts Clock Skew Window 1 Tsk1 Clock Skew Window 1 Tsk2 Clock Skew Window 1 Tsk3 X1, X2 pins From VDD=1.6V to 1st crossing of 66.5 MHz VDD supply ramp < 40ms From 1st crossing of acquisition to < 1% settling PCLK to PCLK; Load=20pF; @1.4V BCLK to BCLK; Load=20pF; @1.4V PCLK & BCLK; Load=20pF; @1.4V MIN TYP MAX UNITS - 0.55 0.95 ns - 0.52 0.90 ns - 1.2 2.1 ns - 1.1 2.0 ns 50 45 57 50 60 55 % % - 50 150 ps -250 - 250 ps -5 12.0 - 1 2 14.318 5 3 5 16.0 - % % MHz pF - 18 - pF - 2.5 4.5 ms - 2.0 4.0 ms - 150 250 ps - 300 500 ps 1 2.6 5 ns Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 6 ICS9159C-14 LEAD COUNT 28L DIMENSIONL 0.704 SOIC Package Ordering Information ICS9159CM-14 Example: ICS XXXX M-PPP Pattern Number(2 or 3 digit number for parts with ROM code patterns) Package Type M=SOIC Device Type (consists of 3 or 4 digit numbers) Prefix ICS=Standard Device 7 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.