ICS9159-20 Integrated Circuit Systems, Inc. Frequency Generator for SIS551X and SIS6205 Chip Set Systems General Description The ICS9159-20 is a low-cost frequency generator designed specifically for SIS551X chip set and SIS6205 VGA controller. The integrated buffer minimizes skew. A 14.31818 MHz XTAL oscillator provides the reference clock to generate standard Pentium™ frequencies. The CPU clock makes gradual frequency transitions without violating the PLL timing of internal microprocessor clock multipliers. Both synchronous and asynchronous bus designs are supported. For chip sets that require an early CPU clock, the buffers are driven by the CPU clock. In this configuration, the CPU clock becomes the early clock and the output of the uncommitted buffers become the bus synchronized bus clocks. Features • One selectable CPU clocks operate up to 66.66 MHz • 5 uncommitted buffers • Maximum CPU jitter of ±200ps • 7 BUS clocks support sync or async bus operation • 500ps skew window for all synchronous clock edges • Integrated buffer outputs drive up to 30pF loads • 3.1V - 3.5V supply range • 28-pin 300-mil SOIC package • Supports chip sets requiring early CPU clocking Applications Block Diagram • Ideal for green Pentium and P6 PCI systems based on the SIS5596 chip set Pin Configuration 28-Pin SOIC Functionality 3.3V±10%, 0-70°C Crystal (X1, X2) = 14.318181 MHz FS1 FS0 REF (MHz) CPU (MHz) BCLK (MHz) BSEL=1 BSEL=0 0 0 1 1 0 1 0 1 Tistate 14.318 14.318 14.318 Tristate 50 60 66.66 Tristate 25 30 33.33 Tristate 33.33 33.33 33.33 All frequencies in MHz, assuming 14.318 MHz input. Pentium is a trademark of Intel Corporation. 9159-20 Rev B 040597 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9159-20 Pin Descriptions PIN NUMBER PIN NAME TYPE DESCRIPTION 1, 8, 20, 26 VDD PWR 2 X1 IN 3 X2 OUT XTAL output which includes XTAL load capacitance. 4, 11, 17, 23 GND PWR Ground for logic, PCLK and fixed frequency output buffers. 5 BSEL IN 6, 7, 9, 10, 24 BOUT(0:4) OUT 13, 12 FS(0:1) IN 15, 16, 18, 19, 21, 22, 27 BCLK(0:6) OUT 28 REF OUT Power for logic, PCLK and fixed frequency output buffers. XTAL or external reference frequency input. This input includes XTAL load capacitance and feedback bias for a 12 - 16 MHz crystal, nominally 14.31818 MHz. The DISK controller clock is fixed at 33 MHz (with 14.318 MHz input). Uncommitted clock buffer outputs. Frequency multiplier select pins. See table above. These inputs have internal pull-up devices. 14 BIN IN Uncommitted buffered inputs. Bus clock outputs are fixed at 33.3 MHz or one half the CPU frequency. 25 CPU OUT Processor clock outputs which are a multiple of the input reference frequency as shown in the table above. REF is a buffered copy of the crystal oscillator or reference input clock, nominally 14.31818 MHz. Note: BCLK buffers cannot be supplied with 5 volts (Pins 14 and 20) if CPU and fixed frequencies (Pins 1, 8 and 26) are being supplied with 3.3 volts. 2 ICS9159-20 Absolute Maximum Ratings Supply Voltage .......................................................................................................... 7.0 V Logic Inputs ....................................................................... GND –0.5 V to VDD +0.5 V Ambient Operating Temperature ............................................................. 0°C to +70°C Storage Temperature ........................................................................... –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics at 3.3V VDD = 3.0 – 3.7 V, TA = 0 – 70° C unless otherwise stated DC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Low Voltage VIL - - 0.2VDD V Input High Voltage VIH 0.7VDD - - V Input Low Current IIL VIN=0V -28.0 -10.5 - µA Input High Current IIH VIN=VDD -5.0 - 5.0 µA Output Low Current1 IOL 30.0 47.0 - mA Output High Current1 IOH - -66.0 -42.0 mA Output Low Current1 IOL VOL=0.8V; for REF CLKs 25.0 38.0 - mA 1 IOH VOH=2.0V; for REF CLKs - -47.0 -30.0 mA Output Low Voltage1 VOL IOL=15mA; for CPUs & BUSes - 0.3 0.4 V 1 VOH IOH=-30mA; for CPUs & BUSes 2.4 2.8 - V Output Low Voltage1 VOL IOL=12.5mA; for REF CLKS - 0.3 0.4 V 1 VOH IOH=-20mA; for REF CLKs 2.4 2.8 - V IDD @66.5 MHz; all outputs unloaded - 90 150 mA Output High Current Output High Voltage Output High Voltage Supply Current VOLT=0.8V; for CPU, BOUT & BUS VOH=2.0V; for CPU, BOUT & BUSes Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 3 ICS9159-20 Electrical Characteristics at 3.3V VDD = 3.1 – 3.7 V, TA = 0 – 70° C AC Characteristics PARAMETER 1 SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - 0.9 1.5 ns Rise Time Tr1 20pF load, 0.8 to 2.0V CPU, BOUT & BUS Fall Time1 Tf1 20pF load, 2.0 to 0.8V CPU, BOUT & BUS - 0.8 1.4 ns Rise Time1 Tr2 20pF load, 20% to 80% CPU, BOUT & BUS - 1.5 2.5 ns Tf2 20pF load, 80% to 20% CPU, BOUT & BUS - 1.4 2.4 ns Dt 45 50 55 % - 50 150 ps -250 - 250 ps - 1 3 % -5 2 5 % 12.0 14.318 16.0 MHz Fall Time1 1 Jitter, One Sigma1 Tj1s1 Jitter, Absolute1 Tjab1 Jitter, One Sigma1 Tj1s2 20pF load @j VOUT=1.4V CPU Load=20pF Bin=EXTCLK CPU Load=20pF Bin=EXTCLK BUS; Load=20pF Tjab2 BUS; Load=20pF Duty Cycle Jitter, Absolute 1 Input Frequency 1 Fi Logic Input Capacitance1 CIN Logic input pins - 5 - pF Crystal Oscillator Capacitance1 CINX - 18 - pF - 2.5 4.5 ms - 2.0 4.0 ms - 150 250 ps Clock Skew Window1 Tsk1 X1, X2 pins From V DD=1.6V to 1 st crossing of 66.5 MHz VDD supply ramp < 40ms From 1st crossing of acquisition to < 1% settling BOUT to BOUT; Load=20pF; @1.4V Clock Skew Window 1 Tsk2 BUS to BUS; Load=20pF; @1.4V - 300 500 ps Clock Skew Window 1 Tsk3 BOUT to BUS; Load=20pF; @1.4V 1 2.6 5 ps Power-on Time1 ton Frequency Settling Time 1 ts Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 4 ICS9159-20 LEAD COUNT 28L DIMENSIONL 0.704 SOIC Package Ordering Information ICS9159M-20 Example: ICS XXXX M-PPP Pattern Number(2 or 3 digit number for parts with ROM code patterns) Package Type M=SOIC, SOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS=Standard Device 5 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.