ICS9219 Integrated Circuit Systems, Inc. Direct Rambus™ Clock Generator Lite General Description Features ICS9219 is a High-speed clock generator providing 400 or 533 MHz differential clock source for direct Rambus memory system. ICS9219 takes a crystal as an input reference source, and produces the differential output clock required for the Rambus channel. ICS9219 provides a solution for a broad range of Direct Rambus memory applications. ICS9219 can be used in single or dual Rambus channels. An additional LVCMOS output, which provides a reference clock at the crystal frequency for the other system blocks is also included. • • • • • • Block Diagram Xtal OSC X2 PLL BUSCLKT BUSCLKC REF VDDT FS1 FS2 Control Logic VDDT GND X2 X1 VDD REF GND FS1* Mult BUSCLK1 0 16 400.00 1 21.332 533.30 Notes: 1 Output frequencies are based on 25MHz XTAL Input multipliers are also applicable to spread spectrum modulated input clocks. 2 Default muliplier value at power up. 0931B—10/25/04 16 15 14 13 12 11 10 9 FS0* VDD GND BUSCLKT BUSCLKC GND VDD FS2* 16-Pin 173 mil TSSOP * Pins have 60K internal pull-up to VDD Table 1. PLL Multiplier Selection and Output Frequency FS0 1 2 3 4 5 6 7 8 ICS9219 Pin Configuration FS0 X1 Compatible with all Direct RambusTM based ICs Provides differential clock source for direct Rambus memory system with 1GHz data transfer rate capability Cycle to Cycle jitter is less than 100ps 3.3V + 4% supply LVCMOS REF clock @ crystal frequency Output edge rate control to minimize EMI ICS9219 Pin Descriptions PIN # 1 2 3 4 5 6 7 8 PIN NAME VDDT GND X2 X1 VDD REF GND FS1* PIN TYPE PWR/IN PWR OUT IN PWR OUT PWR IN 9 FS2* IN 10 11 VDD GND PWR PWR 12 BUSCLKC OUT 13 BUSCLKT OUT 14 GND PWR 15 VDD PWR 16 FS0* IN * Pins have 60K internal pull-up to VDD FS1 FS0 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 0 0 0 0 FS2 Table 2: Function Table FS(2:0) INPUT VDDT MULT 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 X X X X X X 16 21.33 16 21.33 - DESCRIPTION Power supply, nominal 3.3V/Test mode Ground pin. Crystal output (14MHz to 25MHz) Crystal input (14MHz to 25MHz) Power supply, nominal 3.3V Reference of Input Ground pin. Frequency select pin. Real-time frequency select pin with internal 120Kohm pull-up resistor (check SMBus HW/SW setting for priority). Power supply, nominal 3.3V Ground pin. Output clock connected to the Rambus channel. This output is the complement of BUSCLK. Output clock connected to the Rambus channel. This output is the true component of BUSCLK. Ground pin. Power supply, nominal 3.3V Frequency select pin. MODE BUSCLKT BUSCLKC REF NORMAL NORMAL NORMAL NORMAL TEST TEST TEST TEST TEST TEST INPUT x MULT INPUT x MULT INPUT x MULT INPUT x MULT BUSCLKT/2 BUSCLKT/4 X1 X1 X1/2 X1/4 BUSCLKC BUSCLKC BUSCLKC BUSCLKC BUSCLKC/2 BUSCLKC/4 X1(INVERT) X1(INVERT) X1(INVERT)/2 X1(INVERT)/4 INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT 0931B—10/25/04 2 ICS9219 Absolute Maximum Ratings over operating free-air temperature Supply voltage range, VDD or VDDT (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4 V Input voltage range,VI, at any input terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to V DD + 0.5 V Output voltage range, VO, at any output terminal (BUSCLKT/C) . . . . . . . . . . . . . . . . . . . . -0.5 V to V DD + 0.5 V ESD rating (MIL-STD 883C, Method 3015) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 2 kV, Machine Model >200 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0˚C to 85˚C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65˚C to 150˚C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to the GND terminals. Recommended Operating Conditions Supply voltage, VDD Low-level input voltage, VIL High-level input voltage, VIH Internal pullup resistance Input frequency at crystal input MIN 3 FS (2:0) FS (2:0) FS (2:0) Low-level output current, IOL High-level output current, IOH Input capacitance (CMOS), CL 0.65 x VDD 90 14.0625 BUSCLKT/C REF BUSCLKT/C REF NOM 3.3 MAX 3.6 0.35 x VDD UNIT V 150 26 16 10 -16 -10 15 15 85 kΩ MHz MIN 2.5 0.5 MAX 3.7 4 3 UNIT ns V/ns ms MIN 14.0625 -15 MAX 26 15 100 10 1500 25.3 UNIT MHz ppm Ω ppm µΩ mH MΩ dB dB 25 FS (2:0) X1, X2 Operating free-air temperature 0 V mA mA pF C Timing Requirements Clock cycle time, t(CYCLE) Input slew rate, SR State transition latency (VDDX or S0 to CLKs - normal mode), t(STL) Crystal Specifications Frequency Frequency tolerance (at 25°C) ± 3°C) Equivalent resistance (CL = 10 pF) Temperature drift (-10°C to 75°C) Drive level Motional inductance Insulation resistance Spurious attenuation ratio (at frequency ±500 kHz) Overtone spurious 0.01 20.7 500 3 8 0931B—10/25/04 3 ICS9219 Electrical Characteristics over Recommended Operating Free-Air Temperature PARAMETER VX Differential crossing-point output voltage VCOS Peak-to-peak output voltage swing, single ended Input clamp voltage TEST CO NDITIO NS* MIN TYP** MAX UNIT See Figures 1 and 2 1.25 1.6 1.85 V 0.4 0.6 0.7 V VOH - VOL See Figure 1 VDD = 3V II = -18 mA RI Input resistance X1, X2 VDD = 3.3V V I = VO High-level input current X2 VDD = 3.3V VO = 2V 27 IIH FS0 VDD = 3.6V VI = VDD 10 FS1, FS2 VDD = 3.6V VI = VDD 10 VIK IIL Low-level input current -1.2 >50 X2 VDD = 3.6V VO = 0V FS0 VDD = 3.6V VI = 0V -30 -100 -5.7 FS1, FS2 VDD = 3.6V VI = 0V -10 -50 See Figure 1 VOH VOL IOH IOL High-level output voltage Low-level output voltage High-level output current Low-level output current BUSCLKT/C, REF BUSCLKT/C, REF BUSCLKT/C, REF BUSCLKT/C, REF IOH = -1 mA VDD 0.1V VDD = 3V IOH = -16 mA 2.2 See Figure 1 VDD = min to max IOH = 1 mA 0.05 0.1 VDD = 3V IOH = 16 mA 0.25 0.5 VDD = 3.135V VO = 1V -50 -32 VO = 1.65V -50 VDD = 3.465V VO = 3.135V VDD = 3.135V VO = 1.95V 43 VDD = 3.3V VO = 1.65V 69 69 VDD = 3.465V VO = 0.9V 30 36 mA ∠IO - 14.5 mA to ∠IO - 16.5 mA 12 25 40 ∠IO - 14.5 mA to ∠IO - 16.5 mA 12 17 40 Static supply current IDD (NORMA L) 3 pF O utputs high or low (VDDT = 0V) 6.5 mA O utputs high or low (VDDT = 0V) 50 mA Supply current in normal state 400 MHz 84 100 mA 533MHz 91 120 mA * VDD refers to any of the following: VDD, VDDT. ** All typical values are at VDD = 3.3V, T A 25°C. 4 -15 V mA -21 Low-level dynamic output resistance4 IDD mA 2.5 r OL IDDL mA 1 High-level dynamic output resistance 4 CO mA V r OH BUSCLKT, O utput capacitance BUSCLKC, REF Static supply current mA 2.1 VDD = min to max VDD = 3.3V V k r O = ∠VO/∠IO. This is defined at the output terminals, not at the measurement point of figure 1. 0931B—10/25/04 4 ICS9219 Switching Characteristics over Recommended Operating Free-Air Temperature Range. PARAMETER t(CYCLE) tJ Total jitter over 1, 2, 3, 4, 5 or 6 clock cycles tJL Long-term jitter DC tDC,ERR TEST CONDITIONS* Clock cycle time (BUSCLKT/C) TYP** 1.8 400 MHz See Figure 3 533 MHz 400 MHz 533 MHz See Figure 5 400 MHz tCR, tDF Output rise and fall times (measured at BUSCLKT/C 20%-80% of output voltage) See Figure 7 ∆tRF Difference between rise and fall times on a single device (20% ± 80%) |tCR - tCF| See Figure 7 tCYCLE(L) Clock cycle time (REF) t(CJ) REF cycle jitter t(CJ10) REF 10-cycle jitter DC(2) Output duty cycle REF tCRL, tCFL Output rise and fall times (measured at 20%-80% of output voltage) REF 50 50 300 43% 120 -0.2 See Figure 7 fmod = 50 kHz fmod = 8 MHz 0931B—10/25/04 5 ps 53% 30 50 30 50 250 400 ps 50 100 ps 142.2 ns 0.2 ns 1.3 t(CJ) ns 0.1 50 53% 0.8 1 -3 -20 ps 51 -1.3 t(CJ) 47% PLL loop bandwidth ns 33 80 See Figure 8 Measured at 50% UNIT 3.7 300 See Figure 6 533 MHz MAX 42 See Figure 4 Output duty cycle over 10,000 cycles Output cycle-to-cycle duty cycle error MIN ps ns dB ICS9219 Measurement Point RT RS Differential Driver CF ZCH RP RP CMID CMID RS ZCH CF RT Measurement Point Figure 1. Example System Clock Driver Equivalent Circuit CLK Vx+ Vx,nom Vx- CLKB Figure 2. Crossing-point Voltage CLK CLKB t4CYCLE, i+1 t4CYCLE, i tJ = t4CYCLE, i - t4CYCLE, i+1 over 10,000 consecutive cycles Figure 3. Short-term jitter CLK CLKB tCYCLE,i tCYCLE,i+1 tJ = tCYCLE,i - tCYCLE, i+1 over 10,000 consecutive cycles Figure 4. Cycle-to-cycle jitter 0931B—10/25/04 6 ICS9219 CLK CLKB tPW+ tPWtCYCLE DC = (tPW+ / tCYCLE) Figure 5. Duty Cycle Cycle (i) CLK CLKB tPW- (i) Cycle (i+1) tPW+ (i) tPW- (i+1) tCYCLE (i) tPW+ (i+1) tCYCLE (i+1) tDC,ERR = tPW+(i) - tPW+(i+1) and tPW-(i) - tPW-(i+1) Figure 6. Cycle-to-cycle Duty Cycle Error VH 80% V(t) 20% VL tR tF Figure 7. Input and Output Voltage Waveforms REF T Figure 8. REF Jitter 0931B—10/25/04 7 ICS9219 4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) (25.6 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 6.40 BASIC 0.252 BASIC E E1 4.30 4.50 .169 .177 0.65 BASIC 0.0256 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N 0° 8° 0° 8° α aaa -0.10 -.004 c N L E1 INDEX AREA E 1 2 α D A A2 VARIATIONS A1 N -Ce 16 SEATING PLANE b D mm. MIN 4.90 D (inch) MAX 5.10 Ref erence Doc.: JEDEC Publication 95, MO-153 10-0035 aaa C Ordering Information ICS9219yGLF-T Example: ICS XXXX y G LF- T Designation for tape and reel packaging Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0931B—10/25/04 8 MIN .193 MAX .201