TI SN65MLVD080

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SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003
FEATURES
D Low-Voltage Differential 30-Ω to 55-Ω Line
Drivers and Receivers for Signaling Rates(1)
Up to 250 Mbps; Clock Frequencies Up to 125
MHz
D Meets or Exceeds the M-LVDS Standard
TIA/EIA-899 for Multipoint Data Interchange
D Power Up/Down Glitch Free
D Controlled Driver Output Voltage Transition
Times for Improved Signal Quality
D −1 V to 3.4 V Common-Mode Voltage Range
Allows Data Transfer With 2 V of Ground
Noise
D Bus Pins High Impedance When Driver
Disabled or VCC ≤ 1.5 V
Independent Enables for each Driver
D
D Bus Pin ESD Protection Exceeds 8 kV
D Packaged in 64-Pin TSSOP (DGG)
APPLICATIONS
D Parallel Multipoint Data and Clock
multipoint buses presenting loads as low as 30-Ω and
incorporates controlled transition times to allow for stubs
off of the backbone transmission line.
The M-LVDS standard defines two types of receivers,
designated as Type-1 and Type-2. Type-1 receivers
(SN65MLVD080) have thresholds centered about zero
with 25 mV of hysteresis to prevent output oscillations with
loss of input; Type-2 receivers (SN65MLVD082)
implement a failsafe by using an offset threshold. In
addition, the driver rise and fall times are between 1 and
2.0 ns, complying with the M-LVDS standard to provide
operation at 250 Mbps while also accommodating stubs on
the bus. Receiver outputs are slew rate controlled to
reduce EMI and crosstalk effects associated with large
current surges. The M-LVDS standard allows for 32 nodes
on the bus providing a high-speed replacement for RS-485
where lower common-mode can be tolerated or when
higher signaling rates are needed.
The driver logic inputs and the receiver logic outputs are
on separate pins rather than tied together as in some
transceiver designs. The drivers have separate enables
(DE) and the receivers are enabled globally through (RE).
This arrangement of separate logic inputs, logic outputs,
and enable pins allows for a listen-while-talking operation.
The devices are characterized for operation from −40°C to
85°C.
Transmission Via Backplanes and Cables
D Low-Power High-Speed Short-Reach
LOGIC DIAGRAM (POSITIVE LOGIC)
Alternative to TIA/EIA-485
D Cellular Base Stations
D Central-Office Switches
D Network Switches and Routers
DESCRIPTION
SN65MLVD080, SN65MLVD082
Channel 1
1DE
1A
1D
1B
1R
RE
The SN65MLVD080 and SN65MLVD082 provide eight
half-duplex transceivers for transmitting and receiving
Multipoint-Low-Voltage Differential Signals in full
compliance with the TIA/EIA-899 (M-LVDS) standard,
which are optimized to operate at signaling rates up to 250
Mbps. The driver outputs have been designed to support
2DE − 8DE
7
2D − 8D 7
7
2R − 8R
2A − 8A
Channels 2 − 8
2B − 8B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
(1)The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
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Copyright  2003, Texas Instruments Incorporated
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART NUMBER
RECEIVER TYPE
PACKAGE MARKING
PACKAGE/CARRIER
SN65MLVD080DGG
Type 1
MLVD080
64-Pin TSSOP/Tube
SM65MLVD080DGGR
Type 1
MLVD080
64-Pin TSSOP/Tape and Reeled
SN65MLVD082DGG
Type 2
MLVD082
64-Pin TSSOP/Tube
SM65MLVD082DGGR
Type 2
MLVD082
64-Pin TSSOP/Tape and Reeled
PACKAGE DISSIPATION RATINGS
TA ≤ 25°C
POWER RATING
DGG
PCB JEDEC
STANDARD
Low-K(2)
1204.7 mW
DERATING FACTOR(1)
ABOVE TA = 25°C
10.5 mW/_C
DGG
High-K(3)
1839.4 mW
16.0 mW/_C
PACKAGE
TA = 85°C
POWER RATING
576 mW
880 mw
(1) This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow.
(2) In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
(3) In accordance with the High-K thermal metric definitions of EIA/JESD51-7.
THERMAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Junction-to-board thermal resistance, ΘJB
41.08
°C/W
Junction-to-case thermal resistance, ΘJC
6.78
°C/W
VCC = 3.3 V, DE = VCC, RE = GND, CL = 15 pF,
RL = 50 Ω, 250 Mbps random data on each input
Device power dissipation
VCC = 3.6 V, DE = VCC, RE = GND, CL = 15 pF,
RL = 50 Ω, 250 Mbps data on one input and 125
MHz clock on the others
477
mW
854(1)
(1) When all channels are running at a 125-MHz clock frequency, a 250 lfm is required for a low-K board, and 150 lfm is required for a high-K board.
In such applications, a TI 1:8 or dual 1:4 M-LVDS buffer is highly recommended, SN65MLVD128 or SN65MLVD129, to fan out clock signals in
multiple paths.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
SN65MLVD080, 082
Supply voltage range(2), VCC
Input voltage range
Output voltage range
Electrostatic discharge
−0.5 V to 4 V
A, B
−1.8 V to 4 V
R
−0.3 V to 4 V
A, or B
−1.8 V to 4 V
Human Body Model(3)
Charged-Device Model(4)
Continuous power dissipation
Storage temperature range
−0.5 V to 4 V
D, DE, RE
A, B
±8 kV
All pins
±2 kV
All pins
±1500 V
See Dissipation Rating Table
−65°C to 150°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114−A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
2
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RECOMMENDED OPERATING CONDITIONS
Supply voltage, VCC
MIN
NOM
3
3.3
MAX UNIT
3.6
V
VCC
0.8
V
GND
Voltage at any bus terminal VA or VB
−1.4
3.8
V
Magnitude of differential input voltage, VID
0.05
Operating free-air temperature, TA
−40
VCC
85
°C
140
°C
High-level input voltage, VIH
2
Low-level input voltage, VIL
Maximum junction temperature
V
V
DEVICE ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
Driver only
Both disabled
ICC
Supply current
Both enabled
TEST CONDITIONS
MIN TYP(1)
MAX
110
140
5
8
140
180
38
50
RE and DE at VCC, RL = 50 Ω, All others open
RE at VCC, DE at 0 V, RL = No Load, All others open
RE at 0 V, DE at VCC, RL = 50 Ω, CL = 15 pF, All others
open
Receiver only
RE at 0 V, DE at 0 V, CL = 15 pF, All others open
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
UNIT
mA
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
VAB
Differential output voltage magnitude (A, B)
∆VAB
Change in differential output voltage magnitude
between logic states (A, B)
VOS(SS)
Steady-state common-mode output voltage (A, B)
∆VOS(SS)
Change in steady-state common-mode output
voltage between logic states (A, B)
VOS(PP)
Peak-to-peak common-mode output voltage (A, B)
VA(OC)
Maximum steady-state open-circuit output voltage
(A, B)
TEST CONDITIONS
See Figure 2
See Figure 3
MIN(1)
TYP(2)
MAX
UNIT
480
650
mV
−50
50
mV
0.8
1.2
V
−50
50
mV
150
mV
0
2.4
V
0
2.4
V
1.2 VSS
V
See Figure 7
VB(OC)
Maximum steady-state open-circuit output voltage
(A, B)
VP(H)
Voltage overshoot, low-to-high level output (A, B)
VP(L)
Voltage overshoot, high-to-low level output (A, B)
IIH
High-level input current (D, DE)
VIH = 2 V to VCC
10
µA
IIL
Low-level input current (D, DE)
VIL = GND to 0.8 V
10
µA
IOS
Differential short-circuit output current magnitude
(A, B)
See Figure 4
24
mA
See Figure 5
−0.2 VSS
Ci
5
Input capacitance (D, DE)
VI = 0.4 sin(30E6πt) + 0.5 V, (3)
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) All typical values are at 25°C and with a 3.3-V supply voltage.
(3) HP4194A impedance analyzer (or equivalent)
V
pF
3
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SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted(1)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
Positive-going differential input voltage
threshold (A, B)
Type 1
50
VIT+
Type 2
150
VIT−
Negative-going differential input voltage
threshold (A, B)
Type 1 See Figure 9 and Table 1 and
Type 2 Table 2
Differential input voltage hysteresis,
(VIT+ − VIT) (A, B)
Type 1
25
VHYS
Type 2
0
VOH
High-level output voltage (R)
mV
50
VOL
Low-level output voltage (R)
IOL = 8 mA
IIH
High-level input current (RE)
VIH = 2 V to VCC
−10
IIL
Low-level input current (RE)
VIL = GND to 0.8 V
−10
VO = 0 V or VCC
−10
IOZ
High-impedance output current (R)
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
mV
−50
mV
2.4
IOH = −8 mA
UNIT
V
0.4
V
µA
µA
15
µA
BUS INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
IA
Receiver or transceiver with driver
disabled input current
IB
Receiver or transceiver with driver
disabled input current
IAB
Receiver or transceiver with driver
disabled differential input current
(IA − IB)
Receiver or transceiver power-off input
IA(OFF)
current
Receiver or transceiver power-off input
IB(OFF)
current
Receiver input or transceiver
IAB(OFF) power-off differential input current
(IA(off) − IB(off))
TEST CONDITIONS
MIN TYP(1)
MAX
VA = 3.8 V,
VB = 1.2 V,
0
32
VA = 0 V or 2.4 V,
VB = 1.2 V
−20
20
VA = −1.4 V,
VB = 1.2 V
−32
0
VB = 3.8 V,
VA = 1.2 V
0
32
VB = 0 V or 2.4 V,
VA = 1.2 V
−20
20
VB = −1.4 V,
VA = 1.2 V
−32
0
VA = VB,
−1.4 ≤ VA ≤ 3.8 V
−4
4
VA = 3.8 V,
VB = 1.2 V,
0 V ≤ VCC ≤ 1.5 V
0
32
VA = 0 V or 2.4 V,
VB = 1.2 V,
0 V ≤ VCC ≤ 1.5 V
−20
20
VA = −1.4 V,
VB= 1.2 V,
0 V ≤ VCC ≤ 1.5 V
−32
0
VB = 3.8 V,
VA = 1.2 V,
0 V ≤ VCC ≤ 1.5 V
0
32
VB = 0 V or 2.4 V,
VA = 1.2 V,
0 V ≤ VCC ≤ 1.5 V
−20
20
VB = −1.4 V,
VA = 1.2 V,
0 V ≤ VCC ≤ 1.5 V
−32
0
−4
4
VA = VB, 0 V ≤ VCC ≤ 1.5 V, −1.4 ≤ VA ≤ 3.8 V
UNIT
µA
µA
µA
µA
µA
µA
CA
Transceiver with driver disabled input
capacitance
VA = 0.4 sin (30E6πt) + 0.5V(2),
VB =1.2 V
5
pF
CB
Transceiver with driver disabled input
capacitance
VB = 0.4 sin (30E6πt) + 0.5V(2),
VA =1.2 V
5
pF
CAB
Transceiver with driver disabled
differential input capacitance
VAB = 0.4 sin (30E6πt)V (2)
CA/B
Transceiver with driver disabled input
capacitance balance, (CA/CB)
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) HP4194A impedance analyzer (or equivalent)
4
3
0.99
1.01
pF
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DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
tpLH
Propagation delay time, low-to-high-level output
1
1.5
2.4
ns
tpHL
Propagation delay time, high-to-low-level output
1
1.5
2.4
ns
tr
Differential output signal rise time
1
2
ns
tf
Differential output signal fall time
1
2
ns
tsk(o)
Output skew
350
ps
tsk(p)
Pulse skew (|tpHL − tpLH|)
150
ps
tsk(pp)
Part-to-part skew
600
ps
tjit(per)
Period jitter, rms (1 standard deviation) (2)
tjit(c−c)
Cycle-to-cycle jitter, rms
tjit(det)
Deterministic jitter
tjit(pp)
Peak-to-peak jitter(2)(5)
tpZH
Enable time, high-impedance-to-high-level output
tpZL
Enable time, high-impedance-to-low-level output
tpHZ
Disable time, high-level-to-high-impedance output
See Figure 5
0
100 MHz clock input(3)
200 Mbps 215−1 PRBS input(4)
See Figure 6
tpLZ
Disable time, low-level-to-high−impedance output
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
(3) tr = tf = 0.5 ns (10% to 90%), measured over 30 k samples.
(4) tr = tf = 0.5 ns (10% to 90%), measured over 100 k samples.
(5) Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)).
4
ps
45
ps
150
ps
190
ps
7
ns
7
ns
7
ns
7
ns
5
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SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
tpLH
Propagation delay time, low-to-high-level output
2
4
6
ns
tpHL
Propagation delay time, high-to-low-level output
2
4
6
ns
tr
Output signal rise time
1
2.3
ns
tf
Output signal fall time
1
2.3
ns
tsk(o)
Output skew
350
ps
tsk(p)
Pulse skew (|tpHL − tpLH|)
350
ps
tsk(pp)
Part-to-part skew(2)
1
ns
tjit(per)
Period jitter, rms (1 standard deviation) (3)
tjit(c−c)
Cycle-to-cycle jitter, rms
tjit(det)
Deterministic jitter
tjit(pp)
Peak-to-peak jitter(3)(6)
tpZH
Enable time, high-impedance-to-high-level output
tpZL
Enable time, high-impedance-to-low-level output
tpHZ
Disable time, high-level-to-high-impedance output
CL = 15 pF, See Figure 10
50
7
ps
110
ps
Type 1
550
ps
Type 2
480
ps
720
ps
660
ps
30
ns
30
ns
18
ns
28
ns
100 MHz clock input(4)
Type 1
200 Mbps 215−1 PRBS input(5)
Type 2
CL = 15 pF, See Figure 11
tpLZ
Disable time, low-level-to-high-impedance output
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) HP4194A impedance analyzer (or equivalent)
(3) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
(4) VID = 200 mVpp (’080), VID = 400 mVpp (’082), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 30 k samples.
(5) VID = 200 mVpp (’080), VID = 400 mVpp (’082), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 100 k samples.
(6) Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)).
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SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
VCC
IA
A
II
D
VAB
IB
VA
B
VI
VOS
VB
VA + VB
2
Figure 1. Driver Voltage and Current Definitions
3.32 kΩ
A
+
_
49.9 Ω
VAB
D
B
−1 V ≤ Vtest ≤ 3.4 V
3.32 kΩ
NOTE: All resistors are 1% tolerance.
Figure 2. Differential Output Voltage Test Circuit
R1
24.9 Ω
A
C1
1 pF
D
≈ 1.3 V
B
≈ 0.7 V
VOS(PP)
B
C2
1 pF
A
R2
24.9 Ω
VOS
C3
2.5 pF
∆VOS(SS)
VOS(SS)
NOTES:A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse frequency = 1 MHz,
duty cycle = 50 ± 5%.
B. C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 and R2 are metal film, surface mount, ±1%, and located within 2 cm of the D.U.T.
D. The measurement of VOS(PP) is made on test equipment with a −3 dB bandwidth of at least 1 GHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
A
0 V or VCC
IOS
+
B
VTest
−1 V or 3.4 V
−
Figure 4. Driver Short-Circuit Test Circuit
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SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003
A
C1
1 pF
D
C3
0.5 pF
R1
Output
50 Ω
B
C2
1 pF
VCC
VCC/2
Input
0V
tpLH
tpHL
VSS
0.9VSS
VP(H)
Output
0V
VP(L)
0.1V
SS
0 V SS
tf
tr
NOTES:A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 1 MHz,
duty cycle = 50 ± 5%.
B. C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a −3 dB bandwidth of at least 1 GHz.
Figure 5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
R1
24.9 Ω
A
0 V or VCC
C1
1 pF
D
B
DE
C4
Output
0.5 pF
C2
1 pF
R2
24.9 Ω
VCC
VCC/2
0V
DE
tpZH
tpHZ
∼ 0.6 V
0.1 V
0V
Output With
D at VCC
Output With
D at 0 V
NOTES:A.
B.
C.
D.
C3
2.5 pF
tpZL
tpLZ
0V
−0.1 V
∼ −0.6 V
All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%.
C1, C2, C3, and C4 includes instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
R1 and R2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
The measurement is made on test equipment with a −3 dB bandwidth of at least 1 GHz.
Figure 6. Driver Enable and Disable Time Circuit and Definitions
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SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003
A
0 V or VCC
B
VA or VB
1.62 kΩ , ±1%
Figure 7. Maximum Steady State Output Voltage
VCC
CLOCK
INPUT
VCC/2
0V
1/f0
Period Jitter
IDEAL
OUTPUT 0 V
VA −VB
VCC
PRBS INPUT
0V
ACTUAL
OUTPUT 0 V
VA −VB
VCC/2
1/f0
Peak to Peak Jitter
VA −VB
OUTPUT 0 V
tc(n)
tjit(per) =tc(n) −1/f0
VA −VB
tjit(pp)
Cycle to Cycle Jitter
OUTPUT
0V
VA − VB
tc(n)
tc(n+1)
tjit(cc) = | tc(n) − tc(n+1) |
NOTES:A.
B.
C.
D.
All input pulses are supplied by an Agilent 8304A Stimulus System with plug-in TBD.
The measurement is made on a TEK TDS6604 running TDSJIT3 application software
Period jitter and cycle-to-cycle jitter are measured using a 100 MHz 50 ±1% duty cycle clock input.
Peak-to-peak jitter and deterministic jitter are measured using a 200 Mbps 215−1 PRBS input.
Figure 8. Driver Jitter Measurement Waveforms
IA
A
VID
VCM
(VA + VB)/2
VA
IB
R
IO
B
VO
VB
Figure 9. Receiver Voltage and Current Definitions
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SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003
Table 1. Type-1 Receiver Input Threshold Test Voltages
APPLIED VOLTAGES
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMON−
MODE INPUT VOLTAGE
RECEIVER
OUTPUT
VIA
2.400
VIB
0.000
VID
2.400
VIC
1.200
0.000
2.400
−2.400
1.200
L
3.400
3.350
0.050
3.375
H
3.350
3.400
−0.050
3.375
L
−1.350
−1.400
0.050
−1.375
H
−1.400
−1.350
−0.050
−1.375
:
NOTE H= high level, L = low level, output state assumes receiver is enabled (RE = L)
H
L
Table 2. Type-2 Receiver Input Threshold Test Voltages
APPLIED VOLTAGES
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMON−
MODE INPUT VOLTAGE
RECEIVER
OUTPUT
VIA
2.400
VIB
0.000
VID
2.400
VIC
1.200
0.000
2.400
−2.400
1.200
L
3.400
3.250
0.150
3.325
H
3.400
3.350
0.050
3.375
L
−1.250
−1.400
0.150
−1.325
H
−1.350
−1.400
0.050
−1.375
:
NOTE H= high level, L = low level, output state assumes receiver is enabled (RE = L)
H
L
VID
VA
CL
15 pF
VB
VO
VA
1.2 V
VB
1.0 V
VID
0.2 V
0V
−0.2 V
tpHL
VO
tpLH
VOH
VCC/2
VOL
90%
10%
tf
tr
NOTES:A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%.
CL is a combination of a 20%-tolerance, low-loss ceramic, surface-mount capacitor and fixture capacitance within 2 cm of the D.U.T.
B. The measurement is made on test equipment with a −3 dB bandwidth of at least 1 GHz.
Figure 10. Receiver Timing Test Circuit and Waveforms
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SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003
1.2 V
RL
499 Ω
B
A
Inputs
RE
CL
15 pF
VO
+
_
VCC
VTEST
1V
A
VCC
VCC/2
0V
RE
tpZL
tpLZ
VCC
VCC/2
VOL +0.5 V
VOL
VO
VTEST
0V
1.4 V
A
VCC
VCC/2
0V
RE
tpZH
VO
VTEST
tpHZ
VOH
VOH −0.5 V
VCC/2
0V
NOTES:A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 1 MHz,
duty cycle = 50 ± 5%.
B. RL is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T.
C. CL is the instrumentation and fixture capacitance within 2 cm of the DUT and ±20%. The measurement is made on test equipment with
a −3 dB bandwidth of at least 1 GHz.
Figure 11. Receiver Enable/Disable Time Test Circuit and Waveforms
11
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SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003
INPUTS
CLOCK INPUT
VA −VB
VA − VB
0.2 V (’080)
0.4 V (’082)
1/f0
VCM
1V
Period Jitter
IDEAL
OUTPUT
VOH
VA
VCC/2
PRBS INPUT
VOL
1/f0
VB
VOH
ACTUAL
OUTPUT VCC/2
VOL
Peak to Peak Jitter
VOH
tc(n)
tjit(per) =tc(n) −1/f0
OUTPUT V /2
CC
VOL
tjit(pp)
Cycle to Cycle Jitter
VOH
OUTPUT
VCC/2
VOL
tc(n)
tc(n+1)
tjit(cc) = | tc(n) − tc(n+1) |
NOTES:A.
B.
C.
D.
All input pulses are supplied by an Agilent 8304A Stimulus System with plug-in TBD.
The measurement is made on a TEK TDS6604 running TDSJIT3 application software
Period jitter and cycle-to-cycle jitter are measured using a 100 MHz 50 ±1% duty cycle clock input.
Peak-to-peak jitter and deterministic jitter are measured using a 200 Mbps 215−1 PRBS input.
Figure 12. Receiver Jitter Measurement Waveforms
Terminal Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
1D − 8D
58, 57, 52, 51, 46, 45, 40, 39
1R − 8R
59, 56, 53, 50, 47, 44, 41, 38
Output
Data output for receivers
1A − 8A
6, 8, 12, 14, 18, 20, 24, 26
Bus I/O
M-LVDS bus noninverting input/output
1B − 8B
7, 9, 13, 15, 19, 21, 25, 27
Bus I/O
M-LVDS bus inverting input/output
GND
10, 16, 22, 28, 36, 37, 43, 49,
55, 62, 63, 64
Power
Circuit ground
VCC
5, 11, 17, 23, 34, 35, 42, 48,
54, 60, 61
Power
Supply voltage
RE
33
Input
Receiver enable, active low, enables all receivers
1DE − 8DE
1, 2, 3, 4, 29, 30, 31, 32
Input
Driver enable, active high, individual enables
12
Input
Data inputs for drivers
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SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003
PIN ASSIGNMENTS
DGG PACKAGE
(TOP VIEW)
1DE
2DE
3DE
4DE
VCC
1A
1B
2A
2B
GND
VCC
3A
3B
4A
4B
GND
VCC
5A
5B
6A
6B
GND
VCC
7A
7B
8A
8B
GND
5DE
6DE
7DE
8DE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND
GND
GND
VCC
VCC
1R
1D
2D
2R
GND
VCC
3R
3D
4D
4R
GND
VCC
5R
5D
6D
6R
GND
VCC
7R
7D
8D
8R
GND
GND
VCC
VCC
RE
13
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SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003
DEVICE FUNCTION TABLE
RECEIVER (080)
INPUTS
RE
VID = VA − VB
RECEIVER (082)
OUTPUT
INPUTS
OUTPUT
R
VID = VA − VB
RE
R
VID ≥ 50 mV
−50 mV < VID < 50 mV
VID ≤ −50 mV
X
X
L
L
L
H
Open
H
?
L
Z
Z
VID ≥ 150 mV
50 mV < VID < 150 mV
VID ≤ 50 mV
X
X
L
L
L
H
Open
H
?
L
Z
Z
Open Circuit
L
?
Open Circuit
L
L
DRIVERS
INPUT
ENABLE
D
L
H
OPEN
X
X
DE
H
H
H
OPEN
L
OUTPUTS
A OR Y
B OR Z
L
H
L
Z
Z
H
L
H
Z
Z
H = high level, L = low level, Z = high impedance, X = Don’t care, ? = indeterminate
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
DRIVER OUTPUT
DRIVER INPUT AND DRIVER ENABLE
RECEIVER ENABLE
VCC
VCC
VCC
360 kΩ
400 Ω
400 Ω
D or DE
Y or Z
7V
RE
7V
360 kΩ
RECEIVER INPUT
RECEIVER OUTPUT
VCC
VCC
100 kΩ
100 kΩ
250 kΩ
10 Ω
250 kΩ
A
R
B
10 Ω
200 kΩ
14
200 kΩ
7V
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SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREQUENCY
180
VCC = 3.3 V
TA = 25°C
150
VCC = 3.3 V,
TA = 25°C,
f = 100 MHz
150
ICC − Supply Current − mA
ICC − Supply Current − mA
180
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
Tx
120
Rx
90
60
30
120
Rx
90
60
30
0
10
30
50
70
90
f − Frequency − MHz
110
0
−50
130
−30
−10
10
30
50
70
TA − Free-Air Temperature − °C
Figure 13
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT RESISTANCE
1500
550
VCC = 3.3 V
TA = 25°C
VCC = 3.3 V,
TA = 25°C
Differential Output Voltage − mV
Differential Output Voltage − mV
90
Figure 14
DIFFERENTIAL OUTPUT VOLTAGE
vs
FREQUENCY
530
510
490
470
450
Tx
1200
900
600
300
0
0
20
40
60
80
100
f − Frequency − MHz
Figure 15
120
140
0
50
100
150
200
Output Resistance − Ω
Figure 16
15
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SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003
DIFFERENTIAL OUTPUT VOLTAGE
vs
TRACE LENGTH
DRIVER PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
2.5
600
VCC = 3.3 V,
TA = 25°C,
f = 1 MHz,
550
Driver Propagation Delay − ns
Differential Output Voltage − mV
VCC = 3.3 V
TA = 25°C
500
450
400
2
tPLH
tPHL
1.5
1
0.5
350
0
−50
300
0
10
20
30
40
50
60
Trace Length − Inches
70
80
−30
−10
Receiver Type-2 Propagation Delay − ns
Receiver Type-1 Propagation Delay − ns
4
VCC = 3.3 V,
VIC = 1 V,
|VID| = 200 mV,
f = 1 MHz
tPLH
3.2
tPHL
2.8
2.4
−10
10
30
50
TA − Free-Air Temperature − °C
Figure 19
16
70
90
RECEIVER TYPE-2 PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
4
−30
50
Figure 18
RECEIVER TYPE-1 PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
2
−50
30
TA − Free-Air Temperature − °C
Figure 17
3.6
10
70
90
3.6
VCC = 3.3 V,
VIC = 1 V,
|VID| = 400 mV,
f = 1 MHz
tPLH
3.2
tPHL
2.8
2.4
2
−50
−30
−10
10
30
50
TA − Free-Air Temperature − °C
Figure 20
70
90
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SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003
DRIVER TRANSITION TIME
vs
FREE-AIR TRMPERATURE
TYPE-1 RECEIVER TRANSITION TIME
vs
FREE-AIR TEMPERATURE
2.5
2.1
VCC = 3.3 V,
f = 1 MHz,
TA = 25°C
t r / tf − Rising/Falling Transition Time − ns
t r / tf − Rising/Falling Transition Time − ns
2.5
tr
1.7
tf
1.3
0.9
0.5
−50
−30
−10
10
30
50
70
TA − Free-Air Temperature − °C
VCC = 3.3 V,
VIC = 1 V,
|VID| = 200 mV,
f = 1 MHz
2.1
tr
1.7
tf
1.3
0.9
0.5
−50
90
−30
−10
Figure 21
70
90
18
VCC = 3.3 V,
VIC = 1 V,
|VID| = 400 mV,
f = 1 MHz
1.7
Added Receiver Type-1 Period Jitter − ps
t r / tf − Rising/Falling Transition Time − ns
50
ADDED RECEIVER TYPE-1 PERIOD JITTER
vs
FREQUENCY
2.5
tr
tf
1.3
0.9
0.5
−50
30
Figure 22
TYPE-2 RECEIVER TRANSITION TIME
vs
FREE-AIR TEMPERATURE
2.1
10
TA − Free-Air Temperature − °C
−30
−10
10
30
50
70
TA − Free-Air Temperature − °C
Figure 23
90
15
VCC = 3.3 V
VIC = 1 V,
|VID| = 200 mV,
Input = Clock
12
9
6
3
0
15
25
35
45
55
65
75
f − Frequency − MHz
85
95
105
Figure 24
17
www.ti.com
SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003
ADDED RECEIVER TYPE-2 PERIOD JITTER
vs
FREQUENCY
ADDED DRIVER PERIOD JITTER
vs
FREQUENCY
18
VCC = 3.3 V
Input = Clock
VCC = 3.3 V
VIC = 1 V,
|VID| = 400 mV,
Input = Clock
15
Added Driver Period Jitter − ps
Added Receiver Type-2 Period Jitter − ps
18
12
9
6
3
15
12
9
6
3
0
15
25
35
45
55 65
75
f − Frequency − MHz
85
95
0
105
15
25
35
45
Figure 25
VCC = 3.3 V
VIC = 1 V,
|VID| = 200 mV,
Input = Clock
40
30
20
10
0
25
35
45
55
65 75
f − Frequency − MHz
Figure 27
18
75
85
95
105
ADDED RECEIVER TYPE-2 CYCLE-TO-CYCLE JITTER
vs
FREQUENCY
Added Receiver Type-2 Cycle-To-Cycle Jitter − ps
Added Receiver Type-1 Cycle-To-Cycle Jitter − ps
60
15
65
Figure 26
ADDED RECEIVER TYPE-1 CYCLE-TO-CYCLE JITTER
vs
FREQUENCY
50
55
f − Frequency − MHz
85
95 105
60
VCC = 3.3 V
VIC = 1 V,
|VID| = 400 mV,
Input = Clock
50
40
30
20
10
0
15
25
35
45
55
65
75
f − Frequency − MHz
Figure 28
85
95
105
www.ti.com
SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003
ADDED DRIVER CYCLE-TO-CYCLE JITTER
vs
FREQUENCY
350
VCC = 3.3 V
Input = Clock
Added Receiver Type-1 Deterministic Jitter − ps
Added Driver Cycle-To-Cycle Jitter − ps
60
50
40
30
20
10
0
ADDED RECEIVER TYPE-1 DETERMINISTIC JITTER
vs
DATA RATE
15
25
35
45
55 65
75
85
f − Frequency − MHz
95
105
300
VCC = 3.3 V,
TA = 25°C,
VIC = Varying,
Input = PRBS 215−1
250
200
150
100
50
0
30
50
70
110
130 150
170 190 210
Data Rate − Mbps
Figure 29
Figure 30
ADDED RECEIVER TYPE-2 DETERMINISTIC JITTER
vs
DATA RATE
ADDED RECEIVER TYPE-1 PEAK-TO-PEAK JITTER
vs
DATA RATE
350
450
VCC = 3.3 V,
TA = 25°C,
VIC = Varying,
Input = PRBS 215−1
300
Added Receiver Type-1 Peak-To-Peak Jitter − ps
Added Receiver Type-2 Deterministic Jitter − ps
90
250
200
150
100
50
0
30
50
70
90
110
130
150 170
Data Rate − Mbps
Figure 31
190 210
360
VCC = 3.3 V,
|VID| = 200 mV,
VIC = 1 V
Input = PRBS 215−1
270
180
90
0
30
50
70
90
110 130 150 170 190 210
Data Rate − Mbps
Figure 32
19
www.ti.com
SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003
ADDED RECEIVER TYPE-2 PEAK-TO-PEAK JITTER
vs
DATA RATE
120
450
VCC = 3.3 V,
|VID| = 400 mV,
VIC = 1 V
Input = PRBS 215−1
360
Added Driver Peak-To-Peak Jitter − ps
Added Receiver Type-2 Peak-To-Peak Jitter − ps
ADDED DRIVER PEAK-TO-PEAK JITTER
vs
DATA RATE
270
180
90
0
30
50
70
90
110
130 150
170 190 210
100
80
60
40
20
0
30
50
70
90
110 130 150 170 190 210
Data Rate − Mbps
Data Rate − Mbps
Figure 33
Figure 34
RECEIVER OUTPUT EYE PATTERN
200 Mbps, 215−1 PRBS, VCC = 3.3 V,
|VID| = 200 mV, VIC = 1 V
Vertical Scale = 133 mV/div
Vertical Scale = 200 mV/div
DRIVER OUTPUT EYE PATTERN
200 Mbps, 215−1 PRBS, VCC = 3.3 V
Horizontal Scale = 1 ns/div
Figure 35
20
VCC = 3.3 V
TA = 25°C
Input = PRBS 215−1
Horizontal Scale = 1 ns/div
Figure 36
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SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003
APPLICATION INFORMATION
SOURCE SYNCHRONOUS SYSTEM CLOCK (SSSC)
There are two approaches to transmit data in a synchronous system: centralized synchronous system clock
(CSSC) and source synchronous system clock (SSSC). CSSC systems synchronize data transmission
between different modules using a clock signal from a centralized source. The key requirement for a CSSC
system is for data transmission and reception to complete during a single clock cycle. The maximum operating
frequency is the inverse of the shortest clock cycle for which valid data transmission and reception can be
ensured. SSSC systems achieve higher operating frequencies by sending clock and data signals together to
eliminate the flight time on the transmission media, backplane, or cables. In SSSC systems, the maximum
operating frequency is limited by the cumulated skews that can exist between clock and data. The absolute flight
time of data on the backplane does not provide a limitation on the operating frequency as it does with CSSC.
The SN65MLVD082 can be designed for interfacing the data and clock to support source synchronous system
clock (SSSC) operation. It is specified for transmitting data up to 250 Mbps and clock frequencies up to 125
MHz. The figure below shows an example of a SSSC architecture supported by M-LVDS transceivers. The
SN65MLVD206, a single channel transceiver, transmits the main system clock between modules. A retiming
unit is then applied to the main system clock to generate a local clock for subsystem synchronization
processing. System operating data (or control) and subsystem clock signals are generated from the data
processing unit, such as a microprocessor, FPGA, or ASIC, on module 1, and sent to slave modules through
the SN65MLVD082. Such design configurations are common while transmitting parallel control data over the
backplane with a higher SSSC subsystem clock frequency. The subsystem clock frequency is aligned with the
operating frequencies of the data processing unit to synchronize data transmission between different units.
Main System Clock
MLVD206
1Tx 1Rx
Modules 1
Timing
Process
Unit
Modules N
Data Process Unit
ASIC/FPGA
uController
Subsystem
Clock
MLVD206
1Tx 1Rx
Timing
Process
Unit
tsk(o)Source
1 Data Width 15
Data Process Unit
ASIC/FPGA
uController
Subsystem
Clock
Number of Modules
MLVD080/082 (x2)
8Tx 8Rx
MLVD206
1Tx 1Rx
1 Data Width 15
tsk(p−p)RCVR
MLVD080/082 (x2)
8Tx 8Rx
tsk (p−p)DRVR
Centralized − Synchronous Main System Clock M − LVDS Differential Bus
80~100 Ω RT
80~100 Ω RT
Data/Control M − LVDS Differential Bus #1 ~ #15
80~100 Ω RT
tsk(flight)BP
80~100 Ω RT
Source − Synchronous Subsystem Clock M − LVDS Differential Bus
80~100 Ω RT
80~100 Ω RT
M− LVDS Backplane
Figure 37. Using Differential M-LVDS to Perform Source Synchronous System Clock Distribution
21
www.ti.com
SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003
The maximum SSSC frequencies in a transparent mode can be calculated with the following equation:
fmax(clk) < 1/[ tsk(o)Source + tsk(p−p)DRVR + tsk(flight)BP + tsk(p−p)RCVR
Setup time and hold time on the receiver side are decided by the data processing unit, FPGA, or ASIC in this
example. By considering data passes through the transceiver only, the general calculation result is 238 MHz
when using the following data:
tsk(o)Source = 2.0 ns
Output skew of data processing unit; any skew between data bits, or clock
and data bits
tsk(p−p)DRVR = 0.6 ns
Driver part-to-part skew of the SN65MLVD082
tsk(flight)BP = 0.4 ns
Skew of propagation delay on the backplane between data and clock
tsk(p−p)RCVR = 1.0 ns
Receiver part-to-part skew of the SN65MLVD082
The 238-MHz maximum operating speed calculated above was determined based on data and clock skews
only. Another important consideration when calculating the maximum operating speed is output transition time.
Transition-time-limited operating speed can be calculated from the following formula:
f + 45%
2
1
t transition
Using the typical transition time of the SN65MLVD082 of 1.4 ns, a transition-time-limited operating frequency
of 170 MHz can be supported.
In addition to the high operating frequencies of SSSC that can be ensured, the SN65MLVD082 presents other
benefits as other M-LVDS bus transceivers can provide:
D
D
D
D
Robust system operation due to common mode noise cancellation using a low voltage differential receiver
Low EMI radiation noise due to differential signaling improves signal integrity through the backplane
A singly terminated transmission line is easy to design and implement
Low power consumption in both active and idle modes minimizes thermal concerns on each module
In dense backplane design, these benefits are important for improving the performance of the whole system.
A similar result can be achieved with the SN65MLVD080.
22
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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