ICS9250-25 Integrated Circuit Systems, Inc. Preliminary Product Preview Frequency Generator & Integrated Buffers for Celeron & PII/III™ Pin Configuration VDDREF X1 X2 GNDREF GND3V66 3V66-0 3V66-1 3V66-2 VDD3V66 VDDPCI 1 *FS0/PCICLK0 1 *FS1/PCICLK1 PCICLK2 GNDPCI PCICLK3 PCICLK4 PCICLK5 VDDPCI PCICLK6 PCICLK7 GNDPCI PD# SCLK SDATA VDDSDR SDRAM11 SDRAM10 GNDSDR Output Features: • 2 - CPUs @ 2.5V, up to 153.33MHz. • 13 - SDRAM @ 3.3V, up to 153.33MHz. • 3 - 3V66 @ 3.3V, 2x PCI MHz. • 8 - PCI @3.3V. • 1 - 48MHz, @3.3V fixed. • 1 - 24MHz @ 3.3V • 1 - REF @3.3V, 14.318MHz. Features: • Up to 153.33MHz frequency support • Support power management through PD#. • Spread spectrum for EMI control (± 0.25%) center spread. • Uses external 14.318MHz crystal • FS pins for frequency select Key Specifications: • CPU Output Jitter: <250ps • IOAPIC Output Jitter: <500ps • 48MHz, 3V66, PCI Output Jitter: <500ps • Ref Output Jitter. <1000ps • CPU Output Skew: <175ps • PCI Output Skew: <500ps • 3V66 Output Skew <175ps • For group skew timing, please refer to the Group Timing Relationship Table. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 REF0/FS4* VDDLAPIC IOAPIC VDDLCPU CPUCLK0 CPUCLK1 GNDLCPU GNDSDR SDRAM0 SDRAM1 SDRAM2 VDDSDR SDRAM3 SDRAM4 SDRAM5 GNDSDR SDRAM6 SDRAM7 SDRAM_F VDDSDR GND48 24MHz/FS2* 1 48MHz/FS3* VDD48 VDDSDR SDRAM8 SDRAM9 GNDSDR 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 ICS9250-25 Recommended Application: 810/810E and Solano type chipset 56-Pin 300 mil SSOP 1. These pins will have 1.5 to 2X drive strength. * 120K ohm pull-up to VDD on indicated inputs. Block Diagram PLL2 48MHz 24MHz /2 X1 X2 XTAL OSC PLL1 Spread Spectrum FS[4:0] REF0 CPU DIVDER 2 CPUCLK [1:0] SDRAM DIVDER 12 SDRAM [11:0] SDRAM_F Control Logic IOAPIC DIVDER IOAPIC PD# Config. SDATA SCLK 9250-25 Rev A 10/03/00 Third party brands and names are the property of their respective owners. Reg. PCI DIVDER 8 3V66 DIVDER 3 PCICLK [7:0] 3V66 [2:0] PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. ICS9250-25 Preliminary Product Preview General Description The ICS9250-25 is a single chip clock solution for desktop designs using the 810/810E and Solano style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-25 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection. Pin Configuration PIN P I N NA M E NUMBER 1, 9, 10, 18, 25, VDD 32, 33, 37, 45 TYPE PWR 2 X1 IN 3 X2 OUT GND PWR 4, 5, 14, 21, 28, 29, 36, 41, 49 8, 7, 6 11 12 20, 19, 17, 16, 15, 13 DESCRIPTION 3.3V power supply Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) Ground pins for 3.3V supply 3V66 [2:0] OUT 3 . 3 V F i xe d 6 6 M H z c l o c k o u t p u t s f o r H U B PCICLK01 FS0 OUT IN 3.3V PCI clock outputs, with Synchronous CPUCLKS Logic input frequency select bit. Input latched at power on. PCICLK11 IN 3.3V PCI clock outputs, with Synchronous CPUCLKS FS1 IN Logic input frequency select bit. Input latched at power on. PCICLK [7:2] OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS 22 PD# IN Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 23 SCLK IN Clock input of I2C input 24 SDATA IN Data input for I2C serial input. 48MHz OUT 34 35 FS3 FS2 IN IN 3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t f o r U S B Logic input frequency select bit. Input latched at power on. Logic input frequency select bit. Input latched at power on. 24MHz OUT 3.3V fixed 24MHz output 38 48, 47, 44, 43, 42, 40, 39, 31, 30, 30, 27, 26 50 SDRAM_F OUT 3.3V free running 100MHz SDRAM not affected by I2C SDRAM [11:0] OUT 3.3V output running 100MHz. All SDRAM outputs can be turned off t h r o u g h I 2C GNDL PWR Ground for 2.5V power supply for CPU & APIC 51, 52 CPUCLK [1:0] OUT 2.5V Host bus clock output. Output frequency derived from FS pins. 53, 55 54 VDDL IOAPIC FS4 PWR OUT IN 2.5V power suypply for CPU, IOAPIC 2.5V clock outputs running at 16.67MHz. Logic input frequency select bit. Input latched at power on. REF01 OUT 3.3V, 14.318MHz reference clock output. 56 Third party brands and names are the property of their respective owners. 2 ICS9250-25 Preliminary Product Preview Frequency Selection FS4 FS3 FS2 FS1 FS0 CPU MHz SDRAM MHz 3V66 MHz PCI MHz IOAPIC MHz 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 55.00 60.00 66.80 68.33 70.00 72.00 75.00 77.00 83.30 90.00 100.30 103.00 112.50 115.00 120.00 125.00 128.00 130.00 133.70 137.00 140.00 145.00 150.00 153.33 125.00 130.00 133.70 137.00 140.00 145.00 150.00 153.33 82.50 90.00 100.20 102.50 105.00 108.00 112.50 115.50 83.30 90.00 100.30 103.00 112.50 115.00 120.00 125.00 128.00 130.00 133.70 137.00 140.00 145.00 150.00 153.33 93.75 97.50 100.28 102.75 105.00 108.75 112.50 115.00 55.00 60.00 66.80 68.33 70.00 72.00 75.00 77.00 55.53 60.00 66.87 68.67 75.00 76.67 80.00 83.33 64.00 65.00 66.85 68.50 70.00 72.50 75.00 76.67 62.50 65.00 66.85 68.50 70.00 72.50 75.00 76.67 27.5 30 33.4 34.165 35 36 37.5 38.5 27.8 30.0 33.4 34.3 37.5 38.3 40.0 41.7 32.0 32.5 33.4 34.3 35.0 36.3 37.5 38.3 31.3 32.5 33.4 34.3 35.0 36.3 37.5 38.3 13.75 15 16.7 17.0825 17.5 18 18.75 19.25 13.9 15.0 16.7 17.2 18.8 19.2 20.0 20.8 16.0 16.3 16.7 17.1 17.5 18.1 18.8 19.2 15.6 16.3 16.7 17.1 17.5 18.1 18.8 19.2 Clock Enable Configuration PD# CPUCLK SDRAM IOAPIC 66MHz PCICLK REF, 48MHz Osc VCOs 0 LOW LOW LOW LOW LOW LOW OFF OFF 1 ON ON ON ON ON ON ON ON Third party brands and names are the property of their respective owners. 3 ICS9250-25 Preliminary Product Preview Byte 0: Functionality and frequency select register (Default=0) (1 = enable, 0 = disable) Bit CPUCLK SDRAM MHz MHz 0 0 0 0 0 55.00 82.50 0 0 0 0 1 60.00 90.00 0 0 0 1 0 66.80 100.20 0 0 0 1 1 68.33 102.50 0 0 1 0 0 70.00 105.00 0 0 1 0 1 72.00 108.00 0 0 1 1 0 75.00 112.50 0 0 1 1 1 77.00 115.50 0 1 0 0 0 83.30 83.30 0 1 0 0 1 90.00 90.00 0 1 0 1 0 100.30 100.30 0 1 0 1 1 103.00 103.00 0 1 1 0 0 112.50 112.50 0 1 1 0 1 115.00 115.00 0 1 1 1 0 120.00 120.00 0 1 1 1 1 125.00 125.00 1 0 0 0 0 128.00 128.00 1 0 0 0 1 130.00 130.00 1 0 0 1 0 133.70 133.70 1 0 0 1 1 137.00 137.00 1 0 1 0 0 140.00 140.00 1 0 1 0 1 145.00 145.00 1 0 1 1 0 150.00 150.00 1 0 1 1 1 153.33 153.33 1 1 0 0 0 125.00 93.75 1 1 0 0 1 130.00 97.50 1 1 0 1 0 133.70 100.28 1 1 0 1 1 137.00 102.75 1 1 1 0 0 140.00 105.00 1 1 1 0 1 145.00 108.75 1 1 1 1 0 150.00 112.50 1 1 1 1 1 153.33 115.00 0-Frequency is selected by hardware select, latched inputs 1- Frequency is selected by Bit 2,6:4 0- Normal 1- Spread spectrum enable ± 0.25% Center Spread 0- Running 1- Tristate all outputs Bit (2,7:4) Bit (2, 7:4) Bit 3 Bit 1 Bit 0 PWD Description 3V66 MHz 55.00 60.00 66.80 68.33 70.00 72.00 75.00 77.00 55.53 60.00 66.87 68.67 75.00 76.67 80.00 83.33 64.00 65.00 66.85 68.50 70.00 72.50 75.00 76.67 62.50 65.00 66.85 68.50 70.00 72.50 75.00 76.67 PCICLK 27.5 30 33.4 34.165 35 36 37.5 38.5 27.8 30.0 33.4 34.3 37.5 38.3 40.0 41.7 32.0 32.5 33.4 34.3 35.0 36.3 37.5 38.3 31.3 32.5 33.4 34.3 35.0 36.3 37.5 38.3 IOAPIC MHz 13.75 15 16.7 17.0825 17.5 18 18.75 19.25 13.9 15.0 16.7 17.2 18.8 19.2 20.0 20.8 16.0 16.3 16.7 17.1 17.5 18.1 18.8 19.2 15.6 16.3 16.7 17.1 17.5 18.1 18.8 19.2 Notes: 1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3. 2. The I2C readback for Bit 2, 7:4 indicate the revision code. Third party brands and names are the property of their respective owners. 4 00001 Note 1 0 1 0 ICS9250-25 Preliminary Product Preview Byte 2: Control Register (1 = enable, 0 = disable) Byte 1: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 35 34 38 PWD X X X 1 1 1 1 1 Description FS3# FS0# FS2# 24MHz (Reserved) 48MHz (Reserved) SDRAM_F Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 3: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 20 19 17 16 15 13 12 11 PWD 1 1 1 1 1 1 1 1 Pin# 26 27 30 31 PWD 1 1 1 1 1 1 1 1 PWD 1 1 1 1 1 1 1 1 Description SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 Byte 4: Control Register (1 = enable, 0 = disable) Description PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 5: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 39 40 42 43 44 46 47 48 Pin# 8 6 7 54 51 52 PWD 1 1 1 X 1 X 1 1 Description 3V66_2 3V66_0 3V66_1 FS4# IOAPIC FS1# CPUCLK1 CPUCLK0 Byte 6: Peripheral , Active/Inactive Register (1= enable, 0 = disable) Description (Reserved) (Reserved) (Reserved) (Reserved) SDRAM11 SDRAM10 SDRAM9 SDRAM8 Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Pin# - PWD 0 0 0 0 0 1 1 0 Description R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) Note: Dont write into this register, writing into this register can cause malfunction Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default Third party brands and names are the property of their respective owners. 5 ICS9250-25 Preliminary Product Preview Absolute Maximum Ratings Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V 3.6V GND 0.5 V to V DD +0.5 V 0°C to +70°C 65°C to +150°C 115°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Group Timing Relationship Table1 Group CPU 66MHz SDRAM 100MHz CPU 100MHz SDRAM 100MHz CPU 133MHz SDRAM 100MHz CPU 133MHz SDRAM 133MHz Offset Tolerance Offset Tolerance Offset Tolerance Offset Tolerance CPU to SDRAM 2.5ns 500ps 5.0ns 500ps 0.0ns 500ps 3.75ns 500ps CPU to 3V66 7.5ns 500ps 5.0ns 500ps 0.0ns 500ps 0.0ns 500ps SDRAM to 3V66 0.0ns 500ps 0.0ns 500ps 0.0ns 500ps 3.75ns 500ps 3V66 to PCI 1.5-3.5ns 500ps 1.5-3.5ns 500ps 1.5-3.5ns 500ps 1.5 -3.5ns 500ps PCI to PCI USB & DOT 0.0ns Asynch 1.0ns N/A 0.0ns Asynch 1.0ns N/A 0.0ns Asynch 1.0ns N/A 0.0ns Asynch 1.0ns N/A Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Pin Inductance Input Capacitance1 IDD3.3PD CONDITIONS VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66M MIN 2 VSS-0.3 -5 -5 -200 TYP CL = 0 pF; With input address to Vdd or GND MAX UNITS VDD+0.3 V 0.8 V µA 5 µA µA 100 mA 600 µA 7 MHz nH 5 6 45 pF pF pF Fi Lpin VDD = 3.3 V; CIN Cout CINX Logic Inputs Out put pin capacitance X1 & X2 pins Transition Time1 Ttrans To 1st crossing of target Freq. 3 mS Settling Time1 Ts From 1st crossing to 1% target Freq. 3 mS TSTAB t PZH,tPZH t PLZ,t PZH From VDD = 3.3 V to 1% target Freq. output enable delay (all outputs) output disable delay (all outputs) 3 10 10 mS nS nS Clk Stabilization Delay 1 SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP 1 14.318 27 Guarenteed by design, not 100% tested in production. Third party brands and names are the property of their respective owners. 6 1 1 ICS9250-25 Preliminary Product Preview Electrical Characteristics - CPU TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL Output Impedance RDSP2B1 RDSN2B1 Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current VOH2B VOL2B IOH2B IOL2B CONDITIONS MIN TYP MAX UNITS VO = VDD*(0.5) 13.5 45 Ω VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @MIN= 1.0V , VOH@ MAX= 2.375V VOL @MIN= 1.2V , VOL@ MAX= 0.3V 13.5 2 45 -27 27 0.4 -27 30 Ω V V mA mA Rise Time tr2B1 VOL = 0.4 V, VOH = 2.0 V 0.4 1.6 ns Fall Time tf2B1 dt2B1 tsk2B1 VOH = 0.4 V, VOL = 2.0 V 0.4 1.6 ns VT = 1.25 V 45 55 ns VT = 1.25 V 175 ps VT = 1.25 V 250 ps Duty Cycle Skew tjcyc-cyc1 50 Jitter 1 Guarenteed by design, not 100% tested in production. Electrical Characteristics - 3V66 TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS RDSP1 1 VO = VDD*(0.5) 12 55 Ω Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current RDSN1 VOH1 VOL1 IOH1 IOL1 1 VO = VDD*(0.5) 12 IOH = -1 mA 2.4 IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33 VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 30 55 0.55 -33 38 Ω V V mA mA Rise Time tr11 VOL = 0.4 V, VOH = 2.4 V 0.4 1.6 ns Fall Time 1 VOH = 2.4 V, VOL = 0.4 V 0.4 1.6 ns 1 VT = 1.5 V 45 55 % 1 VT = 1.5 V VT = 1.5 V 175 500 ps ps Output Impedance Duty Cycle Skew Jitter 1 tf1 dt1 tsk1 tjcyc-cyc Guarenteed by design, not 100% tested in production. Third party brands and names are the property of their respective owners. 7 ICS9250-25 Preliminary Product Preview Electrical Characteristics - IOAPIC TA = 0 - 70C;VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL Output Impedance RDSP4B1 RDSN4B1 Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current MIN TYP MAX UNITS VO = VDD*(0.5) 9 30 Ω VO = VDD*(0.5) IOH = -5.5 mA IOL = 9.0 mA VOH@ min = 1.4 V, VOH@ MAX = 2.5 V VOL@ MIN = 1.0 V, VOL@ MAX= 0.2 9 2 30 -36 36 0.4 -21 31 Ω V V mA mA Rise Time tr4B1 VOL = 0.4 V, VOH = 2.0 V 0.4 1.6 nS Fall Time tf4B1 dt4B1 VOH = 2.0 V, VOL = 0.4 V 0.4 1.6 nS VT = 1.25 V VT = 1.25 V 45 55 500 % pS Duty Cycle Jitter 1 VOH4\B VOL4B IOH4B IOL4B CONDITIONS tjcyc-cyc Guarenteed by design, not 100% tested in production. Electrical Characteristics - SDRAM TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS RDSP3 1 VO = VDD*(0.5) 10 24 Ω Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current RDSN3 VOH3 VOL3 IOH3 IOL3 1 VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @MIN= 2.0 V, VOH@ MAX=3.135 V VOL@ MIN= 1.0 V, VOL@ MAX=0.4 V 10 2.4 24 -54 54 0.4 -46 53 Ω V V mA mA Rise Time Tr31 VOL = 0.4 V, VOH = 2.4 V 0.4 1.6 ns Fall Time Tf3 1 VOH = 2.4 V, VOL = 0.4 V 0.4 1.6 ns Dt3 1 VT = 1.5 V 45 55 % 250 250 ps ps Output Impedance Duty Cycle Skew Jitter 1 1 Tsk3 tj cyc-cyc VT = 1.5 V VT = 1.5 V Guarenteed by design, not 100% tested in production. Third party brands and names are the property of their respective owners. 8 ICS9250-25 Preliminary Product Preview Electrical Characteristics - PCI TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS RDSP1 1 VO = VDD*(0.5) 12 55 Ω Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current RDSN1 VOH1 VOL1 IOH1 IOL1 1 VO = VDD*(0.5) 12 IOH = -1 mA 2.4 IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33 VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 30 55 0.55 -33 38 Ω V V mA mA Rise Time tr11 VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns Fall Time 1 VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns 1 VT = 1.5 V 45 55 % 1 VT = 1.5 V VT = 1.5 V 500 500 ps ps Output Impedance Duty Cycle Skew Jitter 1 tf1 dt1 tsk1 tjcyc-cyc Guarenteed by design, not 100% tested in production. Electrical Characteristics - 48M, REF TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS RDSP5 1 VO = VDD*(0.5) 20 60 Ω Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current RDSN5 VOH5 VOL5 IOH5 IOL5 1 VO = VDD*(0.5) IOH = 1 mA IOL = -1 mA VOH @MIN=1 V, VOH@MAX= 3.135 V VOL@MIN=1.95 V, VOL@MIN=0.4 V 20 2.4 60 0.4 -23 27 Ω V V mA mA Rise Time tr5 1 VOL = 0.4 V, VOH = 2.4 V 4 nS Fall Time tf5 1 VOH = 2.4 V, VOL = 0.4 V Duty Cycle dt5 1 Output Impedance Jitter 1 VT = 1.5 V 1 tjcyc-cyc tjcyc-cyc1 1.8 1.7 45 VT = 1.5 V; Fixed Clocks VT = 1.5 V; Ref Clocks Guarenteed by design, not 100% tested in production. Third party brands and names are the property of their respective owners. -29 29 9 4 nS 55 % 500 pS 1000 pS ICS9250-25 Preliminary Product Preview General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ACK ICS (Slave/Receiver) ACK Byte Count Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Stop Bit Notes: 1. 2. 3. 4. 5. 6. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. Third party brands and names are the property of their respective owners. 10 ICS9250-25 Preliminary Product Preview Shared Pin Operation Input/Output Pins Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. The I/O pins designated by (input/output) on the ICS9250-25 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Via to VDD Programming Header 2K Via to Gnd Device Pad 8.2K Clock trace to load Series Term. Res. Fig. 1 Third party brands and names are the property of their respective owners. 11 ICS9250-25 Preliminary Product Preview Power Down Waveform Note 1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz Third party brands and names are the property of their respective owners. 12 ICS9250-25 Preliminary Product Preview 0ns 10ns 20ns 30ns Cycle Repeats CPU 66MHz CPU 100MHz CPU 133MHz SDRAM 100MHz SDRAM 133MHz 3.5V 66MHz PCI 33MHz APIC 33MHz REF 14.318MHz USB 48MHz Group Offset Waveforms Third party brands and names are the property of their respective owners. 13 40ns ICS9250-25 Preliminary Product Preview SYMBOL In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A 2.413 2.794 .095 A1 0.203 0.406 .008 .016 b 0.203 0.343 .008 .0135 c D 0.127 0.254 SEE VARIATIONS .005 .010 SEE VARIATIONS E 10.033 10.668 .395 .420 E1 7.391 7.595 .291 .299 e 0.635 BASIC h 0.381 L 0.508 1.016 SEE VARIATIONS N α 0.635 0° .110 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 8° 0° 8° MIN MAX MIN MAX 18.288 18.542 .720 .730 JEDEC MO-118 DOC# 10-0034 6/1/00 REV B VARIATIONS D mm. N 56 D (inch) Ordering Information ICS9250yF-25-T Example: ICS XXXX y F - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device Third party brands and names are the property of their respective owners. 14 PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.