ICS ICS9248F-151-T

Integrated
Circuit
Systems, Inc.
ICS9248-151
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Pin Configuration
VDDREF
GND
X1
X2
AVDD48
*FS3/48MHz
*FS2/24_48MHz
GND
PCICLK_F
PCICLK0
PCICLK1
GND
PCICLK2
PCICLK3
VDDPCI
PCICLK4
PCICLK5
PCICLK6
GND
PCICLK7
*FS1
*FS0
AGPCLK0
VDDAGP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ICS9248-151
Recommended Application:
VIA Apollo Pro 266 style chipset.
Output Features:
•
3 - CPUs @ 2.5V, up to 200MHz.
•
3 - IOAPIC @ 2.5V, ½ PCI frequency
•
9 - PCI @ 3.3V,
•
1 - 48MHz, @ 3.3V fixed.
•
1 - 24/48MHz @ 3.3V
•
2 - REF @ 3.3V, 14.318MHz.
•
3 - AGP @ 3.3V
Features:
•
Up to 200MHz frequency support
•
Support power management: PCI, CPU stop
and Power Down.
•
Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).
•
Uses external 14.318MHz crystal
Skew Specifications:
•
CPU – CPU: <175ps
•
PCI – PCI: <500ps
•
CPU(early)-PCI: Min=1.0ns, Max=2.5ns
•
CPU Cycle to cycle jitter: < 250ps
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF0
REF1/FS4*
VDDLAPIC
IOAPIC0
IOAPIC1
GND
IOAPIC2
VDDLCPU
GND
CPUCLK0
CPUCLK1
VDDLCPU
GND
CPUCLK2/F
CPU_STOP#*
PCI_STOP#*
PD*
AVDD
GND
SDATA
SCLK
AGPCLK2
AGPCLK1
GND
48-Pin 300mil SSOP
* Internal Pull-up Resistor of 120K to VDD
Block Diagram
Functionality
PLL2
48MHz
24_48MHz
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
2
CPU
DIVDER
Stop
2 CPUCLK (1:0)
CPUCLK2/F
Stop/F
FS (4:0)
PD#
PCI_STOP#
CPU_STOP#
SDATA
SCLK
AGP
DIVDER
3 AGPCLK (2:0)
IOAPIC
DIVDER
3 IOAPIC (2:0)
Control
Logic
REF (1:0)
Config.
Reg.
PCI
DIVDER
Stop
8
PCICLK (7:0)
PCICLK_F
9248-151 Rev B 01/29/01
Third party brands and names are the property of their respective owners.
FS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FS3 FS2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1 FS0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
(MHz)
200.00
190.00
180.00
170.00
166.00
160.00
150.00
145.00
140.00
136.00
130.00
124.00
AG P
(MHz)
80.00
76.00
72.00
68.00
66.40
64.00
75.00
72.50
70.00
68.00
65.00
62.00
PCICLK
(MHz)
40.00
38.00
36.00
34.00
33.20
32.00
37.50
36.25
35.00
34.00
32.50
31.00
66.67
100.00
118.00
133.33
66.67
66.67
78.67
66.67
33.34
33.33
39.33
33.34
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9248-151
Pin Descriptions
PIN NUMBER
1
2, 12, 19, 25,
30, 36, 40, 43
P I N NA M E
VDDREF
TYPE
PWR
DESCRIPTION
Ref, XTAL power supply, nominal 3.3V
GND
PWR
Ground
Crystal input, has internal load cap (36pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (36pF)
Power for 24 & 48MHz output buffers and fixed PLL core.
Frequency select pin. Latched Input. Internal Pull-up to VDD
48MHz output clock
Frequency select pin. Latched Input. Internal Pull-up to VDD
24 or 48MHz output
Ground for 24 & 48MHz output buffers and fixed PLL core.
Free running PCI clock not affected by PCI_STOP# for power
management.
3
X1
IN
4
X2
OUT
5
8
AVDD48MHz
FS3
48MHz
FS2
24_48MHz
AGND48MHz
PWR
IN
OUT
IN
OUT
PWR
9
PCICLK_F
OUT
PCICLK (7:0)
OUT
PCI clock outputs. Syncheronous to CPU clocks with 1-2ns skew
VDDPCI
FS (1:0)1, 2
AGPCLK (2:0)
VDDAGP
SCLK
SDATA
AVDD
PWR
IN
OUT
PWR
IN
I/O
PWR
6
7
20, 18, 17, 16, 14,
13, 11, 10
15
21, 22
27, 26, 23
24
28
29
31
32
PD#
IN
33
PCI_STOP#1
IN
34
CPU_STOP#
IN
35
CPUCLK2/F
OUT
VDDLCPU
CPUCLK (1:0)
IOAPIC (2:0)
VDDLAPIC
FS41, 2
PWR
OUT
OUT
PWR
IN
Supply for PCICLK_F and PCICLK, nominal 3.3V
Frequency select pin. Latched Input. Internal Pull-up to VDD
AGP outputs defined as 2X PCI. These may not be stopped.
Power for AGP clocks
Clock input of I2C input, 5V tolerant input
Data pin for I2C circuitry 5V tolerant
Power for PLL core 3.3V
Asynchronous active low input pin used to power down the
device into a low power state. The internal clocks are disabled
a n d t h e V C O a n d t h e c r y s t a l a r e s t o p p e d . T h e l a t e n cy o f t h e
power down will not be greater than 3ms.
Halts PCICLK clocks at logic 0 level, when input low (In mobile
mode, MODE=0)
This asynchronous input halts CPUCLKs at logic "0" level when
driven low.
CPUCLK either stoppable through CPU_STOP# or free running
depending on I2C selection , 0 = Free Running 1= Stoppable
Supply for CPU clocks 2.5V nominal
CPU clock outputs, Low if CPU_STOP#=Low
IOAPIC clock output. 14.318 MHz Powered by VDDLIOAPIC .
Supply for IOAPIC, 2.5V nominal
Frequency select pin. Latched Input
REF1
OUT
14.318 MHz reference clock.
REF0
OUT
14.318 Mhz reference clock.
37, 41
38, 39
42, 44, 45
46
47
48
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
Third party brands and names are the property of their respective owners.
2
ICS9248-151
General Description
Power Groups
The ICS9248-151 is a single chip clock solution for Desktop
designs. It provides all necessary clock signals for such a
system.
AVDD, AGND = Core PLL
AVDD48, AGND48 = 24, 48MHz and fixed PLL
VDDREF, GNDREF = REF clocks, Xtal
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-151
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I2C interface allows changing functions,
stop clock programming and frequency selection.
Third party brands and names are the property of their respective owners.
3
ICS9248-151
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
Bit 2 Bit 1 Bit 6 Bit 5 Bit 4 CPUCLK AGPCLK
(MHz)
(MHz)
FS4
FS3 FS2 FS1 FS0
0
0
0
0
0
200.00
80.00
0
0
0
0
1
190.00
76.00
0
0
0
1
0
180.00
72.00
0
0
0
1
1
170.00
68.00
0
0
1
0
0
166.00
66.40
0
0
1
0
1
160.00
64.00
0
0
1
1
0
150.00
75.00
0
0
1
1
1
145.00
72.50
0
1
0
0
0
140.00
70.00
0
1
0
0
1
136.00
68.00
0
1
0
1
0
130.00
65.00
0
1
0
1
1
124.00
62.00
0
1
1
0
0
66.67
66.67
0
1
1
0
1
100.00
66.67
0
1
1
1
0
1
1
8
.
0
0
7
8.67
Bit 2,1
Bit 6:4
0
1
1
1
1
133.33
66.67
1
0
0
0
0
66.80
66.80
1
0
0
0
1
100.20
66.80
1
0
0
1
0
115.00
76.67
1
0
0
1
1
133.40
66.70
1
0
1
0
0
66.80
66.80
1
0
1
0
1
100.20
66.80
1
0
1
1
0
110.00
73.33
1
0
1
1
1
133.40
66.70
1
1
0
0
0
105.00
70.00
1
1
0
0
1
90.00
60.00
1
1
0
1
0
85.00
56.67
1
1
0
1
1
78.00
78.00
1
1
1
0
0
66.67
66.67
1
1
1
0
1
100.00
66.67
1
1
1
1
0
75.00
75.00
1
1
1
1
1
133.33
66.67
0 - Frequency is selected by hardware select, Latched Inputs
Bit 3 1 - Frequency is selected by Bit 2, 1 [6:4]
al
Bit 7 10 -- SNporrem
ad Spectrum Enabled ± 0.25% Center Spread
Bit 0 10- -TRriusntantienagll outputs
PWD
PCICLK
(MHz)
40.00
38.00
36.00
34.00
33.20
32.00
37.50
36.25
35.00
34.00
32.50
31.00
33.34
33.33
39.33
33.34
33.40
33.40
38.33
33.35
33.40
33.40
36.67
33.35
35.00
30.00
28.33
39.00
33.34
33.33
37.50
33.34
IOAPIC
(MHz)
20.00
19.00
18.00
17.00
16.60
13.00
18.75
18.12
17.50
17.00
16.25
15.50
16.67
16.66
19.66
16.67
16.70
16.70
19.16
16.67
16.67
16.70
18.33
16.67
17.50
15.00
14.16
19.5
16.67
16.66
18.75
16.67
Note1: Default at power-up will be for latched logic inputs to define frequency, as diplayed by Bit 3.
Third party brands and names are the property of their respective owners.
4
Spread
Precentage
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.75%
+/- 0.75%
+/- 0.25%
+/- 0.75%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.5%
+/- 0.5%
+/- 0.25%
+/- 0.5%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
0 to -0.5%
0 to -0.5%
+/- 0.25%
0 to -0.5%
XXXX
Note1
0
1
0
ICS9248-151
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
DESCRIPTION
BIT
Bit 6
1
SEL_CPUF#;
0=CPUCLK2 will be free running
1=CPUCLK2 will not be free running
(Reserved)
X
FS4#
Bit 4
BIT
PIN#
PWD
Bit 7
35
0
Bit 6
-
Bit 5
-
Bit 7
Bit 5
Bit 4
-
X
FS3#
Bit 3
Bit 3
35
1
CPUCLK2
Bit 2
Bit 2
38
1
CPUCLK1
Bit 1
Bit 1
39
1
CPUCLK0
Bit 0
Bit 0
42
1
IOAPIC2
Byte 3: Active/Inactive Register
(1= enable, 0 = disable)
Bit 7
BIT
PIN#
-
Bit 6
-
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
SEL24_48
0=24MHz 1=48MHz
48MHz
6
7
9
27
26
23
1
24_48MHz
1
PCICLK_F
1
AGPCLK2
1
AGPCLK1
1
AGPCLK0
BIT
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT
PIN# PWD
Bit 7
-
1
(Reserved)
-
1
(Reserved)
Bit 5
44
1
IOAPIC1
Bit 4
45
1
IOAPIC0
Bit 3
-
1
(Reserved)
Bit 2
-
1
(Reserved)
Bit 1
47
1
REF1
Bit 0
48
1
REF0
DESCRIPTION
1
PCICLK7
1
PCICLK6
1
PCICLK5
1
PCICLK4
1
PCICLK3
1
PCICLK2
1
PCICLK1
1
PCICLK0
PIN# PWD
DESCRIPTION
Bit 7
-
1
(Reserved)
Bit 6
-
1
(Reserved)
Bit 5
-
1
(Reserved)
Bit 4
-
1
(Reserved)
Bit 3
-
1
(Reserved)
Bit 2
-
1
(Reserved)
Bit 1
-
1
(Reserved)
Bit 0
-
1
(Reserved)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DESCRIPTION
Bit 6
PWD
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
PWD
DESCRIPTION
X
FS2#
0
PIN#
20
18
17
16
14
13
11
10
PIN#
-
PWD
0
0
0
0
0
1
1
0
DESCRIPTION
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
Note: Don’t write into this register, writing into this
register can cause malfunction
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
Third party brands and names are the property of their respective owners.
5
ICS9248-151
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . . . . .
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .
5.5 V
GND –0.5 V to VDD +0.5 V
0°C to +70°C
115°C
–65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD, VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
Input High Voltage
VIH
Input Low Voltage
VIL
Input High Current
IIH
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
Input Low Current
IIL1
VIN = 0 V; Inputs with pull-up resistors
Input Low Current
IIL2
Operating
IDD3.3OP66 CL = max Capacitive Loads; Select @ 66 MHz
Supply Current
IDD3.3OP100 CL = max Capacitive Loads; Select @ 100 MHz
Power Down Current IDDPowerDown CL = max Capacitive Loads; PD#=Low
VDD = 3.3 V
Input frequency
Fi
Input Capacitance1
CIN
Logic Inputs
CINX
X1 & X2 pins
Transition Time1
TTrans
To first crossing of target Freq.
1
Settling Time
TS
From first crossing to 1% of target Freq.
Clk Stabilization1
TSTAB
From VDD = 3.3 V to 1% target Freq.
Skew
TCPU-PCI
VT=1.5 V; VTL=1.25 V; CPU leads
TCPU-AGP VT=1.5 V; VTL=1.25 V
MIN
2
VSS-0.3
-5
-200
12
27
1
-250
TYP
0.1
2.0
-100
105
110
330
14.318
36
0.9
0.3
<2
1.9
20
MAX UNITS
VDD+0.3
V
0.8
V
µA
5
µA
µA
180
mA
600
16
5
45
2
3
3
2.5
+250
µA
MHz
pF
pF
ms
ms
ms
ns
ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
Operating
IDD2.5OP66 CL = max Capacitive Loads; Select @ 66.65 MHz
Supply Current
IDD2.5OP100 CL = max Capacitive Loads; Select @ 100 MHz
Skew
TCPU-PCI VT=1.5 V; VTL=1.25 V; CPU leads
1
TCPU-AGP VT=1.5 V; VTL=1.25 V
-250
Third party brands and names are the property of their respective owners.
6
TYP
19
25
1.9
20
MAX
72
100
2.5
+250
UNITS
mA
ns
ps
ICS9248-151
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL CONDITIONS
MIN
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
Duty Cycle
Skew
Jitter, Cycle to cycle
RDSP2B
1
VO = VDD*(0.5)
1
VO = VDD*(0.5)
IOH = -8.0 mA
IOL = 12 mA
VOH =1.7 V
VOL = 0.8 V
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
VT = 1.25 V
VT = 1.25 V
VT = 1.25 V
VT = 1.25 V
RDSN2B
VOH2B
VOL2B
IOH2B
IOL2B
1
tr2B
1
tf2B
1
dt2B
1
tsk2B
tjcyc-cyc1
1
tj1σ2B
1
tjabs2B
TYP
MAX UNITS
714
Ω
714
Ω
V
V
mA
mA
ns
ns
%
ps
ps
ps
ps
2
0.23
-250
40
0.95
1
50
40
145
60
160
1.6
1.6
55
175
250
150
+250
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Jitter, One Sigma
Jitter, Absolute
33
0.4
-16
45
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
1
Rise Time
1
Fall Time
1
Duty Cycle
1
Skew
Jitter, Cycle to cycle
Jitter, One Sigma
Jitter, Absolute
1
RDSP1
1
VO = VDD*(0.5)
12
33
55
Ω
1
VO = VDD*(0.5)
IOH = -11 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
12
2.4
33
3.1
0.32
-72
55
55
Ω
V
V
mA
mA
RDSN1
VOH1
VOL1
IOH1
IOL1
41
0.4
-22
tr1
VOL = 0.4 V, VOH = 2.4 V
1.4
2
ns
tf1
VOH = 2.4 V, VOL = 0.4 V
1.4
2
ns
dt1
VT = 1.5 V
45
50
55
%
tsk1
tjcyc-cyc1
1
tj1σ2B
1
tjabs2B
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
-500
350
190
50
140
500
500
150
+500
ps
ps
ps
ps
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
7
ICS9248-151
Electrical Characteristics - IOAPIC
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
Output High Voltage
VOH2B
IOH = -8.0 mA
2
Output Low Voltage
VOL2B
IOL = 12 mA
VOH =1.7 V
Output High Current
IOH2B
VOL = 0.8 V
33
Output Low Current
IOL2B
1
Rise Time
tr2B
VOL = 0.4 V, VOH = 2.0 V
1
VOH = 2.0 V, VOL = 0.4 V
Fall Time
tf2B
1
VT = 1.25 V
45
Duty Cycle
dt2B
1
Skew
tsk2B
VT = 1.25 V
Jitter, Cycle to cycle
tjcyc-cyc1 VT = 1.25 V
1
VT = 1.25 V
Jitter, One Sigma
tj1σ2B
1
VT = 1.25 V
tjabs2B
-500
Jitter, Absolute
TYP
40
1.1
1.2
49
215
175
100
220
MAX UNITS
V
0.4
V
-16
mA
mA
1.6
ns
1.6
ns
55
%
250
ps
500
ps
500
ps
+500
ps
TYP
MAX UNITS
0.3
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - AGP
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
1
Rise Time
1
Fall Time
1
Duty Cycle
Skew
Jitter, Cycle to cycle
Jitter, One Sigma
Jitter, Absolute
1
1
VO = VDD*(0.5)
12
33
55
Ω
1
VO = VDD*(0.5)
IOH = -11 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
12
2.4
55
41
33
3.1
0.32
-72
55
Ω
V
V
mA
mA
tr1
VOL = 0.4 V, VOH = 2.4 V
0.5
1.2
2
ns
tf1
VOH = 2.4 V, VOL = 0.4 V
0.5
1.2
2
ns
VT = 1.4 V, CPU @ 100MHz
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
45
50
60
120
30
90
55
175
300
150
+250
%
ps
ps
ps
ps
RDSP1
RDSN1
VOH1
VOL1
IOH1
IOL1
dt1
tsk1
tjcyc-cyc1
1
tj1σ2B
1
tjabs2B
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
8
-250
0.4
-22
ICS9248-151
Electrical Characteristics - REF, 24MHz, 48MHz
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL CONDITIONS
MIN
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
1
1
Fall Time
Duty Cycle1
Rise Time
1
1
Fall Time
Duty Cycle1
Rise Time
1
1
Fall Time
Duty Cycle1
Jitter, Cycle to cycle
Jitter, One Sigma
Jitter, Absolute
Jitter, Cycle to cycle
Jitter, One Sigma
Jitter, Absolute
1
1
RDSP1
VOH5
VOL5
IOH5
IOL5
VO = VDD*(0.5)
IOH = -12 mA
IOL = 10 mA
VOH = 2.0 V
VOL = 0.8 V
20
2.4
16
TYP
48
3
0.26
-42
31
MAX UNITS
60
0.4
-22
Ω
V
V
mA
mA
tr5
VOL = 0.4 V, VOH = 2.4 V; REF
1.3
4
ns
tf5
VOH = 2.4 V, VOL = 0.4 V; REF
1.5
4
ns
dt5
VT = 1.5 V; REF
53
55
%
tr5
VOL = 0.4 V, VOH = 2.4 V; 48MHz
1.3
4
ns
tf5
1.6
4
ns
dt5
VOH = 2.4 V, VOL = 0.4 V; 48MHz
VT = 1.5 V; 48MHz
51
55
%
tr5
VOL = 0.4 V, VOH = 2.4 V; 24MHz
1.5
4
ns
tf5
VOH = 2.4 V, VOL = 0.4 V; 24MHz
VT = 1.5 V; 24MHz
1.6
4
ns
50
460
120
340
250
75
200
55
1000
500
+1000
500
250
+500
%
ps
ps
ps
ps
ps
ps
dt5
45
45
45
tjcyc-cyc5
tj1s5
tjabs5
VT = 1.5 V; REF
VT = 1.5 V; REF
VT = 1.5 V; REF
-1000
tjcyc-cyc5
tj1s5
tjabs5
VT = 1.5 V; 24, 48MHz
VT = 1.5 V; 24, 48MHz
VT = 1.5 V; 24, 48MHz
-500
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
9
ICS9248-151
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
Dummy Command Code
ACK
ICS (Slave/Receiver)
ACK
Byte Count
Dummy Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
Byte 0
Byte 0
Byte 1
Byte 1
Byte 2
Byte 2
Byte 3
Byte 3
Byte 4
Byte 4
Byte 5
Byte 5
Stop Bit
Notes:
1.
2.
3.
4.
5.
6.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
Third party brands and names are the property of their respective owners.
10
ICS9248-151
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CLK_STOP# is synchronized by the ICS9248-151. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
INTERNAL
CPUCLK
PCICLK
CLK_STOP#
PCI_STOP# (High)
IOAPIC
Notes:
1. All timing is referenced to the internal CPU clock.
2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-151.
3. IOAPIC output is Stopped Glitch Free by CLK_STOP# going low.
4. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-151
CLK_STOP# signal. SDRAM's are controlled as shown.
5. All other clocks continue to run undisturbed.
Third party brands and names are the property of their respective owners.
11
ICS9248-151
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-151. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-151 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width
guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-151 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248-151.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
Third party brands and names are the property of their respective owners.
12
ICS9248-151
Shared Pin Operation Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
The I/O pins designated by (input/output) on the ICS9248151 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K Via to Gnd
Device
Pad
8.2K Clock trace to load
Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
13
ICS9248-151
SYMBOL
In Millimeters
COMMON DIMENSIONS
MIN
MAX
In Inches
COMMON DIMENSIONS
MIN
MAX
A
2.413
2.794
.095
A1
0.203
0.406
.008
.016
b
0.203
0.343
.008
.0135
c
D
0.127
0.254
SEE VARIATIONS
.005
.010
SEE VARIATIONS
E
10.033
10.668
.395
.420
E1
7.391
7.595
.291
.299
e
0.635 BASIC
h
0.381
L
0.508
1.016
SEE VARIATIONS
N
α
0.025 BASIC
0.635
0°
.110
.015
.025
.020
.040
SEE VARIATIONS
8°
0°
8°
MIN
MAX
MIN
MAX
9.398
9.652
.370
.380
34
11.303
11.557
.445
.455
48
15.748
16.002
.620
.630
56
18.288
18.542
.720
.730
64
20.828
21.082
.820
.830
VARIATIONS
N
28
D mm.
D (inch)
Ordering Information
ICS9248yF-151-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
14
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.